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| #define | DWT_CTRL MMIO32(DWT_BASE + 0x00) |
| | DWT Control register Purpose Provides configuration and status information for the DWT block, and used to control features of the block Usage constraints: There are no usage constraints. More...
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| |
| #define | DWT_CYCCNT MMIO32(DWT_BASE + 0x04) |
| | DWT_CYCCNT register Cycle Count Register (Shows or sets the value of the processor cycle counter, CYCCNT) When enabled, CYCCNT increments on each processor clock cycle. More...
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| |
| #define | DWT_CPICNT MMIO32(DWT_BASE + 0x08) |
| | DWT_CPICNT register Purpose Counts additional cycles required to execute multi-cycle instructions and instruction fetch stalls. More...
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| |
| #define | DWT_EXCCNT MMIO32(DWT_BASE + 0x0C) |
| |
| #define | DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10) |
| |
| #define | DWT_LSUCNT MMIO32(DWT_BASE + 0x14) |
| |
| #define | DWT_FOLDCNT MMIO32(DWT_BASE + 0x18) |
| |
| #define | DWT_PCSR MMIO32(DWT_BASE + 0x1C) |
| |
| #define | DWT_COMP(n) MMIO32(DWT_BASE + 0x20 + (n) * 16) |
| |
| #define | DWT_MASK(n) MMIO32(DWT_BASE + 0x24 + (n) * 16) |
| |
| #define | DWT_FUNCTION(n) MMIO32(DWT_BASE + 0x28 + (n) * 16) |
| |
| #define | DWT_LSR MMIO32(DWT_BASE + CORESIGHT_LSR_OFFSET) |
| |
| #define | DWT_LAR MMIO32(DWT_BASE + CORESIGHT_LAR_OFFSET) |
| |
| #define | DWT_CTRL_NUMCOMP_SHIFT 28 |
| |
| #define | DWT_CTRL_NUMCOMP (0x0F << DWT_CTRL_NUMCOMP_SHIFT) |
| |
| #define | DWT_CTRL_NOTRCPKT (1 << 27) |
| |
| #define | DWT_CTRL_NOEXTTRIG (1 << 26) |
| |
| #define | DWT_CTRL_NOCYCCNT (1 << 25) |
| |
| #define | DWT_CTRL_NOPRFCCNT (1 << 24) |
| |
| #define | DWT_CTRL_CYCEVTENA (1 << 22) |
| |
| #define | DWT_CTRL_FOLDEVTENA (1 << 21) |
| |
| #define | DWT_CTRL_LSUEVTENA (1 << 20) |
| |
| #define | DWT_CTRL_SLEEPEVTENA (1 << 19) |
| |
| #define | DWT_CTRL_EXCEVTENA (1 << 18) |
| |
| #define | DWT_CTRL_CPIEVTENA (1 << 17) |
| |
| #define | DWT_CTRL_EXCTRCENA (1 << 16) |
| |
| #define | DWT_CTRL_PCSAMPLENA (1 << 12) |
| |
| #define | DWT_CTRL_SYNCTAP_SHIFT 10 |
| |
| #define | DWT_CTRL_SYNCTAP (3 << DWT_CTRL_SYNCTAP_SHIFT) |
| |
| #define | DWT_CTRL_SYNCTAP_DISABLED (0 << DWT_CTRL_SYNCTAP_SHIFT) |
| |
| #define | DWT_CTRL_SYNCTAP_BIT24 (1 << DWT_CTRL_SYNCTAP_SHIFT) |
| |
| #define | DWT_CTRL_SYNCTAP_BIT26 (2 << DWT_CTRL_SYNCTAP_SHIFT) |
| |
| #define | DWT_CTRL_SYNCTAP_BIT28 (3 << DWT_CTRL_SYNCTAP_SHIFT) |
| |
| #define | DWT_CTRL_CYCTAP (1 << 9) |
| |
| #define | DWT_CTRL_POSTCNT_SHIFT 5 |
| |
| #define | DWT_CTRL_POSTCNT (0x0F << DWT_CTRL_POSTCNT_SHIFT) |
| |
| #define | DWT_CTRL_POSTPRESET_SHIFT 1 |
| |
| #define | DWT_CTRL_POSTPRESET (0x0F << DWT_CTRL_POSTPRESET_SHIFT) |
| |
| #define | DWT_CTRL_CYCCNTENA (1 << 0) |
| | CYCCNTENA Enables the Cycle counter. More...
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| |
| #define | DWT_MASKx_MASK 0x0F |
| |
| #define | DWT_FUNCTIONx_MATCHED (1 << 24) |
| |
| #define | DWT_FUNCTIONx_DATAVADDR1_SHIFT 16 |
| |
| #define | DWT_FUNCTIONx_DATAVADDR1 (15 << DWT_FUNCTIONx_DATAVADDR1_SHIFT) |
| |
| #define | DWT_FUNCTIONx_DATAVADDR0_SHIFT 12 |
| |
| #define | DWT_FUNCTIONx_DATAVADDR0 (15 << DWT_FUNCTIONx_DATAVADDR0_SHIFT) |
| |
| #define | DWT_FUNCTIONx_DATAVSIZE_SHIFT 10 |
| |
| #define | DWT_FUNCTIONx_DATAVSIZE (3 << DWT_FUNCTIONx_DATAVSIZE_SHIFT) |
| |
| #define | DWT_FUNCTIONx_DATAVSIZE_BYTE (0 << DWT_FUNCTIONx_DATAVSIZE_SHIFT) |
| |
| #define | DWT_FUNCTIONx_DATAVSIZE_HALF (1 << DWT_FUNCTIONx_DATAVSIZE_SHIFT) |
| |
| #define | DWT_FUNCTIONx_DATAVSIZE_WORD (2 << DWT_FUNCTIONx_DATAVSIZE_SHIFT) |
| |
| #define | DWT_FUNCTIONx_LNK1ENA (1 << 9) |
| |
| #define | DWT_FUNCTIONx_DATAVMATCH (1 << 8) |
| |
| #define | DWT_FUNCTIONx_CYCMATCH (1 << 7) |
| |
| #define | DWT_FUNCTIONx_EMITRANGE (1 << 5) |
| |
| #define | DWT_FUNCTIONx_FUNCTION 15 |
| |
| #define | DWT_FUNCTIONx_FUNCTION_DISABLED 0 |
| |
1.9.4