libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
smc.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2015 Felix Held <felix-libopencm3@felixheld.de>
5 *
6 * This library is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public License
17 * along with this library. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef LIBOPENCM3_SMC_H
21#define LIBOPENCM3_SMC_H
22
23#include <libopencm3/sam/memorymap.h>
24
25
26/* Chip Select Defines */
27#define SMC_CS_0 0
28#define SMC_CS_1 1
29#define SMC_CS_2 2
30#define SMC_CS_3 3
31
32
33/* --- Static Memory Controller (SMC) registers ---------------------------- */
34
35/* Setup Register */
36#define SMC_SETUP(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) \
37 + 0x00)
38
39/* Pulse Register */
40#define SMC_PULSE(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) \
41 + 0x04)
42
43/* Cycle Register */
44#define SMC_CYCLE(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) \
45 + 0x08)
46
47/* Mode Register */
48#define SMC_MODE(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) \
49 + 0x0C)
50
51/* Off Chip Memory Scrambling Mode Register */
52#define SMC_OCMS MMIO32(SMC_BASE + 0x80)
53
54/* Off Chip Memory Scrambling KEY1 Register */
55#define SMC_KEY1 MMIO32(SMC_BASE + 0x84)
56
57/* Off Chip Memory Scrambling KEY2 Register */
58#define SMC_KEY2 MMIO32(SMC_BASE + 0x88)
59
60/* Write Protect Mode Register */
61#define SMC_WPMR MMIO32(SMC_BASE + 0xE4)
62
63/* Write Protect Status Register */
64#define SMC_WPSR MMIO32(SMC_BASE + 0xE8)
65
66
67/* --- Register contents --------------------------------------------------- */
68
69
70/* --- SMC Setup Register (SMC_SETUPx) ------------------------------------- */
71
72/* NCS Setup length in Read access */
73#define SMC_SETUP_NCS_RD_SETUP_SHIFT 24
74#define SMC_SETUP_NCS_RD_SETUP_MASK (0x3F << SMC_SETUP_NCS_RD_SETUP_SHIFT)
75
76/* NRD Setup length */
77#define SMC_SETUP_NRD_SETUP_SHIFT 16
78#define SMC_SETUP_NRD_SETUP_MASK (0x3F << SMC_SETUP_NRD_SETUP_SHIFT)
79
80/* NCS Setup length in Write access */
81#define SMC_SETUP_NCS_WR_SETUP_SHIFT 8
82#define SMC_SETUP_NCS_WR_SETUP_MASK (0x3F << SMC_SETUP_NCS_WR_SETUP_SHIFT)
83
84/* NWE Setup Length */
85#define SMC_SETUP_NWE_SETUP_SHIFT 0
86#define SMC_SETUP_NWE_SETUP_MASK (0x3F << SMC_SETUP_NWE_SETUP_SHIFT)
87
88
89/* --- SMC Pulse Register (SMC_PULSEx) ------------------------------------- */
90
91/* NCS Pulse Length in READ Access */
92#define SMC_PULSE_NCS_RD_PULSE_SHIFT 24
93#define SMC_PULSE_NCS_RD_PULSE_MASK (0x7F << SMC_PULSE_NCS_RD_PULSE_SHIFT)
94
95/* NRD Pulse Length */
96#define SMC_PULSE_NRD_PULSE_SHIFT 16
97#define SMC_PULSE_NRD_PULSE_MASK (0x7F << SMC_PULSE_NRD_PULSE_SHIFT)
98
99/* NCS Pulse Length in WRITE Access */
100#define SMC_PULSE_NCS_WR_PULSE_SHIFT 8
101#define SMC_PULSE_NCS_WR_PULSE_MASK (0x7F << SMC_PULSE_NCS_WR_PULSE_SHIFT)
102
103/* NWE Pulse Length */
104#define SMC_PULSE_NWE_PULSE_SHIFT 0
105#define SMC_PULSE_NWE_PULSE_MASK (0x7F << SMC_PULSE_NWE_PULSE_SHIFT)
106
107
108/* --- SMC Cycle Register (SMC_CYCLEx) ------------------------------------- */
109
110/* Total Read Cycle Length */
111#define SMC_CYCLE_NRD_CYCLE_SHIFT 16
112#define SMC_CYCLE_NRD_CYCLE_MASK (0x1FF << SMC_CYCLE_NRD_CYCLE_SHIFT)
113
114/* Total Write Cycle Length */
115#define SMC_CYCLE_NWE_CYCLE_SHIFT 0
116#define SMC_CYCLE_NWE_CYCLE_MASK (0x1FF << SMC_CYCLE_NWE_CYCLE_SHIFT)
117
118
119/* --- SMC MODE Register (SMC_MODEx) --------------------------------------- */
120
121/* Page Size */
122#define SMC_MODE_PS_SHIFT 28
123#define SMC_MODE_PS_MASK (0x03 << SMC_MODE_PS_SHIFT)
124
125/* Page Size Values */
126#define SMC_MODE_PS_4_BYTE (0x00 << SMC_MODE_PS_SHIFT)
127#define SMC_MODE_PS_8_BYTE (0x01 << SMC_MODE_PS_SHIFT)
128#define SMC_MODE_PS_16_BYTE (0x02 << SMC_MODE_PS_SHIFT)
129#define SMC_MODE_PS_32_BYTE (0x03 << SMC_MODE_PS_SHIFT)
130
131/* Page Mode Enabled */
132#define SMC_MODE_PMEN (1 << 24)
133
134/* TDF Optimization */
135#define SMC_MODE_TDF_MODE (1 << 20)
136
137/* Data Float Time */
138#define SMC_MODE_TDF_CYCLES_SHIFT 16
139#define SMC_MODE_TDF_CYCLES_MASK (0x0F << SMC_MODE_TDF_CYCLES_SHIFT)
140
141/* Data Bus Width */
142#define SMC_MODE_DBW_SHIFT 12
143#define SMC_MODE_DBW_MASK (0x03 << SMC_MODE_DBW_SHIFT)
144
145/* Data Bus Width Values */
146#define SMC_MODE_DBW_8_BIT (0x00 << SMC_MODE_DBW_SHIFT)
147#define SMC_MODE_DBW_16_BIT (0x01 << SMC_MODE_DBW_SHIFT)
148#define SMC_MODE_DBW_32_BIT (0x02 << SMC_MODE_DBW_SHIFT)
149
150/* NWAIT Mode */
151#define SMC_MODE_EXNW_MODE_SHIFT 4
152#define SMC_MODE_EXNW_MODE_MASK (0x03 << SMC_MODE_EXNW_MODE_SHIFT)
153
154/* NWAIT Mode Values */
155#define SMC_MODE_EXNW_MODE_DISABLED (0x00 << SMC_MODE_EXNW_MODE_SHIFT)
156#define SMC_MODE_EXNW_MODE_FROZEN (0x02 << SMC_MODE_EXNW_MODE_SHIFT)
157#define SMC_MODE_EXNW_MODE_READY (0x03 << SMC_MODE_EXNW_MODE_SHIFT)
158
159/* Write Mode */
160#define SMC_MODE_WRITE_MODE (1 << 1)
161
162/* Read Mode */
163#define SMC_MODE_READ_MODE (1 << 0)
164
165
166/* --- SMC OCMS Mode Register (SMC_OCMS) ----------------------------------- */
167
168/* Chip Select 3 Scrambling Enable */
169#define SMC_OCMS_CS3SE (1 << 19)
170
171/* Chip Select 2 Scrambling Enable */
172#define SMC_OCMS_CS2SE (1 << 18)
173
174/* Chip Select 1 Scrambling Enable */
175#define SMC_OCMS_CS1SE (1 << 17)
176
177/* Chip Select 0 Scrambling Enable */
178#define SMC_OCMS_CS0SE (1 << 16)
179
180/* Static Memory Controller Scrambling Enable */
181#define SMC_OCMS_SMSE (1 << 0)
182
183
184/* --- SMC Write Protect Mode Register (SMC_WPMR) -------------------------- */
185
186/* Write Protect Key */
187#define SMC_WPMR_WPKEY_SHIFT 8
188#define SMC_WPMR_WPKEY_KEY (0x534D43 << SMC_WPMR_WPKEY_SHIFT)
189
190/* Write Protect Enable */
191#define SMC_WPMR_WPEN (1 << 0)
192
193
194/* --- SMC Write Protect Status Register (SMC_WPSR) ------------------------ */
195
196/* Write Protection Violation Source */
197#define SMC_WPSR_WP_VSRC_SHIFT 8
198#define SMC_WPSR_WP_VSRC_MASK (0xFFFF << SMC_WPSR_WP_VSRC_SHIFT)
199
200/* Write Protect Enable */
201#define SMC_WPSR_WPVS (1 << 0)
202
203
204#endif