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◆ EEFC
◆ EEFC0
◆ EEFC1
◆ EEFC_FCR
#define EEFC_FCR |
( |
|
port | ) |
MMIO32((port) + 0x04) |
◆ EEFC_FCR_FARG_MASK
#define EEFC_FCR_FARG_MASK (0xFFFF << 8) |
◆ EEFC_FCR_FCMD_CGPB
#define EEFC_FCR_FCMD_CGPB (0x0C << 0) |
◆ EEFC_FCR_FCMD_CLB
#define EEFC_FCR_FCMD_CLB (0x09 << 0) |
◆ EEFC_FCR_FCMD_EA
#define EEFC_FCR_FCMD_EA (0x05 << 0) |
◆ EEFC_FCR_FCMD_EWP
#define EEFC_FCR_FCMD_EWP (0x03 << 0) |
◆ EEFC_FCR_FCMD_EWPL
#define EEFC_FCR_FCMD_EWPL (0x04 << 0) |
◆ EEFC_FCR_FCMD_GETD
#define EEFC_FCR_FCMD_GETD (0x00 << 0) |
◆ EEFC_FCR_FCMD_GGPB
#define EEFC_FCR_FCMD_GGPB (0x0D << 0) |
◆ EEFC_FCR_FCMD_GLB
#define EEFC_FCR_FCMD_GLB (0x0A << 0) |
◆ EEFC_FCR_FCMD_MASK
#define EEFC_FCR_FCMD_MASK (0xFF << 0) |
◆ EEFC_FCR_FCMD_SGPB
#define EEFC_FCR_FCMD_SGPB (0x0B << 0) |
◆ EEFC_FCR_FCMD_SLB
#define EEFC_FCR_FCMD_SLB (0x08 << 0) |
◆ EEFC_FCR_FCMD_SPUI
#define EEFC_FCR_FCMD_SPUI (0x0F << 0) |
◆ EEFC_FCR_FCMD_STUI
#define EEFC_FCR_FCMD_STUI (0x0E << 0) |
◆ EEFC_FCR_FCMD_WP
#define EEFC_FCR_FCMD_WP (0x01 << 0) |
◆ EEFC_FCR_FCMD_WPL
#define EEFC_FCR_FCMD_WPL (0x02 << 0) |
◆ EEFC_FCR_FKEY
#define EEFC_FCR_FKEY (0x5A << 24) |
◆ EEFC_FMR
#define EEFC_FMR |
( |
|
port | ) |
MMIO32((port) + 0x00) |
◆ EEFC_FMR_FAM
#define EEFC_FMR_FAM (0x01 << 24) |
◆ EEFC_FMR_FRDY
#define EEFC_FMR_FRDY (0x01 << 0) |
◆ EEFC_FMR_FWS_MASK
#define EEFC_FMR_FWS_MASK (0x0F << 8) |
◆ EEFC_FRR
#define EEFC_FRR |
( |
|
port | ) |
MMIO32((port) + 0x0C) |
◆ EEFC_FSR
#define EEFC_FSR |
( |
|
port | ) |
MMIO32((port) + 0x08) |
◆ EEFC_FSR_FCMDE
#define EEFC_FSR_FCMDE (0x01 << 1) |
◆ EEFC_FSR_FLOCKE
#define EEFC_FSR_FLOCKE (0x01 << 2) |
◆ EEFC_FSR_FRDY
#define EEFC_FSR_FRDY (0x01 << 0) |
◆ eefc_set_latency()
static void eefc_set_latency |
( |
uint8_t |
wait | ) |
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inlinestatic |