libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
Collaboration diagram for ADC registers:

Macros

#define ADC_ISR(adc)   MMIO32((adc) + 0x00)
 ADC interrupt and status register. More...
 
#define ADC_IER(adc)   MMIO32((adc) + 0x04)
 Interrupt Enable Register. More...
 
#define ADC_CR(adc)   MMIO32((adc) + 0x08)
 Control Register. More...
 
#define ADC_CFGR1(adc)   MMIO32((adc) + 0x0C)
 Configuration Register 1. More...
 
#define ADC_CFGR2(adc)   MMIO32((adc) + 0x10)
 Configuration Register 2. More...
 
#define ADC_SMPR1(adc)   MMIO32((adc) + 0x14)
 Sample Time Register 1. More...
 
#define ADC_TR1(adc)   MMIO32((adc) + 0x20)
 Watchdog Threshold Register 1. More...
 
#define ADC_DR(adc)   MMIO32((adc) + 0x40)
 Regular Data Register. More...
 
#define ADC_CCR(adc)   MMIO32((adc) + 0x300 + 0x8)
 Common Configuration register. More...
 
#define ADC_CHSELR(adc)   MMIO32((adc) + 0x28)
 Channel Select Register. More...
 

Detailed Description

Macro Definition Documentation

◆ ADC_CCR

#define ADC_CCR (   adc)    MMIO32((adc) + 0x300 + 0x8)

Common Configuration register.

Definition at line 60 of file adc_common_v2.h.

◆ ADC_CFGR1

#define ADC_CFGR1 (   adc)    MMIO32((adc) + 0x0C)

Configuration Register 1.

Definition at line 48 of file adc_common_v2.h.

◆ ADC_CFGR2

#define ADC_CFGR2 (   adc)    MMIO32((adc) + 0x10)

Configuration Register 2.

Definition at line 50 of file adc_common_v2.h.

◆ ADC_CHSELR

#define ADC_CHSELR (   adc)    MMIO32((adc) + 0x28)

Channel Select Register.

Definition at line 49 of file adc_common_v2_single.h.

◆ ADC_CR

#define ADC_CR (   adc)    MMIO32((adc) + 0x08)

Control Register.

Definition at line 46 of file adc_common_v2.h.

◆ ADC_DR

#define ADC_DR (   adc)    MMIO32((adc) + 0x40)

Regular Data Register.

Definition at line 56 of file adc_common_v2.h.

◆ ADC_IER

#define ADC_IER (   adc)    MMIO32((adc) + 0x04)

Interrupt Enable Register.

Definition at line 44 of file adc_common_v2.h.

◆ ADC_ISR

#define ADC_ISR (   adc)    MMIO32((adc) + 0x00)

ADC interrupt and status register.

Definition at line 42 of file adc_common_v2.h.

◆ ADC_SMPR1

#define ADC_SMPR1 (   adc)    MMIO32((adc) + 0x14)

Sample Time Register 1.

Definition at line 52 of file adc_common_v2.h.

◆ ADC_TR1

#define ADC_TR1 (   adc)    MMIO32((adc) + 0x20)

Watchdog Threshold Register 1.

Definition at line 54 of file adc_common_v2.h.