Cortex M0/M3/M4 System Interrupts

IRQ numbers -3 and -6 to -9 are reserved. More...

Collaboration diagram for Cortex M0/M3/M4 System Interrupts:

Macros
#define	NVIC_NMI_IRQ   -14
#define	NVIC_HARD_FAULT_IRQ   -13
#define	NVIC_SV_CALL_IRQ   -5
#define	NVIC_PENDSV_IRQ   -2
#define	NVIC_SYSTICK_IRQ   -1

Detailed Description

IRQ numbers -3 and -6 to -9 are reserved.

Macro Definition Documentation

NVIC_HARD_FAULT_IRQ

#define NVIC_HARD_FAULT_IRQ   -13

Definition at line 121 of file cm3/nvic.h.

NVIC_NMI_IRQ

#define NVIC_NMI_IRQ   -14

Definition at line 120 of file cm3/nvic.h.

NVIC_PENDSV_IRQ

#define NVIC_PENDSV_IRQ   -2

Definition at line 139 of file cm3/nvic.h.

NVIC_SV_CALL_IRQ

#define NVIC_SV_CALL_IRQ   -5

Definition at line 131 of file cm3/nvic.h.

NVIC_SYSTICK_IRQ

#define NVIC_SYSTICK_IRQ   -1

Definition at line 140 of file cm3/nvic.h.