libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
timer_common_f24.h
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1/** @addtogroup timer_defines
2
3@author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
4
5*/
6
7/*
8 * This file is part of the libopencm3 project.
9 *
10 * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
11 *
12 * This library is free software: you can redistribute it and/or modify
13 * it under the terms of the GNU Lesser General Public License as published by
14 * the Free Software Foundation, either version 3 of the License, or
15 * (at your option) any later version.
16 *
17 * This library is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU Lesser General Public License for more details.
21 *
22 * You should have received a copy of the GNU Lesser General Public License
23 * along with this library. If not, see <http://www.gnu.org/licenses/>.
24 */
25
26/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H
27The order of header inclusion is important. timer.h includes the device
28specific memorymap.h header before including this header file.*/
29
30#pragma once
32
33/*
34 * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
35 * CNT, ARR, CCR1, CCR2, CCR3, CCR4
36 */
37
38/* Timer 2/5 option register (TIMx_OR) */
39#define TIM_OR(tim_base) MMIO32((tim_base) + 0x50)
40#define TIM2_OR TIM_OR(TIM2)
41#define TIM5_OR TIM_OR(TIM5)
42
43/* --- TIM2_OR values ---------------------------------------------------- */
44
45/* ITR1_RMP */
46/****************************************************************************/
47/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal
48Trigger 1 Remap
49
50Only available in F2 and F4 series.
51@ingroup timer_defines
52
53@{*/
54/** Internal Trigger 1 remapped to timer 8 trigger out */
55#define TIM2_OR_ITR1_RMP_TIM8_TRGOU (0x0 << 10)
56/** Internal Trigger 1 remapped to PTP trigger out */
57#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10)
58/** Internal Trigger 1 remapped to USB OTG FS SOF */
59#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
60/** Internal Trigger 1 remapped to USB OTG HS SOF */
61#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)
62/**@}*/
63#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10)
64
65/* --- TIM5_OR values ---------------------------------------------------- */
66
67/* ITR4_RMP */
68/****************************************************************************/
69/** @defgroup tim5_opt_trigger_remap TIM5_OR Timer 5 Option Register Internal Trigger 4 Remap
70
71Only available in F2 and F4 series.
72@ingroup timer_defines
73
74@{*/
75/** Internal Trigger 4 remapped to GPIO (see reference manual) */
76#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6)
77/** Internal Trigger 4 remapped to LSI internal clock */
78#define TIM5_OR_TI4_RMP_LSI (0x1 << 6)
79/** Internal Trigger 4 remapped to LSE internal clock */
80#define TIM5_OR_TI4_RMP_LSE (0x2 << 6)
81/** Internal Trigger 4 remapped to RTC output event */
82#define TIM5_OR_TI4_RMP_RTC (0x3 << 6)
83/**@}*/
84#define TIM5_OR_TI4_RMP_MASK (0x3 << 6)
85
86/** Input Capture input polarity */
91};
92
93/* --- Function prototypes ------------------------------------------------- */
94
96
97void timer_set_option(uint32_t timer_peripheral, uint32_t option);
98void timer_ic_set_polarity(uint32_t timer, enum tim_ic_id ic,
99 enum tim_ic_pol pol);
100
#define END_DECLS
Definition: common.h:34
#define BEGIN_DECLS
Definition: common.h:33
tim_ic_id
Input Capture channel designators.
void timer_ic_set_polarity(uint32_t timer, enum tim_ic_id ic, enum tim_ic_pol pol)
Set Input Polarity.
tim_ic_pol
Input Capture input polarity.
@ TIM_IC_FALLING
@ TIM_IC_RISING
@ TIM_IC_BOTH
void timer_set_option(uint32_t timer_peripheral, uint32_t option)