#include <stdbool.h>
#include <libopencm3/stm32/common/rcc_common_all.h>

Include dependency graph for f3/rcc.h:

Data Structures
struct	rcc_clock_scale

Macros
#define	RCC_CR MMIO32(RCC_BASE + 0x00)

#define	RCC_CFGR MMIO32(RCC_BASE + 0x04)

#define	RCC_CIR MMIO32(RCC_BASE + 0x08)

#define	RCC_APB2RSTR MMIO32(RCC_BASE + 0x0C)

#define	RCC_APB1RSTR MMIO32(RCC_BASE + 0x10)

#define	RCC_AHBENR MMIO32(RCC_BASE + 0x14)

#define	RCC_APB2ENR MMIO32(RCC_BASE + 0x18)

#define	RCC_APB1ENR MMIO32(RCC_BASE + 0x1C)

#define	RCC_BDCR MMIO32(RCC_BASE + 0x20)

#define	RCC_CSR MMIO32(RCC_BASE + 0x24)

#define	RCC_AHBRSTR MMIO32(RCC_BASE + 0x28)

#define	RCC_CFGR2 MMIO32(RCC_BASE + 0x2C)

#define	RCC_CFGR3 MMIO32(RCC_BASE + 0x30)

#define	RCC_CR_PLLRDY (1 << 25)

#define	RCC_CR_PLLON (1 << 24)

#define	RCC_CR_CSSON (1 << 19)

#define	RCC_CR_HSEBYP (1 << 18)

#define	RCC_CR_HSERDY (1 << 17)

#define	RCC_CR_HSEON (1 << 16)

#define	RCC_CR_HSIRDY (1 << 1)

#define	RCC_CR_HSION (1 << 0)

#define	RCC_CFGR_MCOF (1 << 28)

#define	RCC_CFGR_I2SSRC (1 << 23)

#define	RCC_CFGR_USBPRES (1 << 22)

#define	RCC_CFGR_PLLXTPRE (1 << 17)

#define	RCC_CFGR_PLLSRC (1 << 16)

#define	RCC_CFGR_MCO_SHIFT 24

#define	RCC_CFGR_MCO_MASK 0x7

#define	RCC_CFGR_MCO_NOCLK 0x0

#define	RCC_CFGR_MCO_LSI 0x2

#define	RCC_CFGR_MCO_LSE 0x3

#define	RCC_CFGR_MCO_SYSCLK 0x4

#define	RCC_CFGR_MCO_HSI 0x5

#define	RCC_CFGR_MCO_HSE 0x6

#define	RCC_CFGR_MCO_PLL 0x7

#define	RCC_CFGR_PLLSRC_HSI_DIV2 0

#define	RCC_CFGR_PLLSRC_HSE_PREDIV 1

#define	RCC_CFGR_PLLMUL_SHIFT 18

#define	RCC_CFGR_PLLMUL_MASK 0xF

#define	RCC_CFGR_PLLMUL_MUL2 0x0

#define	RCC_CFGR_PLLMUL_MUL3 0x1

#define	RCC_CFGR_PLLMUL_MUL4 0x2

#define	RCC_CFGR_PLLMUL_MUL5 0x3

#define	RCC_CFGR_PLLMUL_MUL6 0x4

#define	RCC_CFGR_PLLMUL_MUL7 0x5

#define	RCC_CFGR_PLLMUL_MUL8 0x6

#define	RCC_CFGR_PLLMUL_MUL9 0x7

#define	RCC_CFGR_PLLMUL_MUL10 0x8

#define	RCC_CFGR_PLLMUL_MUL11 0x9

#define	RCC_CFGR_PLLMUL_MUL12 0xA

#define	RCC_CFGR_PLLMUL_MUL13 0xB

#define	RCC_CFGR_PLLMUL_MUL14 0xC

#define	RCC_CFGR_PLLMUL_MUL15 0xD

#define	RCC_CFGR_PLLMUL_MUL16 0xE

#define	RCC_CFGR_PPRE2_SHIFT 11

#define	RCC_CFGR_PPRE2_MASK 0x7

#define	RCC_CFGR_PPRE1_SHIFT 8

#define	RCC_CFGR_PPRE1_MASK 0x7

#define	RCC_CFGR_PPRE_NODIV 0x0

#define	RCC_CFGR_PPRE_DIV2 0x4

#define	RCC_CFGR_PPRE_DIV4 0x5

#define	RCC_CFGR_PPRE_DIV8 0x6

#define	RCC_CFGR_PPRE_DIV16 0x7

#define	RCC_CFGR_HPRE_SHIFT 4

#define	RCC_CFGR_HPRE_MASK 0xf

#define	RCC_CFGR_HPRE_NODIV 0x0

#define	RCC_CFGR_HPRE_DIV2 0x8

#define	RCC_CFGR_HPRE_DIV4 0x9

#define	RCC_CFGR_HPRE_DIV8 0xA

#define	RCC_CFGR_HPRE_DIV16 0xB

#define	RCC_CFGR_HPRE_DIV64 0xC

#define	RCC_CFGR_HPRE_DIV128 0xD

#define	RCC_CFGR_HPRE_DIV256 0xE

#define	RCC_CFGR_HPRE_DIV512 0xF

#define	RCC_CFGR_SWS_SHIFT 2

#define	RCC_CFGR_SWS_MASK 0x3

#define	RCC_CFGR_SWS_HSI 0x0

#define	RCC_CFGR_SWS_HSE 0x1

#define	RCC_CFGR_SWS_PLL 0x2

#define	RCC_CFGR_SW_SHIFT 0

#define	RCC_CFGR_SW_HSI 0x0

#define	RCC_CFGR_SW_HSE 0x1

#define	RCC_CFGR_SW_PLL 0x2

#define	RCC_CFGR_PPRE2_DIV_NONE 0x0

#define	RCC_CFGR_PPRE2_DIV_2 0x4

#define	RCC_CFGR_PPRE2_DIV_4 0x5

#define	RCC_CFGR_PPRE2_DIV_8 0x6

#define	RCC_CFGR_PPRE2_DIV_16 0x7

#define	RCC_CFGR_PPRE1_DIV_NONE 0x0

#define	RCC_CFGR_PPRE1_DIV_2 0x4

#define	RCC_CFGR_PPRE1_DIV_4 0x5

#define	RCC_CFGR_PPRE1_DIV_8 0x6

#define	RCC_CFGR_PPRE1_DIV_16 0x7

#define	RCC_CFGR_HPRE_DIV_NONE 0x0

#define	RCC_CFGR_HPRE_DIV_2 0x8

#define	RCC_CFGR_HPRE_DIV_4 0x9

#define	RCC_CFGR_HPRE_DIV_8 0xA

#define	RCC_CFGR_HPRE_DIV_16 0xB

#define	RCC_CFGR_HPRE_DIV_64 0xC

#define	RCC_CFGR_HPRE_DIV_128 0xD

#define	RCC_CFGR_HPRE_DIV_256 0xE

#define	RCC_CFGR_HPRE_DIV_512 0xF

#define	RCC_CIR_CSSC (1 << 23)

#define	RCC_CIR_PLLRDYC (1 << 20)

#define	RCC_CIR_HSERDYC (1 << 19)

#define	RCC_CIR_HSIRDYC (1 << 18)

#define	RCC_CIR_LSERDYC (1 << 17)

#define	RCC_CIR_LSIRDYC (1 << 16)

#define	RCC_CIR_PLLRDYIE (1 << 12)

#define	RCC_CIR_HSERDYIE (1 << 11)

#define	RCC_CIR_HSIRDYIE (1 << 10)

#define	RCC_CIR_LSERDYIE (1 << 9)

#define	RCC_CIR_LSIRDYIE (1 << 8)

#define	RCC_CIR_CSSF (1 << 7)

#define	RCC_CIR_PLLRDYF (1 << 4)

#define	RCC_CIR_HSERDYF (1 << 3)

#define	RCC_CIR_HSIRDYF (1 << 2)

#define	RCC_CIR_LSERDYF (1 << 1)

#define	RCC_CIR_LSIRDYF (1 << 0)

#define	RCC_APB2RSTR_TIM20RST (1 << 20)

#define	RCC_APB2RSTR_TIM17RST (1 << 18)

#define	RCC_APB2RSTR_TIM16RST (1 << 17)

#define	RCC_APB2RSTR_TIM15RST (1 << 16)

#define	RCC_APB2RSTR_SPI4RST (1 << 15)

#define	RCC_APB2RSTR_USART1RST (1 << 14)

#define	RCC_APB2RSTR_TIM8RST (1 << 13)

#define	RCC_APB2RSTR_SPI1RST (1 << 12)

#define	RCC_APB2RSTR_TIM1RST (1 << 11)

#define	RCC_APB2RSTR_SYSCFGRST (1 << 0)

#define	RCC_APB1RSTR_I2C3RST (1 << 30)

#define	RCC_APB1RSTR_DAC1RST (1 << 29)

#define	RCC_APB1RSTR_PWRRST (1 << 28)

#define	RCC_APB1RSTR_DAC2RST (1 << 26)

#define	RCC_APB1RSTR_CAN1RST (1 << 25)

#define	RCC_APB1RSTR_USBRST (1 << 23)

#define	RCC_APB1RSTR_I2C2RST (1 << 22)

#define	RCC_APB1RSTR_I2C1RST (1 << 21)

#define	RCC_APB1RSTR_UART5RST (1 << 20)

#define	RCC_APB1RSTR_UART4RST (1 << 19)

#define	RCC_APB1RSTR_USART3RST (1 << 18)

#define	RCC_APB1RSTR_USART2RST (1 << 17)

#define	RCC_APB1RSTR_SPI3RST (1 << 15)

#define	RCC_APB1RSTR_SPI2RST (1 << 14)

#define	RCC_APB1RSTR_WWDGRST (1 << 11)

#define	RCC_APB1RSTR_TIM7RST (1 << 5)

#define	RCC_APB1RSTR_TIM6RST (1 << 4)

#define	RCC_APB1RSTR_TIM4RST (1 << 2)

#define	RCC_APB1RSTR_TIM3RST (1 << 1)

#define	RCC_APB1RSTR_TIM2RST (1 << 0)

#define	RCC_AHBENR_ADC34EN (1 << 29)

#define	RCC_AHBENR_ADC12EN (1 << 28)

#define	RCC_AHBENR_TSCEN (1 << 24)

#define	RCC_AHBENR_IOPGEN (1 << 23)

#define	RCC_AHBENR_IOPFEN (1 << 22)

#define	RCC_AHBENR_IOPEEN (1 << 21)

#define	RCC_AHBENR_IOPDEN (1 << 20)

#define	RCC_AHBENR_IOPCEN (1 << 19)

#define	RCC_AHBENR_IOPBEN (1 << 18)

#define	RCC_AHBENR_IOPAEN (1 << 17)

#define	RCC_AHBENR_IOPHEN (1 << 16)

#define	RCC_AHBENR_CRCEN (1 << 6)

#define	RCC_AHBENR_FMCEN (1 << 5)

#define	RCC_AHBENR_FLITFEN (1 << 4)

#define	RCC_AHBENR_SRAMEN (1 << 2)

#define	RCC_AHBENR_DMA2EN (1 << 1)

#define	RCC_AHBENR_DMA1EN (1 << 0)

#define	RCC_APB2ENR_TIM20EN (1 << 20)

#define	RCC_APB2ENR_TIM17EN (1 << 18)

#define	RCC_APB2ENR_TIM16EN (1 << 17)

#define	RCC_APB2ENR_TIM15EN (1 << 16)

#define	RCC_APB2ENR_SPI4EN (1 << 15)

#define	RCC_APB2ENR_USART1EN (1 << 14)

#define	RCC_APB2ENR_TIM8EN (1 << 13)

#define	RCC_APB2ENR_SPI1EN (1 << 12)

#define	RCC_APB2ENR_TIM1EN (1 << 11)

#define	RCC_APB2ENR_SYSCFGEN (1 << 0)

#define	RCC_APB1ENR_I2C3EN (1 << 30)

#define	RCC_APB1ENR_DAC1EN (1 << 29)

#define	RCC_APB1ENR_PWREN (1 << 28)

#define	RCC_APB1ENR_DAC2EN (1 << 26)

#define	RCC_APB1ENR_CANEN (1 << 25)

#define	RCC_APB1ENR_USBEN (1 << 23)

#define	RCC_APB1ENR_I2C2EN (1 << 22)

#define	RCC_APB1ENR_I2C1EN (1 << 21)

#define	RCC_APB1ENR_USART5EN (1 << 20)

#define	RCC_APB1ENR_USART4EN (1 << 19)

#define	RCC_APB1ENR_USART3EN (1 << 18)

#define	RCC_APB1ENR_USART2EN (1 << 17)

#define	RCC_APB1ENR_SPI3EN (1 << 15)

#define	RCC_APB1ENR_SPI2EN (1 << 14)

#define	RCC_APB1ENR_WWDGEN (1 << 11)

#define	RCC_APB1ENR_TIM7EN (1 << 5)

#define	RCC_APB1ENR_TIM6EN (1 << 4)

#define	RCC_APB1ENR_TIM4EN (1 << 2)

#define	RCC_APB1ENR_TIM3EN (1 << 1)

#define	RCC_APB1ENR_TIM2EN (1 << 0)

#define	RCC_BDCR_BDRST (1 << 16)

#define	RCC_BDCR_RTCEN (1 << 15)

#define	RCC_BDCR_LSEBYP (1 << 2)

#define	RCC_BDCR_LSERDY (1 << 1)

#define	RCC_BDCR_LSEON (1 << 0)

#define	RCC_CSR_LPWRRSTF (1 << 31)

#define	RCC_CSR_WWDGRSTF (1 << 30)

#define	RCC_CSR_IWDGRSTF (1 << 29)

#define	RCC_CSR_SFTRSTF (1 << 28)

#define	RCC_CSR_PORRSTF (1 << 27)

#define	RCC_CSR_PINRSTF (1 << 26)

#define	RCC_CSR_OBLRSTF (1 << 25)

#define	RCC_CSR_RMVF (1 << 24)

#define	RCC_CSR_LSIRDY (1 << 1)

#define	RCC_CSR_LSION (1 << 0)

#define	RCC_AHBRSTR_ADC34RST (1 << 29)

#define	RCC_AHBRSTR_ADC12RST (1 << 28)

#define	RCC_AHBRSTR_TSCRST (1 << 24)

#define	RCC_AHBRSTR_IOPGRST (1 << 23)

#define	RCC_AHBRSTR_IOPFRST (1 << 22)

#define	RCC_AHBRSTR_IOPERST (1 << 21)

#define	RCC_AHBRSTR_IOPDRST (1 << 20)

#define	RCC_AHBRSTR_IOPCRST (1 << 19)

#define	RCC_AHBRSTR_IOPBRST (1 << 18)

#define	RCC_AHBRSTR_IOPARST (1 << 17)

#define	RCC_AHBRSTR_IOPHRST (1 << 16)

#define	RCC_AHBRSTR_FMCRST (1 << 5)

#define	RCC_CFGR2_ADC34PRES_SHIFT 9

#define	RCC_CFGR2_ADC12PRES_SHIFT 4

#define	RCC_CFGR2_ADCxPRES_MASK 0x1f

#define	RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_1 0x10

#define	RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_2 0x11

#define	RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_4 0x12

#define	RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_6 0x13

#define	RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_8 0x14

#define	RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_10 0x15

#define	RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_12 0x16

#define	RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_16 0x17

#define	RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_32 0x18

#define	RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_64 0x19

#define	RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_128 0x1A

#define	RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_256 0x1B

#define	RCC_CFGR2_PREDIV 0xf

#define	RCC_CFGR2_PREDIV_NODIV 0x0

#define	RCC_CFGR2_PREDIV_DIV2 0x1

#define	RCC_CFGR2_PREDIV_DIV3 0x2

#define	RCC_CFGR2_PREDIV_DIV4 0x3

#define	RCC_CFGR2_PREDIV_DIV5 0x4

#define	RCC_CFGR2_PREDIV_DIV6 0x5

#define	RCC_CFGR2_PREDIV_DIV7 0x6

#define	RCC_CFGR2_PREDIV_DIV8 0x7

#define	RCC_CFGR2_PREDIV_DIV9 0x8

#define	RCC_CFGR2_PREDIV_DIV10 0x9

#define	RCC_CFGR2_PREDIV_DIV11 0xa

#define	RCC_CFGR2_PREDIV_DIV12 0xb

#define	RCC_CFGR2_PREDIV_DIV13 0xc

#define	RCC_CFGR2_PREDIV_DIV14 0xd

#define	RCC_CFGR2_PREDIV_DIV15 0xe

#define	RCC_CFGR2_PREDIV_DIV16 0xf

#define	RCC_CFGR3_TIM8SW (1 << 9)

#define	RCC_CFGR3_TIM1SW (1 << 8)

#define	RCC_CFGR3_I2C2SW (1 << 5)

#define	RCC_CFGR3_I2C1SW (1 << 4)

#define	RCC_CFGR3_UART5SW_SHIFT 22

#define	RCC_CFGR3_UART4SW_SHIFT 20

#define	RCC_CFGR3_UART3SW_SHIFT 18

#define	RCC_CFGR3_UART2SW_SHIFT 16

#define	RCC_CFGR3_UART1SW_SHIFT 0

#define	RCC_CFGR3_UARTxSW_PCLK 0x0

#define	RCC_CFGR3_UARTxSW_SYSCLK 0x1

#define	RCC_CFGR3_UARTxSW_LSE 0x2

#define	RCC_CFGR3_UARTxSW_HSI 0x3

#define	RCC_CFGR3_UARTxSW_MASK 0x3

#define	_REG_BIT(base, bit) (((base) << 5) + (bit))

Enumerations
enum	rcc_clock_hsi { RCC_CLOCK_HSI_48MHZ , RCC_CLOCK_HSI_64MHZ , RCC_CLOCK_HSI_END }

enum	rcc_clock_hse8 { RCC_CLOCK_HSE8_72MHZ , RCC_CLOCK_HSE8_END }

enum	rcc_osc { RCC_PLL , RCC_HSE , RCC_HSI , RCC_LSE , RCC_LSI }

enum	rcc_periph_clken { RCC_DMA1 = _REG_BIT(0x14, 0) , RCC_DMA2 = _REG_BIT(0x14, 1) , RCC_SRAM = _REG_BIT(0x14, 2) , RCC_FLTIF = _REG_BIT(0x14, 4) , RCC_FMC = _REG_BIT(0x14, 5) , RCC_CRC = _REG_BIT(0x14, 6) , RCC_GPIOH = _REG_BIT(0x14, 16) , RCC_GPIOA = _REG_BIT(0x14, 17) , RCC_GPIOB = _REG_BIT(0x14, 18) , RCC_GPIOC = _REG_BIT(0x14, 19) , RCC_GPIOD = _REG_BIT(0x14, 20) , RCC_GPIOE = _REG_BIT(0x14, 21) , RCC_GPIOF = _REG_BIT(0x14, 22) , RCC_GPIOG = _REG_BIT(0x14, 23) , RCC_TSC = _REG_BIT(0x14, 24) , RCC_ADC12 = _REG_BIT(0x14, 28) , RCC_ADC34 = _REG_BIT(0x14, 29) , RCC_SYSCFG = _REG_BIT(0x18, 0) , RCC_ADC = _REG_BIT(0x18, 9) , RCC_TIM1 = _REG_BIT(0x18, 11) , RCC_SPI1 = _REG_BIT(0x18, 12) , RCC_TIM8 = _REG_BIT(0x18, 13) , RCC_USART1 = _REG_BIT(0x18, 14) , RCC_SPI4 = _REG_BIT(0x18, 15) , RCC_TIM15 = _REG_BIT(0x18, 16) , RCC_TIM16 = _REG_BIT(0x18, 17) , RCC_TIM17 = _REG_BIT(0x18, 18) , RCC_TIM19 = _REG_BIT(0x18, 19) , RCC_TIM20 = _REG_BIT(0x18, 20) , RCC_DBGMCU = _REG_BIT(0x18, 22) , RCC_SDADC1 = _REG_BIT(0x18, 24) , RCC_SDADC2 = _REG_BIT(0x18, 25) , RCC_SDADC3 = _REG_BIT(0x18, 26) , RCC_HRTIM = _REG_BIT(0x18, 29) , RCC_TIM2 = _REG_BIT(0x1C, 0) , RCC_TIM3 = _REG_BIT(0x1C, 1) , RCC_TIM4 = _REG_BIT(0x1C, 2) , RCC_TIM5 = _REG_BIT(0x1C, 3) , RCC_TIM6 = _REG_BIT(0x1C, 4) , RCC_TIM7 = _REG_BIT(0x1C, 5) , RCC_TIM12 = _REG_BIT(0x1C, 6) , RCC_TIM13 = _REG_BIT(0x1C, 7) , RCC_TIM14 = _REG_BIT(0x1C, 8) , RCC_TIM18 = _REG_BIT(0x1C, 9) , RCC_WWDG = _REG_BIT(0x1C, 11) , RCC_SPI2 = _REG_BIT(0x1C, 14) , RCC_SPI3 = _REG_BIT(0x1C, 15) , RCC_USART2 = _REG_BIT(0x1C, 17) , RCC_USART3 = _REG_BIT(0x1C, 18) , RCC_UART4 = _REG_BIT(0x1C, 19) , RCC_UART5 = _REG_BIT(0x1C, 20) , RCC_I2C1 = _REG_BIT(0x1C, 21) , RCC_I2C2 = _REG_BIT(0x1C, 22) , RCC_USB = _REG_BIT(0x1C, 23) , RCC_CAN = _REG_BIT(0x1C, 25) , RCC_CAN1 = _REG_BIT(0x1C, 25) , RCC_DAC2 = _REG_BIT(0x1C, 26) , RCC_PWR = _REG_BIT(0x1C, 28) , RCC_DAC1 = _REG_BIT(0x1C, 29) , RCC_CEC = _REG_BIT(0x1C, 30) , RCC_I2C3 = _REG_BIT(0x1C, 30) }

enum	rcc_periph_rst { RST_SYSCFG = _REG_BIT(0x0C, 0) , RST_ADC = _REG_BIT(0x0C, 9) , RST_TIM1 = _REG_BIT(0x0C, 11) , RST_SPI1 = _REG_BIT(0x0C, 12) , RST_TIM8 = _REG_BIT(0x0C, 13) , RST_USART1 = _REG_BIT(0x0C, 14) , RST_SPI4 = _REG_BIT(0x0C, 15) , RST_TIM15 = _REG_BIT(0x0C, 16) , RST_TIM16 = _REG_BIT(0x0C, 17) , RST_TIM17 = _REG_BIT(0x0C, 18) , RST_TIM19 = _REG_BIT(0x0C, 19) , RST_TIM20 = _REG_BIT(0x0C, 20) , RST_SDADC1 = _REG_BIT(0x0C, 24) , RST_SDADC2 = _REG_BIT(0x0C, 25) , RST_SDADC3 = _REG_BIT(0x0C, 26) , RST_HRTIM = _REG_BIT(0x0C, 29) , RST_TIM2 = _REG_BIT(0x10, 0) , RST_TIM3 = _REG_BIT(0x10, 1) , RST_TIM4 = _REG_BIT(0x10, 2) , RST_TIM5 = _REG_BIT(0x10, 3) , RST_TIM6 = _REG_BIT(0x10, 4) , RST_TIM7 = _REG_BIT(0x10, 5) , RST_TIM12 = _REG_BIT(0x10, 6) , RST_TIM13 = _REG_BIT(0x10, 7) , RST_TIM14 = _REG_BIT(0x10, 8) , RST_TIM18 = _REG_BIT(0x10, 9) , RST_WWDG = _REG_BIT(0x10, 11) , RST_SPI2 = _REG_BIT(0x10, 14) , RST_SPI3 = _REG_BIT(0x10, 15) , RST_USART2 = _REG_BIT(0x10, 17) , RST_USART3 = _REG_BIT(0x10, 18) , RST_UART4 = _REG_BIT(0x10, 19) , RST_UART5 = _REG_BIT(0x10, 20) , RST_I2C1 = _REG_BIT(0x10, 21) , RST_I2C2 = _REG_BIT(0x10, 22) , RST_USB = _REG_BIT(0x10, 23) , RST_CAN = _REG_BIT(0x10, 25) , RST_CAN1 = _REG_BIT(0x10, 25) , RST_DAC2 = _REG_BIT(0x10, 26) , RST_PWR = _REG_BIT(0x10, 28) , RST_DAC1 = _REG_BIT(0x10, 29) , RST_CEC = _REG_BIT(0x10, 30) , RST_I2C3 = _REG_BIT(0x10, 30) , RST_FMC = _REG_BIT(0x28, 5) , RST_GPIOH = _REG_BIT(0x28, 16) , RST_GPIOA = _REG_BIT(0x28, 17) , RST_GPIOB = _REG_BIT(0x28, 18) , RST_GPIOC = _REG_BIT(0x28, 19) , RST_GPIOD = _REG_BIT(0x28, 20) , RST_GPIOE = _REG_BIT(0x28, 21) , RST_GPIOF = _REG_BIT(0x28, 22) , RST_GPIOG = _REG_BIT(0x28, 23) , RST_TSC = _REG_BIT(0x28, 24) , RST_ADC12 = _REG_BIT(0x28, 28) , RST_ADC34 = _REG_BIT(0x28, 29) , RST_BD = _REG_BIT(0x20, 16) }

Functions
void	rcc_osc_ready_int_clear (enum rcc_osc osc)

void	rcc_osc_ready_int_enable (enum rcc_osc osc)

void	rcc_osc_ready_int_disable (enum rcc_osc osc)

int	rcc_osc_ready_int_flag (enum rcc_osc osc)

void	rcc_css_int_clear (void)

int	rcc_css_int_flag (void)

void	rcc_wait_for_osc_not_ready (enum rcc_osc osc)

void	rcc_wait_for_sysclk_status (enum rcc_osc osc)

void	rcc_osc_on (enum rcc_osc osc)

void	rcc_osc_off (enum rcc_osc osc)

void	rcc_css_enable (void)

void	rcc_css_disable (void)

void	rcc_set_sysclk_source (uint32_t clk)

void	rcc_set_pll_source (uint32_t pllsrc)

void	rcc_set_ppre2 (uint32_t ppre2)

void	rcc_set_ppre1 (uint32_t ppre1)

void	rcc_set_hpre (uint32_t hpre)

void	rcc_set_prediv (uint32_t prediv)
	Set PLL Source pre-divider CAUTION. More...

void	rcc_set_pll_multiplier (uint32_t pll)

uint32_t	rcc_get_system_clock_source (void)

void	rcc_backupdomain_reset (void)

void	rcc_clock_setup_pll (const struct rcc_clock_scale *clock)
	Setup clocks to run from PLL. More...

void	rcc_clock_setup_hsi (const struct rcc_clock_scale *clock)

void	rcc_set_i2c_clock_hsi (uint32_t i2c)

void	rcc_set_i2c_clock_sysclk (uint32_t i2c)

uint32_t	rcc_get_i2c_clocks (void)

void	rcc_usb_prescale_1_5 (void)

void	rcc_usb_prescale_1 (void)

void	rcc_adc_prescale (uint32_t prescale1, uint32_t prescale2)

uint32_t	rcc_get_usart_clk_freq (uint32_t usart)
	Get the peripheral clock speed for the USART at base specified. More...

uint32_t	rcc_get_timer_clk_freq (uint32_t timer)
	Get the peripheral clock speed for the Timer at base specified. More...

uint32_t	rcc_get_i2c_clk_freq (uint32_t i2c)
	Get the peripheral clock speed for the I2C device at base specified. More...

uint32_t	rcc_get_spi_clk_freq (uint32_t spi)
	Get the peripheral clock speed for the SPI device at base specified. More...

Variables
uint32_t	rcc_ahb_frequency

uint32_t	rcc_apb1_frequency

uint32_t	rcc_apb2_frequency

const struct rcc_clock_scale	rcc_hsi_configs [RCC_CLOCK_HSI_END]

const struct rcc_clock_scale	rcc_hse8mhz_configs [RCC_CLOCK_HSE8_END]

Macro Definition Documentation

◆ _REG_BIT

#define _REG_BIT	(	base,
		bit
	)	(((base) << 5) + (bit))

Definition at line 472 of file f3/rcc.h.

◆ RCC_AHBENR

#define RCC_AHBENR MMIO32(RCC_BASE + 0x14)

Definition at line 63 of file f3/rcc.h.

◆ RCC_AHBRSTR

#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28)

Definition at line 68 of file f3/rcc.h.

◆ RCC_APB1ENR

#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1C)

Definition at line 65 of file f3/rcc.h.

◆ RCC_APB1RSTR

#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10)

Definition at line 62 of file f3/rcc.h.

◆ RCC_APB2ENR

#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18)

Definition at line 64 of file f3/rcc.h.

◆ RCC_APB2RSTR

#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0C)

Definition at line 61 of file f3/rcc.h.

◆ RCC_BDCR

#define RCC_BDCR MMIO32(RCC_BASE + 0x20)

Definition at line 66 of file f3/rcc.h.

◆ RCC_BDCR_BDRST

#define RCC_BDCR_BDRST (1 << 16)

Definition at line 326 of file f3/rcc.h.

◆ RCC_BDCR_LSEBYP

#define RCC_BDCR_LSEBYP (1 << 2)

Definition at line 330 of file f3/rcc.h.

◆ RCC_BDCR_LSEON

#define RCC_BDCR_LSEON (1 << 0)

Definition at line 332 of file f3/rcc.h.

◆ RCC_BDCR_LSERDY

#define RCC_BDCR_LSERDY (1 << 1)

Definition at line 331 of file f3/rcc.h.

◆ RCC_BDCR_RTCEN

#define RCC_BDCR_RTCEN (1 << 15)

Definition at line 327 of file f3/rcc.h.

◆ RCC_CFGR

#define RCC_CFGR MMIO32(RCC_BASE + 0x04)

Definition at line 59 of file f3/rcc.h.

◆ RCC_CFGR2

#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2C)

Definition at line 69 of file f3/rcc.h.

◆ RCC_CFGR2_ADC12PRES_SHIFT

#define RCC_CFGR2_ADC12PRES_SHIFT 4

Definition at line 366 of file f3/rcc.h.

◆ RCC_CFGR2_ADC34PRES_SHIFT

#define RCC_CFGR2_ADC34PRES_SHIFT 9

Definition at line 365 of file f3/rcc.h.

◆ RCC_CFGR2_ADCxPRES_MASK

#define RCC_CFGR2_ADCxPRES_MASK 0x1f

Definition at line 367 of file f3/rcc.h.

◆ RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_1

#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_1 0x10

Definition at line 368 of file f3/rcc.h.

◆ RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_10

#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_10 0x15

Definition at line 373 of file f3/rcc.h.

◆ RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_12

#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_12 0x16

Definition at line 374 of file f3/rcc.h.

◆ RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_128

#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_128 0x1A

Definition at line 378 of file f3/rcc.h.

◆ RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_16

#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_16 0x17

Definition at line 375 of file f3/rcc.h.

◆ RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_2

#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_2 0x11

Definition at line 369 of file f3/rcc.h.

◆ RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_256

#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_256 0x1B

Definition at line 379 of file f3/rcc.h.

◆ RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_32

#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_32 0x18

Definition at line 376 of file f3/rcc.h.

◆ RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_4

#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_4 0x12

Definition at line 370 of file f3/rcc.h.

◆ RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_6

#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_6 0x13

Definition at line 371 of file f3/rcc.h.

◆ RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_64

#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_64 0x19

Definition at line 377 of file f3/rcc.h.

◆ RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_8

#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_8 0x14

Definition at line 372 of file f3/rcc.h.

◆ RCC_CFGR2_PREDIV

#define RCC_CFGR2_PREDIV 0xf

Definition at line 381 of file f3/rcc.h.

◆ RCC_CFGR3

#define RCC_CFGR3 MMIO32(RCC_BASE + 0x30)

Definition at line 70 of file f3/rcc.h.

◆ RCC_CFGR3_I2C1SW

#define RCC_CFGR3_I2C1SW (1 << 4)

Definition at line 407 of file f3/rcc.h.

◆ RCC_CFGR3_I2C2SW

#define RCC_CFGR3_I2C2SW (1 << 5)

Definition at line 406 of file f3/rcc.h.

◆ RCC_CFGR3_TIM1SW

#define RCC_CFGR3_TIM1SW (1 << 8)

Definition at line 405 of file f3/rcc.h.

◆ RCC_CFGR3_TIM8SW

#define RCC_CFGR3_TIM8SW (1 << 9)

Definition at line 404 of file f3/rcc.h.

◆ RCC_CFGR3_UARTxSW_MASK

#define RCC_CFGR3_UARTxSW_MASK 0x3

Definition at line 429 of file f3/rcc.h.

◆ RCC_CFGR_HPRE_MASK

#define RCC_CFGR_HPRE_MASK 0xf

Definition at line 143 of file f3/rcc.h.

◆ RCC_CFGR_HPRE_SHIFT

#define RCC_CFGR_HPRE_SHIFT 4

Definition at line 142 of file f3/rcc.h.

◆ RCC_CFGR_I2SSRC

#define RCC_CFGR_I2SSRC (1 << 23)

Definition at line 87 of file f3/rcc.h.

◆ RCC_CFGR_MCO_HSE

#define RCC_CFGR_MCO_HSE 0x6

Definition at line 101 of file f3/rcc.h.

◆ RCC_CFGR_MCO_HSI

#define RCC_CFGR_MCO_HSI 0x5

Definition at line 100 of file f3/rcc.h.

◆ RCC_CFGR_MCO_LSE

#define RCC_CFGR_MCO_LSE 0x3

Definition at line 98 of file f3/rcc.h.

◆ RCC_CFGR_MCO_LSI

#define RCC_CFGR_MCO_LSI 0x2

Definition at line 97 of file f3/rcc.h.

◆ RCC_CFGR_MCO_MASK

#define RCC_CFGR_MCO_MASK 0x7

Definition at line 94 of file f3/rcc.h.

◆ RCC_CFGR_MCO_NOCLK

#define RCC_CFGR_MCO_NOCLK 0x0

Definition at line 95 of file f3/rcc.h.

◆ RCC_CFGR_MCO_PLL

#define RCC_CFGR_MCO_PLL 0x7

Definition at line 102 of file f3/rcc.h.

◆ RCC_CFGR_MCO_SHIFT

#define RCC_CFGR_MCO_SHIFT 24

Definition at line 93 of file f3/rcc.h.

◆ RCC_CFGR_MCO_SYSCLK

#define RCC_CFGR_MCO_SYSCLK 0x4

Definition at line 99 of file f3/rcc.h.

◆ RCC_CFGR_MCOF

#define RCC_CFGR_MCOF (1 << 28)

Definition at line 86 of file f3/rcc.h.

◆ RCC_CFGR_PLLMUL_MASK

#define RCC_CFGR_PLLMUL_MASK 0xF

Definition at line 110 of file f3/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL10

#define RCC_CFGR_PLLMUL_MUL10 0x8

Definition at line 119 of file f3/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL11

#define RCC_CFGR_PLLMUL_MUL11 0x9

Definition at line 120 of file f3/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL12

#define RCC_CFGR_PLLMUL_MUL12 0xA

Definition at line 121 of file f3/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL13

#define RCC_CFGR_PLLMUL_MUL13 0xB

Definition at line 122 of file f3/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL14

#define RCC_CFGR_PLLMUL_MUL14 0xC

Definition at line 123 of file f3/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL15

#define RCC_CFGR_PLLMUL_MUL15 0xD

Definition at line 124 of file f3/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL16

#define RCC_CFGR_PLLMUL_MUL16 0xE

Definition at line 125 of file f3/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL2

#define RCC_CFGR_PLLMUL_MUL2 0x0

Definition at line 111 of file f3/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL3

#define RCC_CFGR_PLLMUL_MUL3 0x1

Definition at line 112 of file f3/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL4

#define RCC_CFGR_PLLMUL_MUL4 0x2

Definition at line 113 of file f3/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL5

#define RCC_CFGR_PLLMUL_MUL5 0x3

Definition at line 114 of file f3/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL6

#define RCC_CFGR_PLLMUL_MUL6 0x4

Definition at line 115 of file f3/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL7

#define RCC_CFGR_PLLMUL_MUL7 0x5

Definition at line 116 of file f3/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL8

#define RCC_CFGR_PLLMUL_MUL8 0x6

Definition at line 117 of file f3/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL9

#define RCC_CFGR_PLLMUL_MUL9 0x7

Definition at line 118 of file f3/rcc.h.

◆ RCC_CFGR_PLLMUL_SHIFT

#define RCC_CFGR_PLLMUL_SHIFT 18

Definition at line 109 of file f3/rcc.h.

◆ RCC_CFGR_PLLSRC

#define RCC_CFGR_PLLSRC (1 << 16)

Definition at line 90 of file f3/rcc.h.

◆ RCC_CFGR_PLLSRC_HSE_PREDIV

#define RCC_CFGR_PLLSRC_HSE_PREDIV 1

Definition at line 106 of file f3/rcc.h.

◆ RCC_CFGR_PLLSRC_HSI_DIV2

#define RCC_CFGR_PLLSRC_HSI_DIV2 0

Definition at line 105 of file f3/rcc.h.

◆ RCC_CFGR_PLLXTPRE

#define RCC_CFGR_PLLXTPRE (1 << 17)

Definition at line 89 of file f3/rcc.h.

◆ RCC_CFGR_PPRE1_MASK

#define RCC_CFGR_PPRE1_MASK 0x7

Definition at line 130 of file f3/rcc.h.

◆ RCC_CFGR_PPRE1_SHIFT

#define RCC_CFGR_PPRE1_SHIFT 8

Definition at line 129 of file f3/rcc.h.

◆ RCC_CFGR_PPRE2_MASK

#define RCC_CFGR_PPRE2_MASK 0x7

Definition at line 128 of file f3/rcc.h.

◆ RCC_CFGR_PPRE2_SHIFT

#define RCC_CFGR_PPRE2_SHIFT 11

Definition at line 127 of file f3/rcc.h.

◆ RCC_CFGR_SW_HSE

#define RCC_CFGR_SW_HSE 0x1

Definition at line 167 of file f3/rcc.h.

◆ RCC_CFGR_SW_HSI

#define RCC_CFGR_SW_HSI 0x0

Definition at line 166 of file f3/rcc.h.

◆ RCC_CFGR_SW_PLL

#define RCC_CFGR_SW_PLL 0x2

Definition at line 168 of file f3/rcc.h.

◆ RCC_CFGR_SW_SHIFT

#define RCC_CFGR_SW_SHIFT 0

Definition at line 165 of file f3/rcc.h.

◆ RCC_CFGR_SWS_HSE

#define RCC_CFGR_SWS_HSE 0x1

Definition at line 161 of file f3/rcc.h.

◆ RCC_CFGR_SWS_HSI

#define RCC_CFGR_SWS_HSI 0x0

Definition at line 160 of file f3/rcc.h.

◆ RCC_CFGR_SWS_MASK

#define RCC_CFGR_SWS_MASK 0x3

Definition at line 159 of file f3/rcc.h.

◆ RCC_CFGR_SWS_PLL

#define RCC_CFGR_SWS_PLL 0x2

Definition at line 162 of file f3/rcc.h.

◆ RCC_CFGR_SWS_SHIFT

#define RCC_CFGR_SWS_SHIFT 2

Definition at line 158 of file f3/rcc.h.

◆ RCC_CFGR_USBPRES

#define RCC_CFGR_USBPRES (1 << 22)

Definition at line 88 of file f3/rcc.h.

◆ RCC_CIR

#define RCC_CIR MMIO32(RCC_BASE + 0x08)

Definition at line 60 of file f3/rcc.h.

◆ RCC_CIR_CSSC

#define RCC_CIR_CSSC (1 << 23)

Definition at line 201 of file f3/rcc.h.

◆ RCC_CIR_CSSF

#define RCC_CIR_CSSF (1 << 7)

Definition at line 218 of file f3/rcc.h.

◆ RCC_CIR_HSERDYC

#define RCC_CIR_HSERDYC (1 << 19)

Definition at line 205 of file f3/rcc.h.

◆ RCC_CIR_HSERDYF

#define RCC_CIR_HSERDYF (1 << 3)

Definition at line 222 of file f3/rcc.h.

◆ RCC_CIR_HSERDYIE

#define RCC_CIR_HSERDYIE (1 << 11)

Definition at line 212 of file f3/rcc.h.

◆ RCC_CIR_HSIRDYC

#define RCC_CIR_HSIRDYC (1 << 18)

Definition at line 206 of file f3/rcc.h.

◆ RCC_CIR_HSIRDYF

#define RCC_CIR_HSIRDYF (1 << 2)

Definition at line 223 of file f3/rcc.h.

◆ RCC_CIR_HSIRDYIE

#define RCC_CIR_HSIRDYIE (1 << 10)

Definition at line 213 of file f3/rcc.h.

◆ RCC_CIR_LSERDYC

#define RCC_CIR_LSERDYC (1 << 17)

Definition at line 207 of file f3/rcc.h.

◆ RCC_CIR_LSERDYF

#define RCC_CIR_LSERDYF (1 << 1)

Definition at line 224 of file f3/rcc.h.

◆ RCC_CIR_LSERDYIE

#define RCC_CIR_LSERDYIE (1 << 9)

Definition at line 214 of file f3/rcc.h.

◆ RCC_CIR_LSIRDYC

#define RCC_CIR_LSIRDYC (1 << 16)

Definition at line 208 of file f3/rcc.h.

◆ RCC_CIR_LSIRDYF

#define RCC_CIR_LSIRDYF (1 << 0)

Definition at line 225 of file f3/rcc.h.

◆ RCC_CIR_LSIRDYIE

#define RCC_CIR_LSIRDYIE (1 << 8)

Definition at line 215 of file f3/rcc.h.

◆ RCC_CIR_PLLRDYC

#define RCC_CIR_PLLRDYC (1 << 20)

Definition at line 204 of file f3/rcc.h.

◆ RCC_CIR_PLLRDYF

#define RCC_CIR_PLLRDYF (1 << 4)

Definition at line 221 of file f3/rcc.h.

◆ RCC_CIR_PLLRDYIE

#define RCC_CIR_PLLRDYIE (1 << 12)

Definition at line 211 of file f3/rcc.h.

◆ RCC_CR

#define RCC_CR MMIO32(RCC_BASE + 0x00)

Definition at line 58 of file f3/rcc.h.

◆ RCC_CR_CSSON

#define RCC_CR_CSSON (1 << 19)

Definition at line 76 of file f3/rcc.h.

◆ RCC_CR_HSEBYP

#define RCC_CR_HSEBYP (1 << 18)

Definition at line 77 of file f3/rcc.h.

◆ RCC_CR_HSEON

#define RCC_CR_HSEON (1 << 16)

Definition at line 79 of file f3/rcc.h.

◆ RCC_CR_HSERDY

#define RCC_CR_HSERDY (1 << 17)

Definition at line 78 of file f3/rcc.h.

◆ RCC_CR_HSION

#define RCC_CR_HSION (1 << 0)

Definition at line 83 of file f3/rcc.h.

◆ RCC_CR_HSIRDY

#define RCC_CR_HSIRDY (1 << 1)

Definition at line 82 of file f3/rcc.h.

◆ RCC_CR_PLLON

#define RCC_CR_PLLON (1 << 24)

Definition at line 75 of file f3/rcc.h.

◆ RCC_CR_PLLRDY

#define RCC_CR_PLLRDY (1 << 25)

Definition at line 74 of file f3/rcc.h.

◆ RCC_CSR

#define RCC_CSR MMIO32(RCC_BASE + 0x24)

Definition at line 67 of file f3/rcc.h.

◆ RCC_CSR_IWDGRSTF

#define RCC_CSR_IWDGRSTF (1 << 29)

Definition at line 338 of file f3/rcc.h.

◆ RCC_CSR_LPWRRSTF

#define RCC_CSR_LPWRRSTF (1 << 31)

Definition at line 336 of file f3/rcc.h.

◆ RCC_CSR_LSION

#define RCC_CSR_LSION (1 << 0)

Definition at line 345 of file f3/rcc.h.

◆ RCC_CSR_LSIRDY

#define RCC_CSR_LSIRDY (1 << 1)

Definition at line 344 of file f3/rcc.h.

◆ RCC_CSR_OBLRSTF

#define RCC_CSR_OBLRSTF (1 << 25)

Definition at line 342 of file f3/rcc.h.

◆ RCC_CSR_PINRSTF

#define RCC_CSR_PINRSTF (1 << 26)

Definition at line 341 of file f3/rcc.h.

◆ RCC_CSR_PORRSTF

#define RCC_CSR_PORRSTF (1 << 27)

Definition at line 340 of file f3/rcc.h.

◆ RCC_CSR_RMVF

#define RCC_CSR_RMVF (1 << 24)

Definition at line 343 of file f3/rcc.h.

◆ RCC_CSR_SFTRSTF

#define RCC_CSR_SFTRSTF (1 << 28)

Definition at line 339 of file f3/rcc.h.

◆ RCC_CSR_WWDGRSTF

#define RCC_CSR_WWDGRSTF (1 << 30)

Definition at line 337 of file f3/rcc.h.

Enumeration Type Documentation

◆ rcc_clock_hse8

enum rcc_clock_hse8

Enumerator
RCC_CLOCK_HSE8_72MHZ
RCC_CLOCK_HSE8_END

Definition at line 444 of file f3/rcc.h.

◆ rcc_clock_hsi

enum rcc_clock_hsi

Enumerator
RCC_CLOCK_HSI_48MHZ
RCC_CLOCK_HSI_64MHZ
RCC_CLOCK_HSI_END

Definition at line 439 of file f3/rcc.h.

◆ rcc_osc

enum rcc_osc

Enumerator
RCC_PLL
RCC_HSE
RCC_HSI
RCC_LSE
RCC_LSI

Definition at line 468 of file f3/rcc.h.

◆ rcc_periph_clken

enum rcc_periph_clken

Enumerator
RCC_DMA1
RCC_DMA2
RCC_SRAM
RCC_FLTIF
RCC_FMC
RCC_CRC
RCC_GPIOH
RCC_GPIOA
RCC_GPIOB
RCC_GPIOC
RCC_GPIOD
RCC_GPIOE
RCC_GPIOF
RCC_GPIOG
RCC_TSC
RCC_ADC12
RCC_ADC34
RCC_SYSCFG
RCC_ADC
RCC_TIM1
RCC_SPI1
RCC_TIM8
RCC_USART1
RCC_SPI4
RCC_TIM15
RCC_TIM16
RCC_TIM17
RCC_TIM19
RCC_TIM20
RCC_DBGMCU
RCC_SDADC1
RCC_SDADC2
RCC_SDADC3
RCC_HRTIM
RCC_TIM2
RCC_TIM3
RCC_TIM4
RCC_TIM5
RCC_TIM6
RCC_TIM7
RCC_TIM12
RCC_TIM13
RCC_TIM14
RCC_TIM18
RCC_WWDG
RCC_SPI2
RCC_SPI3
RCC_USART2
RCC_USART3
RCC_UART4
RCC_UART5
RCC_I2C1
RCC_I2C2
RCC_USB
RCC_CAN
RCC_CAN1
RCC_DAC2
RCC_PWR
RCC_DAC1
RCC_CEC
RCC_I2C3

Definition at line 480 of file f3/rcc.h.

◆ rcc_periph_rst

enum rcc_periph_rst

Enumerator
RST_SYSCFG
RST_ADC
RST_TIM1
RST_SPI1
RST_TIM8
RST_USART1
RST_SPI4
RST_TIM15
RST_TIM16
RST_TIM17
RST_TIM19
RST_TIM20
RST_SDADC1
RST_SDADC2
RST_SDADC3
RST_HRTIM
RST_TIM2
RST_TIM3
RST_TIM4
RST_TIM5
RST_TIM6
RST_TIM7
RST_TIM12
RST_TIM13
RST_TIM14
RST_TIM18
RST_WWDG
RST_SPI2
RST_SPI3
RST_USART2
RST_USART3
RST_UART4
RST_UART5
RST_I2C1
RST_I2C2
RST_USB
RST_CAN
RST_CAN1
RST_DAC2
RST_PWR
RST_DAC1
RST_CEC
RST_I2C3
RST_FMC
RST_GPIOH
RST_GPIOA
RST_GPIOB
RST_GPIOC
RST_GPIOD
RST_GPIOE
RST_GPIOF
RST_GPIOG
RST_TSC
RST_ADC12
RST_ADC34
RST_BD

Definition at line 549 of file f3/rcc.h.

Data Structures

Macros

Enumerations

Functions

Variables