libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
dma2d_common_f47.h
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1/** @addtogroup dma2d_defines
2 *
3 * @version 1.0.0
4 *
5 * @date 15 August 2016
6 *
7 * This library supports the DMA2D Peripheral in the STM32F4xx and STM32F7xx
8 * series of ARM Cortex Microcontrollers by ST Microelectronics.
9 *
10 * LGPL License Terms @ref lgpl_license
11 */
12
13/*
14 * STM32F4xx/STM32F7xx DMA2D Register defines
15 *
16 * Copyright (C) 2016, Chuck McManis <cmcmanis@mcmanis.com>
17 *
18 * This file is part of the libopencm3 project.
19 *
20 * This library is free software: you can redistribute it and/or modify
21 * it under the terms of the GNU Lesser General Public License as published by
22 * the Free Software Foundation, either version 3 of the License, or
23 * (at your option) any later version.
24 *
25 * This library is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU Lesser General Public License for more details.
29 *
30 * You should have received a copy of the GNU Lesser General Public License
31 * along with this library. If not, see <http://www.gnu.org/licenses/>.
32 *
33 */
34
35#include <libopencm3/stm32/memorymap.h>
36#include <stdint.h>
37
38#ifndef DMA2D_H
39#define DMA2D_H
40
41/**@{*/
42
43/** DMA2D Control Register */
44#define DMA2D_CR MMIO32(DMA2D_BASE + 0x0U)
45#define DMA2D_CR_MODE_SHIFT 16
46#define DMA2D_CR_MODE_MASK 0x3
47#define DMA2D_CR_MODE_M2M 0 /* memory to memory */
48#define DMA2D_CR_MODE_M2MWPFC 1 /* memory to memory with pix convert */
49#define DMA2D_CR_MODE_M2MWB 2 /* memory to memory with blend */
50#define DMA2D_CR_MODE_R2M 3 /* register to memory */
51#define DMA2D_CR_CEIE (1 << 13)
52#define DMA2D_CR_CTCIE (1 << 12)
53#define DMA2D_CR_CAEIE (1 << 11)
54#define DMA2D_CR_TWIE (1 << 10)
55#define DMA2D_CR_TCIE (1 << 9)
56#define DMA2D_CR_TEIE (1 << 8)
57#define DMA2D_CR_ABORT (1 << 2)
58#define DMA2D_CR_SUSP (1 << 1)
59#define DMA2D_CR_START (1 << 0)
60
61/** DMA2D Interrupt Status Register */
62#define DMA2D_ISR MMIO32(DMA2D_BASE + 0x4U)
63#define DMA2D_ISR_CEIF (1 << 5)
64#define DMA2D_ISR_CTCIF (1 << 4)
65#define DMA2D_ISR_CAEIF (1 << 3)
66#define DMA2D_ISR_TWIF (1 << 2)
67#define DMA2D_ISR_TCIF (1 << 1)
68#define DMA2D_ISR_TEIF (1 << 0)
69
70/** DMA2D Interrupt Flag Clear Register */
71#define DMA2D_IFCR MMIO32(DMA2D_BASE + 0x8U)
72#define DMA2D_IFCR_CCEIF (1 << 5)
73#define DMA2D_IFCR_CCTCIF (1 << 4)
74#define DMA2D_IFCR_CCAEIF (1 << 3)
75#define DMA2D_IFCR_CTWIF (1 << 2)
76#define DMA2D_IFCR_CTCIF (1 << 1)
77#define DMA2D_IFCR_CTEIF (1 << 0)
78
79/** DMA2D Foreground Memory Address Register */
80#define DMA2D_FGMAR MMIO32(DMA2D_BASE + 0xCU)
81
82/** DMA2D Foreground Offset Register */
83#define DMA2D_FGOR MMIO32(DMA2D_BASE + 0x10U)
84#define DMA2D_FGOR_LO_SHIFT 0
85#define DMA2D_FGOR_LO_MASK 0x3fff
86
87/** DMA2D Background Memory Address Register */
88#define DMA2D_BGMAR MMIO32(DMA2D_BASE + 0x14U)
89
90/** DMA2D Background Offset Register */
91#define DMA2D_BGOR MMIO32(DMA2D_BASE + 0x18U)
92#define DMA2D_BGOR_LO_SHIFT 0
93#define DMA2D_BGOR_LO_MASK 0x3fff
94
95/** DMA2D Foreground and Background PFC Control Register */
96#define DMA2D_FGPFCCR MMIO32(DMA2D_BASE + 0x1cU)
97#define DMA2D_BGPFCCR MMIO32(DMA2D_BASE + 0x24U)
98
99#define DMA2D_xPFCCR_ALPHA_SHIFT 24
100#define DMA2D_xPFCCR_ALPHA_MASK 0xff
101#define DMA2D_xPFCCR_AM_SHIFT 16
102#define DMA2D_xPFCCR_AM_MASK 0x3
103#define DMA2D_xPFCCR_AM_NONE 0
104#define DMA2D_xPFCCR_AM_FORCE 1
105#define DMA2D_xPFCCR_AM_PRODUCT 2
106#define DMA2D_xPFCCR_CS_SHIFT 8
107#define DMA2D_xPFCCR_CS_MASK 0xff
108#define DMA2D_xPFCCR_START (1 << 5)
109#define DMA2D_xPFCCR_CCM_ARGB8888 (0 << 4)
110#define DMA2D_xPFCCR_CCM_RGB888 (1 << 4)
111#define DMA2D_xPFCCR_CM_SHIFT 0
112#define DMA2D_xPFCCR_CM_MASK 0xf
113#define DMA2D_xPFCCR_CM_ARGB8888 0
114#define DMA2D_xPFCCR_CM_RGB888 1
115#define DMA2D_xPFCCR_CM_RGB565 2
116#define DMA2D_xPFCCR_CM_ARGB1555 3
117#define DMA2D_xPFCCR_CM_ARGB4444 4
118#define DMA2D_xPFCCR_CM_L8 5
119#define DMA2D_xPFCCR_CM_AL44 6
120#define DMA2D_xPFCCR_CM_AL88 7
121#define DMA2D_xPFCCR_CM_L4 8
122#define DMA2D_xPFCCR_CM_A8 9
123#define DMA2D_xPFCCR_CM_A4 10
124
125/** DMA2D Foreground and Background Color Register */
126#define DMA2D_FGCOLR MMIO32(DMA2D_BASE + 0x20U)
127#define DMA2D_BGCOLR MMIO32(DMA2D_BASE + 0x28U)
128#define DMA2D_xCOLR_RED_SHIFT 16
129#define DMA2D_xCOLR_RED_MASK 0xff
130#define DMA2D_xCOLR_GREEN_SHIFT 8
131#define DMA2D_xCOLR_GREEN_MASK 0xff
132#define DMA2D_xCOLR_BLUE_SHIFT 0
133#define DMA2D_xCOLR_BLUE_MASK 0xff
134
135/** DMA2D Foreground CLUT Memory Address Register */
136#define DMA2D_FGCMAR MMIO32(DMA2D_BASE + 0x2CU)
137
138/** DMA2D Background CLUT Memory Address Register */
139#define DMA2D_BGCMAR MMIO32(DMA2D_BASE + 0x30U)
140
141/** DMA2D Output PFC Control Register */
142#define DMA2D_OPFCCR MMIO32(DMA2D_BASE + 0x34U)
143#define DMA2D_OPFCCR_CM_SHIFT 0
144#define DMA2D_OPFCCR_CM_MASK 0x3
145#define DMA2D_OPFCCR_CM_ARGB8888 0
146#define DMA2D_OPFCCR_CM_RGB888 1
147#define DMA2D_OPFCCR_CM_RGB565 2
148#define DMA2D_OPFCCR_CM_ARGB1555 3
149#define DMA2D_OPFCCR_CM_ARGB4444 4
150
151/** DMA2D Output Color Register */
152/* The format of this register depends on PFC control above */
153#define DMA2D_OCOLR MMIO32(DMA2D_BASE + 0x38U)
154
155/** DMA2D Output Memory Address Register */
156#define DMA2D_OMAR MMIO32(DMA2D_BASE + 0x3CU)
157
158/** DMA2D Output offset Register */
159#define DMA2D_OOR MMIO32(DMA2D_BASE + 0x40U)
160#define DMA2D_OOR_LO_SHIFT 0
161#define DMA2D_OOR_LO_MASK 0x3fff
162
163/** DMA2D Number of Lines Register */
164#define DMA2D_NLR MMIO32(DMA2D_BASE + 0x44U)
165#define DMA2D_NLR_PL_SHIFT 16
166#define DMA2D_NLR_PL_MASK 0x3fff
167#define DMA2D_NLR_NL_SHIFT 0
168#define DMA2D_NLR_NL_MASK 0xffff
169
170/** DMA2D Line Watermark Register */
171#define DMA2D_LWR MMIO32(DMA2D_BASE + 0x48U)
172#define DMA2D_LWR_LW_SHIFT 0
173#define DMA2D_LWR_LW_MASK 0xffff
174
175/** DMA2D AHB Master Timer Config Register */
176#define DMA2D_AMTCR MMIO32(DMA2D_BASE + 0x4CU)
177#define DMA2D_AMTCR_DT_SHIFT 8
178#define DMA2D_AMTCR_DT_MASK 0xff
179#define DMA2D_AMTCR_EN (1 << 0)
180
181/** DMA2D Foreground Color Lookup table */
182#define DMA2D_FG_CLUT (uint32_t *)(DMA2D_BASE + 0x400U)
183
184/** DMA2D Background Color Lookup table */
185#define DMA2D_BG_CLUT (uint32_t *)(DMA2D_BASE + 0x800U)
186
187/**@}*/
188#endif