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#define | PWR_CR1_UDEN_LSB 18 |
| UDEN[19:18]: Under-drive enable in stop mode. More...
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#define | PWR_CR1_UDEN_MASK (0x3 << PWR_CR1_UDEN_LSB) |
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#define | PWR_CR1_ODSWEN (1 << 17) |
| ODSWEN: Over-drive switching enabled. More...
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#define | PWR_CR1_ODEN (1 << 16) |
| ODEN: Over-drive enable. More...
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#define | PWR_CR1_VOS_LSB 14 |
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#define | PWR_CR1_VOS_MASK (0x3 << PWR_CR1_VOS_LSB) |
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#define | PWR_CR1_ADCDC1 (1 << 13) |
| ADCDC1: Masks extra flash accesses by prefetch (see AN4073) More...
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#define | PWR_CR1_MRUDS (1 << 11) |
| MRUDS: Main regulator in deepsleep under-drive mode. More...
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#define | PWR_CR1_LPUDS (1 << 10) |
| LPUDS: Low-power regulator in deepsleep under-drive mode. More...
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#define | PWR_CR1_FPDS (1 << 9) |
| FPDS: Flash power-down in Stop mode. More...
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#define | PWR_CR1_DBP (1 << 8) |
| DBP: Disable backup domain write protection. More...
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#define | PWR_CR1_PLS_LSB 5 |
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#define | PWR_CR1_PLS_MASK (0x7 << PWR_CR_PLS_LSB) |
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#define | PWR_CR1_PVDE (1 << 4) |
| PVDE: Power voltage detector enable. More...
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#define | PWR_CR1_CSBF (1 << 3) |
| CSBF: Clear standby flag. More...
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#define | PWR_CR1_PDDS (1 << 1) |
| PDDS: Power down deepsleep. More...
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#define | PWR_CR1_LPDS (1 << 0) |
| LPDS: Low-power deepsleep. More...
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