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#define | USART_CR1_M1 (1 << 28) /* F07x */ |
| M1: Wordlength. More...
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#define | USART_CR1_EOBIE (1 << 27) |
| EOBIE: End of Block interrupt enable. More...
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#define | USART_CR1_RTOIE (1 << 26) |
| RTOIE: Receiver timeout interrupt enable. More...
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#define | USART_CR1_DEAT_SHIFT 21 |
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#define | USART_CR1_DEAT (0x1F << USART_CR1_DEAT_SHIFT) |
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#define | USART_CR1_DEAT_VAL(x) ((x) << USART_CR1_DEAT_SHIFT) |
| DEAT[4:0]: Driver Enable assertion time. More...
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#define | USART_CR1_DEDT_SHIFT 16 |
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#define | USART_CR1_DEDT (0x1F << USART_CR1_DEDT_SHIFT) |
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#define | USART_CR1_DEDT_VAL(x) ((x) << USART_CR1_DEDT_SHIFT) |
| DEDT[4:0]: Driver Enable deassertion time. More...
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#define | USART_CR1_OVER8 (1 << 15) |
| OVER8: Oversampling mode. More...
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#define | USART_CR1_CMIE (1 << 14) |
| CMIE: Character match interrupt enable. More...
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#define | USART_CR1_MME (1 << 13) |
| MME: Mute mode enable. More...
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#define | USART_CR1_M0 (1 << 12) |
| M0: Word length. More...
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#define | USART_CR1_M USART_CR1_M0 |
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#define | USART_CR1_WAKE (1 << 11) |
| WAKE: Receiver wakeup method. More...
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#define | USART_CR1_PCE (1 << 10) |
| PCE: Parity control enable. More...
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#define | USART_CR1_PS (1 << 9) |
| PS: Parity selection. More...
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#define | USART_CR1_PEIE (1 << 8) |
| PEIE: PE interrupt enable. More...
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#define | USART_CR1_TXEIE (1 << 7) |
| TXEIE: Interrupt enable. More...
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#define | USART_CR1_TCIE (1 << 6) |
| TCIE: Transmission complete interrupt enable. More...
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#define | USART_CR1_RXNEIE (1 << 5) |
| RXNEIE: RXNE interrupt enable. More...
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#define | USART_CR1_IDLEIE (1 << 4) |
| IDLEIE: IDLE interrupt enable. More...
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#define | USART_CR1_TE (1 << 3) |
| TE: Transmitter enable. More...
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#define | USART_CR1_RE (1 << 2) |
| RE: Receiver enable. More...
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#define | USART_CR1_UESM (1 << 1) |
| UESM: USART enable in Stop mode. More...
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#define | USART_CR1_UE (1 << 0) |
| UE: USART enable. More...
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