#include <libopencm3/cm3/memorymap.h>
Go to the source code of this file.
Macro Definition Documentation
◆ ADC1_BASE
| #define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400) |
Definition at line 67 of file stm32/l0/memorymap.h.
◆ AES_BASE
| #define AES_BASE (PERIPH_BASE_AHB + 0x06000) |
Definition at line 79 of file stm32/l0/memorymap.h.
◆ CRC_BASE
| #define CRC_BASE (PERIPH_BASE_AHB + 0x03000) |
Definition at line 76 of file stm32/l0/memorymap.h.
◆ CRS_BASE
| #define CRS_BASE (PERIPH_BASE_APB1 + 0x6C00) |
Definition at line 54 of file stm32/l0/memorymap.h.
◆ DAC_BASE
| #define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) |
Definition at line 56 of file stm32/l0/memorymap.h.
◆ DBGMCU_BASE
| #define DBGMCU_BASE (PERIPH_BASE_APB2 + 0x5800) |
Definition at line 70 of file stm32/l0/memorymap.h.
◆ DESIG_FLASH_SIZE_BASE
| #define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7C) |
Definition at line 89 of file stm32/l0/memorymap.h.
◆ DESIG_UNIQUE_ID0
| #define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) |
Definition at line 91 of file stm32/l0/memorymap.h.
◆ DESIG_UNIQUE_ID1
| #define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) |
Definition at line 92 of file stm32/l0/memorymap.h.
◆ DESIG_UNIQUE_ID2
| #define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14) |
Definition at line 93 of file stm32/l0/memorymap.h.
◆ DESIG_UNIQUE_ID_BASE
| #define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x50) |
Definition at line 90 of file stm32/l0/memorymap.h.
◆ DMA1_BASE
| #define DMA1_BASE (PERIPH_BASE_AHB + 0x00000) |
Definition at line 73 of file stm32/l0/memorymap.h.
◆ EXTI_BASE
| #define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) |
Definition at line 63 of file stm32/l0/memorymap.h.
◆ FIREWALL_BASE
| #define FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00) |
Definition at line 66 of file stm32/l0/memorymap.h.
◆ FLASH_BASE
| #define FLASH_BASE (0x08000000U) |
Definition at line 26 of file stm32/l0/memorymap.h.
◆ FLASH_MEM_INTERFACE_BASE
| #define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000) |
Definition at line 75 of file stm32/l0/memorymap.h.
◆ GPIO_PORT_A_BASE
| #define GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000) |
Definition at line 81 of file stm32/l0/memorymap.h.
◆ GPIO_PORT_B_BASE
| #define GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400) |
Definition at line 82 of file stm32/l0/memorymap.h.
◆ GPIO_PORT_C_BASE
| #define GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800) |
Definition at line 83 of file stm32/l0/memorymap.h.
◆ GPIO_PORT_D_BASE
| #define GPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00) |
Definition at line 84 of file stm32/l0/memorymap.h.
◆ GPIO_PORT_E_BASE
| #define GPIO_PORT_E_BASE (IOPORT_BASE + 0x01000) |
Definition at line 85 of file stm32/l0/memorymap.h.
◆ GPIO_PORT_H_BASE
| #define GPIO_PORT_H_BASE (IOPORT_BASE + 0x01C00) |
Definition at line 86 of file stm32/l0/memorymap.h.
◆ I2C1_BASE
| #define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) |
Definition at line 50 of file stm32/l0/memorymap.h.
◆ I2C2_BASE
| #define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) |
Definition at line 51 of file stm32/l0/memorymap.h.
◆ I2C3_BASE
| #define I2C3_BASE (PERIPH_BASE_APB1 + 0x7800) |
Definition at line 57 of file stm32/l0/memorymap.h.
◆ INFO_BASE
| #define INFO_BASE (0x1ff80000U) |
Definition at line 29 of file stm32/l0/memorymap.h.
◆ IOPORT_BASE
| #define IOPORT_BASE (0x50000000U) |
Definition at line 28 of file stm32/l0/memorymap.h.
◆ IWDG_BASE
| #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) |
Definition at line 44 of file stm32/l0/memorymap.h.
◆ LCD_BASE
| #define LCD_BASE (PERIPH_BASE_APB1 + 0x2400) |
Definition at line 41 of file stm32/l0/memorymap.h.
◆ LPTIM1_BASE
| #define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00) |
Definition at line 58 of file stm32/l0/memorymap.h.
◆ LPUART1_BASE
| #define LPUART1_BASE (PERIPH_BASE_APB1 + 0x4800) |
Definition at line 47 of file stm32/l0/memorymap.h.
◆ PERIPH_BASE
| #define PERIPH_BASE (0x40000000U) |
Definition at line 27 of file stm32/l0/memorymap.h.
◆ PERIPH_BASE_AHB
| #define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000) |
Definition at line 32 of file stm32/l0/memorymap.h.
◆ PERIPH_BASE_APB1
| #define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) |
Definition at line 30 of file stm32/l0/memorymap.h.
◆ PERIPH_BASE_APB2
| #define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) |
Definition at line 31 of file stm32/l0/memorymap.h.
◆ POWER_CONTROL_BASE
| #define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) |
Definition at line 55 of file stm32/l0/memorymap.h.
◆ RCC_BASE
| #define RCC_BASE (PERIPH_BASE_AHB + 0x01000) |
Definition at line 74 of file stm32/l0/memorymap.h.
◆ RNG_BASE
| #define RNG_BASE (PERIPH_BASE_AHB + 0x05000) |
Definition at line 78 of file stm32/l0/memorymap.h.
◆ RTC_BASE
| #define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) |
Definition at line 42 of file stm32/l0/memorymap.h.
◆ SPI1_BASE
| #define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) |
Definition at line 68 of file stm32/l0/memorymap.h.
◆ SPI2_BASE
| #define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) |
Definition at line 45 of file stm32/l0/memorymap.h.
◆ ST_TSENSE_CAL1_30C
Definition at line 97 of file stm32/l0/memorymap.h.
◆ ST_TSENSE_CAL2_110C
Definition at line 98 of file stm32/l0/memorymap.h.
◆ ST_VREFINT_CAL
Definition at line 96 of file stm32/l0/memorymap.h.
◆ SYSCFG_BASE
| #define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000) |
Definition at line 62 of file stm32/l0/memorymap.h.
◆ TIM21_BASE
| #define TIM21_BASE (PERIPH_BASE_APB2 + 0x0800) |
Definition at line 64 of file stm32/l0/memorymap.h.
◆ TIM22_BASE
| #define TIM22_BASE (PERIPH_BASE_APB2 + 0x1400) |
Definition at line 65 of file stm32/l0/memorymap.h.
◆ TIM2_BASE
| #define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) |
Definition at line 37 of file stm32/l0/memorymap.h.
◆ TIM3_BASE
| #define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) |
Definition at line 38 of file stm32/l0/memorymap.h.
◆ TIM6_BASE
| #define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) |
Definition at line 39 of file stm32/l0/memorymap.h.
◆ TIM7_BASE
| #define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) |
Definition at line 40 of file stm32/l0/memorymap.h.
◆ TSC_BASE
| #define TSC_BASE (PERIPH_BASE_AHB + 0x04000) |
Definition at line 77 of file stm32/l0/memorymap.h.
◆ USART1_BASE
| #define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) |
Definition at line 69 of file stm32/l0/memorymap.h.
◆ USART2_BASE
| #define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) |
Definition at line 46 of file stm32/l0/memorymap.h.
◆ USART4_BASE
| #define USART4_BASE (PERIPH_BASE_APB1 + 0x4c00) |
Definition at line 48 of file stm32/l0/memorymap.h.
◆ USART5_BASE
| #define USART5_BASE (PERIPH_BASE_APB1 + 0x5000) |
Definition at line 49 of file stm32/l0/memorymap.h.
◆ USB_DEV_FS_BASE
| #define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) |
Definition at line 52 of file stm32/l0/memorymap.h.
◆ USB_PMA_BASE
| #define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000) |
Definition at line 53 of file stm32/l0/memorymap.h.
◆ WWDG_BASE
| #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) |
Definition at line 43 of file stm32/l0/memorymap.h.
