NVIC

libopencm3 Cortex Nested Vectored Interrupt Controller More...

Collaboration diagram for NVIC:

Functions
void	nvic_enable_irq (uint8_t irqn)
	NVIC Enable Interrupt. More...
void	nvic_disable_irq (uint8_t irqn)
	NVIC Disable Interrupt. More...
uint8_t	nvic_get_pending_irq (uint8_t irqn)
	NVIC Return Pending Interrupt. More...
void	nvic_set_pending_irq (uint8_t irqn)
	NVIC Set Pending Interrupt. More...
void	nvic_clear_pending_irq (uint8_t irqn)
	NVIC Clear Pending Interrupt. More...
uint8_t	nvic_get_irq_enabled (uint8_t irqn)
	NVIC Return Enabled Interrupt. More...
void	nvic_set_priority (uint8_t irqn, uint8_t priority)
	NVIC Set Interrupt Priority. More...
uint8_t	nvic_get_active_irq (uint8_t irqn)
	NVIC Return Active Interrupt. More...
void	nvic_generate_software_interrupt (uint16_t irqn)
	NVIC Software Trigger Interrupt. More...

Detailed Description

libopencm3 Cortex Nested Vectored Interrupt Controller

Version

1.0.0

Author

© 2010 Thomas Otto tommi.nosp@m.@via.nosp@m.dmin..nosp@m.org

© 2012 Fergus Noble fergu.nosp@m.snob.nosp@m.le@gm.nosp@m.ail..nosp@m.com

Date

18 August 2012

Cortex processors provide 14 cortex-defined interrupts (NMI, usage faults, systicks etc.) and varying numbers of implementation defined interrupts (typically peripherial interrupts and DMA).

See also

Cortex-M3 Devices Generic User Guide

STM32F10xxx Cortex-M3 programming manual

LGPL License Terms libopencm3 License

Function Documentation

nvic_clear_pending_irq()

void nvic_clear_pending_irq

(

uint8_t

irqn

)

NVIC Clear Pending Interrupt.

Force remove a user interrupt from a pending state. This has no effect if the interrupt is actively being serviced.

Parameters

[in]

irqn

Unsigned int8. Interrupt number User interrupts for STM32 L1 series

Definition at line 112 of file nvic.c.

References NVIC_ICPR.

nvic_disable_irq()

void nvic_disable_irq

(

uint8_t

irqn

)

NVIC Disable Interrupt.

Disables a user interrupt.

Parameters

[in]

irqn

Unsigned int8. Interrupt number User interrupts for STM32 L1 series

Definition at line 70 of file nvic.c.

References NVIC_ICER.

nvic_enable_irq()

void nvic_enable_irq

(

uint8_t

irqn

)

NVIC Enable Interrupt.

Enables a user interrupt.

Parameters

[in]

irqn

Unsigned int8. Interrupt number User interrupts for STM32 L1 series

Definition at line 57 of file nvic.c.

References NVIC_ISER.

nvic_generate_software_interrupt()

void nvic_generate_software_interrupt

(

uint16_t

irqn

)

NVIC Software Trigger Interrupt.

Generate an interrupt from software. This has no effect for unprivileged access unless the privilege level has been elevated through the System Control Registers.

Parameters

[in]

irqn

Unsigned int16. Interrupt number (0 ... 239)

Definition at line 209 of file nvic.c.

References NVIC_STIR.

nvic_get_active_irq()

uint8_t nvic_get_active_irq

(

uint8_t

irqn

)

NVIC Return Active Interrupt.

Interrupt has occurred and is currently being serviced.

Parameters

[in]

irqn

Unsigned int8. Interrupt number User interrupts for STM32 L1 series

Returns

Boolean. Interrupt active.

Definition at line 194 of file nvic.c.

References NVIC_IABR.

nvic_get_irq_enabled()

uint8_t nvic_get_irq_enabled

(

uint8_t

irqn

)

NVIC Return Enabled Interrupt.

Parameters

[in]

irqn

Unsigned int8. Interrupt number User interrupts for STM32 L1 series

Returns

Boolean. Interrupt enabled.

Definition at line 126 of file nvic.c.

References NVIC_ISER.

nvic_get_pending_irq()

uint8_t nvic_get_pending_irq

(

uint8_t

irqn

)

NVIC Return Pending Interrupt.

True if the interrupt has occurred and is waiting for service.

Parameters

[in]

irqn

Unsigned int8. Interrupt number User interrupts for STM32 L1 series

Returns

Boolean. Interrupt pending.

Definition at line 84 of file nvic.c.

References NVIC_ISPR.

nvic_set_pending_irq()

void nvic_set_pending_irq

(

uint8_t

irqn

)

NVIC Set Pending Interrupt.

Force a user interrupt to a pending state. This has no effect if the interrupt is already pending.

Parameters

[in]

irqn

Unsigned int8. Interrupt number User interrupts for STM32 L1 series

Definition at line 98 of file nvic.c.

References NVIC_ISPR.

nvic_set_priority()

void nvic_set_priority	(	uint8_t	irqn,
		uint8_t	priority
	)

NVIC Set Interrupt Priority.

There are 16 priority levels only, given by the upper four bits of the priority byte, as required by ARM standards. The priority levels are interpreted according to the pre-emptive priority grouping set in the SCB Application Interrupt and Reset Control Register (SCB_AIRCR), as done in scb_set_priority_grouping,

Parameters

[in]	irqn	Interrupt number User interrupts for STM32 L1 series
[in]	priority	Interrupt priority (0 ... 255 in steps of 16)

Definition at line 152 of file nvic.c.

References NVIC_IPR, NVIC_IRQ_COUNT, and SCB_SHPR.