#include <libopencm3/cm3/memorymap.h>

Include dependency graph for stm32/l4/memorymap.h:

Macros
#define	FLASH_BASE (0x08000000U)

#define	PERIPH_BASE (0x40000000U)

#define	FMC1_BANK_BASE (0x60000000U)

#define	FMC3_BANK_BASE (0x80000000U)

#define	QUADSPI_BANK_BASE (0x90000000U)

#define	FMC_QUADSPI_BASE (0xA0000000U)

#define	INFO_BASE (0x1fff0000U)

#define	PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)

#define	PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)

#define	PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)

#define	PERIPH_BASE_AHB2 (0x48000000U)

#define	TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)

#define	TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)

#define	TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)

#define	TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)

#define	TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)

#define	TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)

#define	LCD_BASE (PERIPH_BASE_APB1 + 0x2400)

#define	RTC_BASE (PERIPH_BASE_APB1 + 0x2800)

#define	WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)

#define	IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)

#define	SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)

#define	SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)

#define	USART2_BASE (PERIPH_BASE_APB1 + 0x4400)

#define	USART3_BASE (PERIPH_BASE_APB1 + 0x4800)

#define	UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)

#define	UART5_BASE (PERIPH_BASE_APB1 + 0x5000)

#define	I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)

#define	I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)

#define	I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)

#define	CRS_BASE (PERIPH_BASE_APB1 + 0x6000)

#define	BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)

#define	BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)

#define	USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)

#define	USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)

#define	POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)

#define	DAC_BASE (PERIPH_BASE_APB1 + 0x7400)

#define	OPAMP_BASE (PERIPH_BASE_APB1 + 0x7800)

#define	LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)

#define	LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)

#define	SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)

#define	LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)

#define	SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)

#define	VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)

#define	COMP_BASE (PERIPH_BASE_APB2 + 0x0200)

#define	EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)

#define	FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)

#define	SDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)

#define	TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)

#define	SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)

#define	TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)

#define	USART1_BASE (PERIPH_BASE_APB2 + 0x3800)

#define	TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)

#define	TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)

#define	TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)

#define	SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)

#define	SAI2_BASE (PERIPH_BASE_APB2 + 0x5800)

#define	DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)

#define	DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)

#define	DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)

#define	RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)

#define	FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)

#define	CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)

#define	TSC_BASE (PERIPH_BASE_AHB1 + 0x4000)

#define	GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)

#define	GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)

#define	GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)

#define	GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)

#define	GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)

#define	GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)

#define	GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)

#define	GPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)

#define	USB_OTG_FS_BASE (0x50000000U + 0x00000)

#define	ADC1_BASE (0x50000000U + 0x40000)

#define	AES_BASE (0x50000000U + 0x60000)

#define	RNG_BASE (0x50000000U + 0x60800)

#define	FMC_BASE (0xa0000000U)

#define	QUADSPI_BASE (0xa0001000U)

#define	DBGMCU_BASE (PPBI_BASE + 0x00042000)

#define	DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)

#define	DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)

#define	DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)

#define	DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)

#define	DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)

#define	DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))

#define	ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))

#define	ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))

#define	ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))

Macro Definition Documentation

◆ ADC1_BASE

#define ADC1_BASE (0x50000000U + 0x40000)

Definition at line 111 of file stm32/l4/memorymap.h.

◆ AES_BASE

#define AES_BASE (0x50000000U + 0x60000)

Definition at line 112 of file stm32/l4/memorymap.h.

◆ BX_CAN1_BASE

#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)

Definition at line 61 of file stm32/l4/memorymap.h.

◆ BX_CAN2_BASE

#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)

Definition at line 62 of file stm32/l4/memorymap.h.

◆ COMP_BASE

#define COMP_BASE (PERIPH_BASE_APB2 + 0x0200)

Definition at line 77 of file stm32/l4/memorymap.h.

◆ CRC_BASE

#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)

Definition at line 97 of file stm32/l4/memorymap.h.

◆ CRS_BASE

#define CRS_BASE (PERIPH_BASE_APB1 + 0x6000)

Definition at line 60 of file stm32/l4/memorymap.h.

◆ DAC_BASE

#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)

Definition at line 66 of file stm32/l4/memorymap.h.

◆ DBGMCU_BASE

#define DBGMCU_BASE (PPBI_BASE + 0x00042000)

Definition at line 119 of file stm32/l4/memorymap.h.

◆ DESIG_FLASH_SIZE_BASE

#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)

Definition at line 122 of file stm32/l4/memorymap.h.

◆ DESIG_PACKAGE

#define DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))

Definition at line 127 of file stm32/l4/memorymap.h.

◆ DESIG_UNIQUE_ID0

#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)

Definition at line 124 of file stm32/l4/memorymap.h.

◆ DESIG_UNIQUE_ID1

#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)

Definition at line 125 of file stm32/l4/memorymap.h.

◆ DESIG_UNIQUE_ID2

#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)

Definition at line 126 of file stm32/l4/memorymap.h.

◆ DESIG_UNIQUE_ID_BASE

#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)

Definition at line 123 of file stm32/l4/memorymap.h.

◆ DFSDM_BASE

#define DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)

Definition at line 90 of file stm32/l4/memorymap.h.

◆ DMA1_BASE

#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)

Definition at line 93 of file stm32/l4/memorymap.h.

◆ DMA2_BASE

#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)

Definition at line 94 of file stm32/l4/memorymap.h.

◆ EXTI_BASE

#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)

Definition at line 78 of file stm32/l4/memorymap.h.

◆ FIREWALL_BASE

#define FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)

Definition at line 79 of file stm32/l4/memorymap.h.

◆ FLASH_BASE

#define FLASH_BASE (0x08000000U)

Definition at line 26 of file stm32/l4/memorymap.h.

◆ FLASH_MEM_INTERFACE_BASE

#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)

Definition at line 96 of file stm32/l4/memorymap.h.

◆ FMC1_BANK_BASE

#define FMC1_BANK_BASE (0x60000000U)

Definition at line 28 of file stm32/l4/memorymap.h.

◆ FMC3_BANK_BASE

#define FMC3_BANK_BASE (0x80000000U)

Definition at line 29 of file stm32/l4/memorymap.h.

◆ FMC_BASE

#define FMC_BASE (0xa0000000U)

Definition at line 115 of file stm32/l4/memorymap.h.

◆ FMC_QUADSPI_BASE

#define FMC_QUADSPI_BASE (0xA0000000U)

Definition at line 31 of file stm32/l4/memorymap.h.

◆ GPIO_PORT_A_BASE

#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)

Definition at line 101 of file stm32/l4/memorymap.h.

◆ GPIO_PORT_B_BASE

#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)

Definition at line 102 of file stm32/l4/memorymap.h.

◆ GPIO_PORT_C_BASE

#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)

Definition at line 103 of file stm32/l4/memorymap.h.

◆ GPIO_PORT_D_BASE

#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)

Definition at line 104 of file stm32/l4/memorymap.h.

◆ GPIO_PORT_E_BASE

#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)

Definition at line 105 of file stm32/l4/memorymap.h.

◆ GPIO_PORT_F_BASE

#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)

Definition at line 106 of file stm32/l4/memorymap.h.

◆ GPIO_PORT_G_BASE

#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)

Definition at line 107 of file stm32/l4/memorymap.h.

◆ GPIO_PORT_H_BASE

#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)

Definition at line 108 of file stm32/l4/memorymap.h.

◆ I2C1_BASE

#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)

Definition at line 57 of file stm32/l4/memorymap.h.

◆ I2C2_BASE

#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)

Definition at line 58 of file stm32/l4/memorymap.h.

◆ I2C3_BASE

#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)

Definition at line 59 of file stm32/l4/memorymap.h.

◆ INFO_BASE

#define INFO_BASE (0x1fff0000U)

Definition at line 32 of file stm32/l4/memorymap.h.

◆ IWDG_BASE

#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)

Definition at line 50 of file stm32/l4/memorymap.h.

◆ LCD_BASE

#define LCD_BASE (PERIPH_BASE_APB1 + 0x2400)

Definition at line 47 of file stm32/l4/memorymap.h.

◆ LPTIM1_BASE

#define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)

Definition at line 68 of file stm32/l4/memorymap.h.

◆ LPTIM2_BASE

#define LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)

Definition at line 71 of file stm32/l4/memorymap.h.

◆ LPUART1_BASE

#define LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)

Definition at line 69 of file stm32/l4/memorymap.h.

◆ OPAMP_BASE

#define OPAMP_BASE (PERIPH_BASE_APB1 + 0x7800)

Definition at line 67 of file stm32/l4/memorymap.h.

◆ PERIPH_BASE

#define PERIPH_BASE (0x40000000U)

Definition at line 27 of file stm32/l4/memorymap.h.

◆ PERIPH_BASE_AHB1

#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)

Definition at line 35 of file stm32/l4/memorymap.h.

◆ PERIPH_BASE_AHB2

#define PERIPH_BASE_AHB2 (0x48000000U)

Definition at line 36 of file stm32/l4/memorymap.h.

◆ PERIPH_BASE_APB1

#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)

Definition at line 33 of file stm32/l4/memorymap.h.

◆ PERIPH_BASE_APB2

#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)

Definition at line 34 of file stm32/l4/memorymap.h.

◆ POWER_CONTROL_BASE

#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)

Definition at line 65 of file stm32/l4/memorymap.h.

◆ QUADSPI_BANK_BASE

#define QUADSPI_BANK_BASE (0x90000000U)

Definition at line 30 of file stm32/l4/memorymap.h.

◆ QUADSPI_BASE

#define QUADSPI_BASE (0xa0001000U)

Definition at line 116 of file stm32/l4/memorymap.h.

◆ RCC_BASE

#define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)

Definition at line 95 of file stm32/l4/memorymap.h.

◆ RNG_BASE

#define RNG_BASE (0x50000000U + 0x60800)

Definition at line 113 of file stm32/l4/memorymap.h.

◆ RTC_BASE

#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)

Definition at line 48 of file stm32/l4/memorymap.h.

◆ SAI1_BASE

#define SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)

Definition at line 88 of file stm32/l4/memorymap.h.

◆ SAI2_BASE

#define SAI2_BASE (PERIPH_BASE_APB2 + 0x5800)

Definition at line 89 of file stm32/l4/memorymap.h.

◆ SDMMC1_BASE

#define SDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)

Definition at line 80 of file stm32/l4/memorymap.h.

◆ SPI1_BASE

#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)

Definition at line 82 of file stm32/l4/memorymap.h.

◆ SPI2_BASE

#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)

Definition at line 51 of file stm32/l4/memorymap.h.

◆ SPI3_BASE

#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)

Definition at line 52 of file stm32/l4/memorymap.h.

◆ ST_TSENSE_CAL1_30C

#define ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))

Definition at line 131 of file stm32/l4/memorymap.h.

◆ ST_TSENSE_CAL2_110C

#define ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))

Definition at line 132 of file stm32/l4/memorymap.h.

◆ ST_VREFINT_CAL

#define ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))

Definition at line 130 of file stm32/l4/memorymap.h.

◆ SWPMI1_BASE

#define SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)

Definition at line 70 of file stm32/l4/memorymap.h.

◆ SYSCFG_BASE

#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)

Definition at line 75 of file stm32/l4/memorymap.h.

◆ TIM15_BASE

#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)

Definition at line 85 of file stm32/l4/memorymap.h.

◆ TIM16_BASE

#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)

Definition at line 86 of file stm32/l4/memorymap.h.

◆ TIM17_BASE

#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)

Definition at line 87 of file stm32/l4/memorymap.h.

◆ TIM1_BASE

#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)

Definition at line 81 of file stm32/l4/memorymap.h.

◆ TIM2_BASE

#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)

Definition at line 41 of file stm32/l4/memorymap.h.

◆ TIM3_BASE

#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)

Definition at line 42 of file stm32/l4/memorymap.h.

◆ TIM4_BASE

#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)

Definition at line 43 of file stm32/l4/memorymap.h.

◆ TIM5_BASE

#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)

Definition at line 44 of file stm32/l4/memorymap.h.

◆ TIM6_BASE

#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)

Definition at line 45 of file stm32/l4/memorymap.h.

◆ TIM7_BASE

#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)

Definition at line 46 of file stm32/l4/memorymap.h.

◆ TIM8_BASE

#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)

Definition at line 83 of file stm32/l4/memorymap.h.

◆ TSC_BASE

#define TSC_BASE (PERIPH_BASE_AHB1 + 0x4000)

Definition at line 98 of file stm32/l4/memorymap.h.

◆ UART4_BASE

#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)

Definition at line 55 of file stm32/l4/memorymap.h.

◆ UART5_BASE

#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000)

Definition at line 56 of file stm32/l4/memorymap.h.

◆ USART1_BASE

#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)

Definition at line 84 of file stm32/l4/memorymap.h.

◆ USART2_BASE

#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)

Definition at line 53 of file stm32/l4/memorymap.h.

◆ USART3_BASE

#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)

Definition at line 54 of file stm32/l4/memorymap.h.

◆ USB_DEV_FS_BASE

#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)

Definition at line 63 of file stm32/l4/memorymap.h.

◆ USB_OTG_FS_BASE

#define USB_OTG_FS_BASE (0x50000000U + 0x00000)

Definition at line 110 of file stm32/l4/memorymap.h.

◆ USB_PMA_BASE

#define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)

Definition at line 64 of file stm32/l4/memorymap.h.

◆ VREFBUF_BASE

#define VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)

Definition at line 76 of file stm32/l4/memorymap.h.

◆ WWDG_BASE

#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)

Definition at line 49 of file stm32/l4/memorymap.h.

Macros