Mask used to set the clock divider
Collaboration diagram for Mask used to set the clock divider:
Macros | |
| #define | CLK_MASK 0xFFFFFC00 |
Functions | |
| void | clk_speed (enum clk_speeds mhz, uint16_t div) |
| Setup and change the system clock multiplier and divider. More... | |
Detailed Description
Macro Definition Documentation
◆ CLK_MASK
Function Documentation
◆ clk_speed()
| void clk_speed | ( | enum clk_speeds | mhz, |
| uint16_t | div | ||
| ) |
Setup and change the system clock multiplier and divider.
Change system clock speed and wait for the clock to stabilize. The clock only needs time to stabilize on the first invocation of this function. This should be run at startup if you want to have a stable clock before doing anything.
- Parameters
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[in] mhz Base clock speed Base Clock Speeds The base clock speed, before the clock divider [in] div Clock divider Takes values from 0 to 1023 (in reality the possible values are the even numbers from 2 to 1022, as well as the number 1). Anything more than the first 10 bits is stripped off of the value. If the value is 0, it will be treated as a 1. All odd values other than 1 are rounded down to the closest even value, due to the fact that all odd values are treated by the register as a 1, which would likely be unexpected. A value of 0 would also normally be treated as a 2, which would also be unexpected behavior.
Definition at line 50 of file clk.c.
References BIT0, CLK_18MHZ, CLK_36MHZ, CLK_MASK, clk_speed(), SYSCTL_SYS_CFG_0, and SYSCTL_SYS_DBLF.
Referenced by clk_speed().
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