|
| #define | GPIOA GPIO_PORT_A_BASE |
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| #define | GPIOB GPIO_PORT_B_BASE |
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| #define | GPIOC GPIO_PORT_C_BASE |
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| #define | GPIOD GPIO_PORT_D_BASE |
| |
| #define | GPIOE GPIO_PORT_E_BASE |
| |
| #define | GPIOF GPIO_PORT_F_BASE |
| |
| #define | GPIOG GPIO_PORT_G_BASE |
| |
| #define | GPIO_CAN1_RX GPIO11 /* PA11 */ |
| |
| #define | GPIO_CAN1_TX GPIO12 /* PA12 */ |
| |
| #define | GPIO_CAN_RX GPIO_CAN1_RX /* Alias */ |
| |
| #define | GPIO_CAN_TX GPIO_CAN1_TX /* Alias */ |
| |
| #define | GPIO_CAN_PB_RX GPIO8 /* PB8 */ |
| |
| #define | GPIO_CAN_PB_TX GPIO9 /* PB9 */ |
| |
| #define | GPIO_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */ |
| |
| #define | GPIO_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */ |
| |
| #define | GPIO_CAN_PD_RX GPIO0 /* PD0 */ |
| |
| #define | GPIO_CAN_PD_TX GPIO1 /* PD1 */ |
| |
| #define | GPIO_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */ |
| |
| #define | GPIO_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */ |
| |
| #define | GPIO_BANK_CAN1_RX GPIOA /* PA11 */ |
| |
| #define | GPIO_BANK_CAN1_TX GPIOA /* PA12 */ |
| |
| #define | GPIO_BANK_CAN_RX GPIO_BANK_CAN1_RX /* Alias */ |
| |
| #define | GPIO_BANK_CAN_TX GPIO_BANK_CAN1_TX /* Alias */ |
| |
| #define | GPIO_BANK_CAN_PB_RX GPIOB /* PB8 */ |
| |
| #define | GPIO_BANK_CAN_PB_TX GPIOB /* PB9 */ |
| |
| #define | GPIO_BANK_CAN1_PB_RX GPIO_BANK_CAN_PB_RX /* Alias */ |
| |
| #define | GPIO_BANK_CAN1_PB_TX GPIO_BANK_CAN_PB_TX /* Alias */ |
| |
| #define | GPIO_BANK_CAN_PD_RX GPIOD /* PD0 */ |
| |
| #define | GPIO_BANK_CAN_PD_TX GPIOD /* PD1 */ |
| |
| #define | GPIO_BANK_CAN1_PD_RX GPIO_BANK_CAN_PD_RX /* Alias */ |
| |
| #define | GPIO_BANK_CAN1_PD_TX GPIO_BANK_CAN_PD_TX /* Alias */ |
| |
| #define | GPIO_CAN2_RX GPIO12 /* PB12 */ |
| |
| #define | GPIO_CAN2_TX GPIO13 /* PB13 */ |
| |
| #define | GPIO_CAN2_RE_RX GPIO5 /* PB5 */ |
| |
| #define | GPIO_CAN2_RE_TX GPIO6 /* PB6 */ |
| |
| #define | GPIO_BANK_CAN2_RX GPIOB /* PB12 */ |
| |
| #define | GPIO_BANK_CAN2_TX GPIOB /* PB13 */ |
| |
| #define | GPIO_BANK_CAN2_RE_RX GPIOB /* PB5 */ |
| |
| #define | GPIO_BANK_CAN2_RE_TX GPIOB /* PB6 */ |
| |
| #define | GPIO_JTMS_SWDIO GPIO13 /* PA13 */ |
| |
| #define | GPIO_JTCK_SWCLK GPIO14 /* PA14 */ |
| |
| #define | GPIO_JTDI GPIO15 /* PA15 */ |
| |
| #define | GPIO_JTDO_TRACESWO GPIO3 /* PB3 */ |
| |
| #define | GPIO_JNTRST GPIO4 /* PB4 */ |
| |
| #define | GPIO_TRACECK GPIO2 /* PE2 */ |
| |
| #define | GPIO_TRACED0 GPIO3 /* PE3 */ |
| |
| #define | GPIO_TRACED1 GPIO4 /* PE4 */ |
| |
| #define | GPIO_TRACED2 GPIO5 /* PE5 */ |
| |
| #define | GPIO_TRACED3 GPIO6 /* PE6 */ |
| |
| #define | GPIO_BANK_JTMS_SWDIO GPIOA /* PA13 */ |
| |
| #define | GPIO_BANK_JTCK_SWCLK GPIOA /* PA14 */ |
| |
| #define | GPIO_BANK_JTDI GPIOA /* PA15 */ |
| |
| #define | GPIO_BANK_JTDO_TRACESWO GPIOB /* PB3 */ |
| |
| #define | GPIO_BANK_JNTRST GPIOB /* PB4 */ |
| |
| #define | GPIO_BANK_TRACECK GPIOE /* PE2 */ |
| |
| #define | GPIO_BANK_TRACED0 GPIOE /* PE3 */ |
| |
| #define | GPIO_BANK_TRACED1 GPIOE /* PE4 */ |
| |
| #define | GPIO_BANK_TRACED2 GPIOE /* PE5 */ |
| |
| #define | GPIO_BANK_TRACED3 GPIOE /* PE6 */ |
| |
| #define | GPIO_TIM5_CH1 GPIO0 /* PA0 */ |
| |
| #define | GPIO_TIM5_CH2 GPIO1 /* PA1 */ |
| |
| #define | GPIO_TIM5_CH3 GPIO2 /* PA2 */ |
| |
| #define | GPIO_TIM5_CH4 GPIO3 /* PA3 */ |
| |
| #define | GPIO_BANK_TIM5_CH1 GPIOA /* PA0 */ |
| |
| #define | GPIO_BANK_TIM5_CH2 GPIOA /* PA1 */ |
| |
| #define | GPIO_BANK_TIM5_CH3 GPIOA /* PA2 */ |
| |
| #define | GPIO_BANK_TIM5_CH4 GPIOA /* PA3 */ |
| |
| #define | GPIO_BANK_TIM5 GPIOA |
| |
| #define | GPIO_TIM4_CH1 GPIO6 /* PB6 */ |
| |
| #define | GPIO_TIM4_CH2 GPIO7 /* PB7 */ |
| |
| #define | GPIO_TIM4_CH3 GPIO8 /* PB8 */ |
| |
| #define | GPIO_TIM4_CH4 GPIO9 /* PB9 */ |
| |
| #define | GPIO_TIM4_RE_CH1 GPIO12 /* PD12 */ |
| |
| #define | GPIO_TIM4_RE_CH2 GPIO13 /* PD13 */ |
| |
| #define | GPIO_TIM4_RE_CH3 GPIO14 /* PD14 */ |
| |
| #define | GPIO_TIM4_RE_CH4 GPIO15 /* PD15 */ |
| |
| #define | GPIO_BANK_TIM4_CH1 GPIOB /* PB6 */ |
| |
| #define | GPIO_BANK_TIM4_CH2 GPIOB /* PB7 */ |
| |
| #define | GPIO_BANK_TIM4_CH3 GPIOB /* PB8 */ |
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| #define | GPIO_BANK_TIM4_CH4 GPIOB /* PB9 */ |
| |
| #define | GPIO_BANK_TIM4 GPIOB |
| |
| #define | GPIO_BANK_TIM4_RE_CH1 GPIOD /* PD12 */ |
| |
| #define | GPIO_BANK_TIM4_RE_CH2 GPIOD /* PD13 */ |
| |
| #define | GPIO_BANK_TIM4_RE_CH3 GPIOD /* PD14 */ |
| |
| #define | GPIO_BANK_TIM4_RE_CH4 GPIOD /* PD15 */ |
| |
| #define | GPIO_BANK_TIM4_RE GPIOD |
| |
| #define | GPIO_TIM3_CH1 GPIO6 /* PA6 */ |
| |
| #define | GPIO_TIM3_CH2 GPIO7 /* PA7 */ |
| |
| #define | GPIO_TIM3_CH3 GPIO0 /* PB0 */ |
| |
| #define | GPIO_TIM3_CH4 GPIO1 /* PB1 */ |
| |
| #define | GPIO_TIM3_PR_CH1 GPIO4 /* PB4 */ |
| |
| #define | GPIO_TIM3_PR_CH2 GPIO5 /* PB5 */ |
| |
| #define | GPIO_TIM3_PR_CH3 GPIO0 /* PB0 */ |
| |
| #define | GPIO_TIM3_PR_CH4 GPIO1 /* PB1 */ |
| |
| #define | GPIO_TIM3_FR_CH1 GPIO6 /* PC6 */ |
| |
| #define | GPIO_TIM3_FR_CH2 GPIO7 /* PC7 */ |
| |
| #define | GPIO_TIM3_FR_CH3 GPIO8 /* PC8 */ |
| |
| #define | GPIO_TIM3_FR_CH4 GPIO9 /* PC9 */ |
| |
| #define | GPIO_BANK_TIM3_CH1 GPIOA /* PA6 */ |
| |
| #define | GPIO_BANK_TIM3_CH2 GPIOA /* PA7 */ |
| |
| #define | GPIO_BANK_TIM3_CH3 GPIOB /* PB0 */ |
| |
| #define | GPIO_BANK_TIM3_CH4 GPIOB /* PB1 */ |
| |
| #define | GPIO_BANK_TIM3_CH12 GPIOA |
| |
| #define | GPIO_BANK_TIM3_CH34 GPIOB |
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| #define | GPIO_BANK_TIM3_PR_CH1 GPIOB /* PB4 */ |
| |
| #define | GPIO_BANK_TIM3_PR_CH2 GPIOB /* PB5 */ |
| |
| #define | GPIO_BANK_TIM3_PR_CH3 GPIOB /* PB0 */ |
| |
| #define | GPIO_BANK_TIM3_PR_CH4 GPIOB /* PB1 */ |
| |
| #define | GPIO_BANK_TIM3_PR GPIOB |
| |
| #define | GPIO_BANK_TIM3_FR_CH1 GPIOC /* PC6 */ |
| |
| #define | GPIO_BANK_TIM3_FR_CH2 GPIOC /* PC7 */ |
| |
| #define | GPIO_BANK_TIM3_FR_CH3 GPIOC /* PC8 */ |
| |
| #define | GPIO_BANK_TIM3_FR_CH4 GPIOC /* PC9 */ |
| |
| #define | GPIO_BANK_TIM3_FR GPIOC |
| |
| #define | GPIO_TIM2_CH1_ETR GPIO0 /* PA0 */ |
| |
| #define | GPIO_TIM2_CH2 GPIO1 /* PA1 */ |
| |
| #define | GPIO_TIM2_CH3 GPIO2 /* PA2 */ |
| |
| #define | GPIO_TIM2_CH4 GPIO3 /* PA3 */ |
| |
| #define | GPIO_TIM2_PR1_CH1_ETR GPIO15 /* PA15 */ |
| |
| #define | GPIO_TIM2_PR1_CH2 GPIO3 /* PB3 */ |
| |
| #define | GPIO_TIM2_PR1_CH3 GPIO2 /* PA2 */ |
| |
| #define | GPIO_TIM2_PR1_CH4 GPIO3 /* PA3 */ |
| |
| #define | GPIO_TIM2_PR2_CH1_ETR GPIO0 /* PA0 */ |
| |
| #define | GPIO_TIM2_PR2_CH2 GPIO1 /* PA1 */ |
| |
| #define | GPIO_TIM2_PR2_CH3 GPIO10 /* PB10 */ |
| |
| #define | GPIO_TIM2_PR2_CH4 GPIO11 /* PB11 */ |
| |
| #define | GPIO_TIM2_FR_CH1_ETR GPIO15 /* PA15 */ |
| |
| #define | GPIO_TIM2_FR_CH2 GPIO3 /* PB3 */ |
| |
| #define | GPIO_TIM2_FR_CH3 GPIO10 /* PB10 */ |
| |
| #define | GPIO_TIM2_FR_CH4 GPIO11 /* PB11 */ |
| |
| #define | GPIO_BANK_TIM2_CH1_ETR GPIOA /* PA0 */ |
| |
| #define | GPIO_BANK_TIM2_CH2 GPIOA /* PA1 */ |
| |
| #define | GPIO_BANK_TIM2_CH3 GPIOA /* PA2 */ |
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| #define | GPIO_BANK_TIM2_CH4 GPIOA /* PA3 */ |
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| #define | GPIO_BANK_TIM2 GPIOA |
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| #define | GPIO_BANK_TIM2_PR1_CH1_ETR GPIOA /* PA15 */ |
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| #define | GPIO_BANK_TIM2_PR1_CH2 GPIOB /* PB3 */ |
| |
| #define | GPIO_BANK_TIM2_PR1_CH3 GPIOA /* PA2 */ |
| |
| #define | GPIO_BANK_TIM2_PR1_CH4 GPIOA /* PA3 */ |
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| #define | GPIO_BANK_TIM2_PR1_CH134 GPIOA |
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| #define | GPIO_BANK_TIM2_PR2_CH1_ETR GPIOA /* PA0 */ |
| |
| #define | GPIO_BANK_TIM2_PR2_CH2 GPIOA /* PA1 */ |
| |
| #define | GPIO_BANK_TIM2_PR2_CH3 GPIOB /* PB10 */ |
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| #define | GPIO_BANK_TIM2_PR2_CH4 GPIOB /* PB11 */ |
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| #define | GPIO_BANK_TIM2_PR2_CH12 GPIOA |
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| #define | GPIO_BANK_TIM2_PR2_CH34 GPIOB |
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| #define | GPIO_BANK_TIM2_FR_CH1_ETR GPIOA /* PA15 */ |
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| #define | GPIO_BANK_TIM2_FR_CH2 GPIOB /* PB3 */ |
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| #define | GPIO_BANK_TIM2_FR_CH3 GPIOB /* PB10 */ |
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| #define | GPIO_BANK_TIM2_FR_CH4 GPIOB /* PB11 */ |
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| #define | GPIO_BANK_TIM2_FR_CH234 GPIOB |
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| #define | GPIO_TIM1_ETR GPIO12 /* PA12 */ |
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| #define | GPIO_TIM1_CH1 GPIO8 /* PA8 */ |
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| #define | GPIO_TIM1_CH2 GPIO9 /* PA9 */ |
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| #define | GPIO_TIM1_CH3 GPIO10 /* PA10 */ |
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| #define | GPIO_TIM1_CH4 GPIO11 /* PA11 */ |
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| #define | GPIO_TIM1_BKIN GPIO12 /* PB12 */ |
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| #define | GPIO_TIM1_CH1N GPIO13 /* PB13 */ |
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| #define | GPIO_TIM1_CH2N GPIO14 /* PB14 */ |
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| #define | GPIO_TIM1_CH3N GPIO15 /* PB15 */ |
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| #define | GPIO_TIM1_PR_ETR GPIO12 /* PA12 */ |
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| #define | GPIO_TIM1_PR_CH1 GPIO8 /* PA8 */ |
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| #define | GPIO_TIM1_PR_CH2 GPIO9 /* PA9 */ |
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| #define | GPIO_TIM1_PR_CH3 GPIO10 /* PA10 */ |
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| #define | GPIO_TIM1_PR_CH4 GPIO11 /* PA11 */ |
| |
| #define | GPIO_TIM1_PR_BKIN GPIO6 /* PA6 */ |
| |
| #define | GPIO_TIM1_PR_CH1N GPIO7 /* PA7 */ |
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| #define | GPIO_TIM1_PR_CH2N GPIO0 /* PB0 */ |
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| #define | GPIO_TIM1_PR_CH3N GPIO1 /* PB1 */ |
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| #define | GPIO_TIM1_FR_ETR GPIO7 /* PE7 */ |
| |
| #define | GPIO_TIM1_FR_CH1 GPIO9 /* PE9 */ |
| |
| #define | GPIO_TIM1_FR_CH2 GPIO11 /* PE11 */ |
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| #define | GPIO_TIM1_FR_CH3 GPIO13 /* PE13 */ |
| |
| #define | GPIO_TIM1_FR_CH4 GPIO14 /* PE14 */ |
| |
| #define | GPIO_TIM1_FR_BKIN GPIO15 /* PE15 */ |
| |
| #define | GPIO_TIM1_FR_CH1N GPIO8 /* PE8 */ |
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| #define | GPIO_TIM1_FR_CH2N GPIO10 /* PE10 */ |
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| #define | GPIO_TIM1_FR_CH3N GPIO12 /* PE12 */ |
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| #define | GPIO_BANK_TIM1_ETR GPIOA /* PA12 */ |
| |
| #define | GPIO_BANK_TIM1_CH1 GPIOA /* PA8 */ |
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| #define | GPIO_BANK_TIM1_CH2 GPIOA /* PA9 */ |
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| #define | GPIO_BANK_TIM1_CH3 GPIOA /* PA10 */ |
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| #define | GPIO_BANK_TIM1_CH4 GPIOA /* PA11 */ |
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| #define | GPIO_BANK_TIM1_BKIN GPIOB /* PB12 */ |
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| #define | GPIO_BANK_TIM1_CH1N GPIOB /* PB13 */ |
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| #define | GPIO_BANK_TIM1_CH2N GPIOB /* PB14 */ |
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| #define | GPIO_BANK_TIM1_CH3N GPIOB /* PB15 */ |
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| #define | GPIO_BANK_TIM1_ETR_CH1234 GPIOA |
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| #define | GPIO_BANK_TIM1_BKIN_CH123N GPIOB |
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| #define | GPIO_BANK_TIM1_PR_ETR GPIOA /* PA12 */ |
| |
| #define | GPIO_BANK_TIM1_PR_CH1 GPIOA /* PA8 */ |
| |
| #define | GPIO_BANK_TIM1_PR_CH2 GPIOA /* PA9 */ |
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| #define | GPIO_BANK_TIM1_PR_CH3 GPIOA /* PA10 */ |
| |
| #define | GPIO_BANK_TIM1_PR_CH4 GPIOA /* PA11 */ |
| |
| #define | GPIO_BANK_TIM1_PR_BKIN GPIOA /* PA6 */ |
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| #define | GPIO_BANK_TIM1_PR_CH1N GPIOA /* PA7 */ |
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| #define | GPIO_BANK_TIM1_PR_CH2N GPIOB /* PB0 */ |
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| #define | GPIO_BANK_TIM1_PR_CH3N GPIOB /* PB1 */ |
| |
| #define | GPIO_BANK_TIM1_PR_ETR_CH1234_BKIN_CH1N GPIOA |
| |
| #define | GPIO_BANK_TIM1_PR_CH23N GPIOB |
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| #define | GPIO_BANK_TIM1_FR_ETR GPIOE /* PE7 */ |
| |
| #define | GPIO_BANK_TIM1_FR_CH1 GPIOE /* PE9 */ |
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| #define | GPIO_BANK_TIM1_FR_CH2 GPIOE /* PE11 */ |
| |
| #define | GPIO_BANK_TIM1_FR_CH3 GPIOE /* PE13 */ |
| |
| #define | GPIO_BANK_TIM1_FR_CH4 GPIOE /* PE14 */ |
| |
| #define | GPIO_BANK_TIM1_FR_BKIN GPIOE /* PE15 */ |
| |
| #define | GPIO_BANK_TIM1_FR_CH1N GPIOE /* PE8 */ |
| |
| #define | GPIO_BANK_TIM1_FR_CH2N GPIOE /* PE10 */ |
| |
| #define | GPIO_BANK_TIM1_FR_CH3N GPIOE /* PE12 */ |
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| #define | GPIO_BANK_TIM1_FR GPIOE |
| |
| #define | GPIO_UART5_TX GPIO12 /* PC12 */ |
| |
| #define | GPIO_UART5_RX GPIO2 /* PD2 */ |
| |
| #define | GPIO_BANK_UART5_TX GPIOC /* PC12 */ |
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| #define | GPIO_BANK_UART5_RX GPIOD /* PD2 */ |
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| #define | GPIO_UART4_TX GPIO10 /* PC10 */ |
| |
| #define | GPIO_UART4_RX GPIO11 /* PC11 */ |
| |
| #define | GPIO_BANK_UART4_TX GPIOC /* PC10 */ |
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| #define | GPIO_BANK_UART4_RX GPIOC /* PC11 */ |
| |
| #define | GPIO_USART3_TX GPIO10 /* PB10 */ |
| |
| #define | GPIO_USART3_RX GPIO11 /* PB11 */ |
| |
| #define | GPIO_USART3_CK GPIO12 /* PB12 */ |
| |
| #define | GPIO_USART3_CTS GPIO13 /* PB13 */ |
| |
| #define | GPIO_USART3_RTS GPIO14 /* PB14 */ |
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| #define | GPIO_USART3_PR_TX GPIO10 /* PC10 */ |
| |
| #define | GPIO_USART3_PR_RX GPIO11 /* PC11 */ |
| |
| #define | GPIO_USART3_PR_CK GPIO12 /* PC12 */ |
| |
| #define | GPIO_USART3_PR_CTS GPIO13 /* PB13 */ |
| |
| #define | GPIO_USART3_PR_RTS GPIO14 /* PB14 */ |
| |
| #define | GPIO_USART3_FR_TX GPIO8 /* PD8 */ |
| |
| #define | GPIO_USART3_FR_RX GPIO9 /* PD9 */ |
| |
| #define | GPIO_USART3_FR_CK GPIO10 /* PD10 */ |
| |
| #define | GPIO_USART3_FR_CTS GPIO11 /* PD11 */ |
| |
| #define | GPIO_USART3_FR_RTS GPIO12 /* PD12 */ |
| |
| #define | GPIO_BANK_USART3_TX GPIOB /* PB10 */ |
| |
| #define | GPIO_BANK_USART3_RX GPIOB /* PB11 */ |
| |
| #define | GPIO_BANK_USART3_CK GPIOB /* PB12 */ |
| |
| #define | GPIO_BANK_USART3_CTS GPIOB /* PB13 */ |
| |
| #define | GPIO_BANK_USART3_RTS GPIOB /* PB14 */ |
| |
| #define | GPIO_BANK_USART3_PR_TX GPIOC /* PC10 */ |
| |
| #define | GPIO_BANK_USART3_PR_RX GPIOC /* PC11 */ |
| |
| #define | GPIO_BANK_USART3_PR_CK GPIOC /* PC12 */ |
| |
| #define | GPIO_BANK_USART3_PR_CTS GPIOB /* PB13 */ |
| |
| #define | GPIO_BANK_USART3_PR_RTS GPIOB /* PB14 */ |
| |
| #define | GPIO_BANK_USART3_FR_TX GPIOD /* PD8 */ |
| |
| #define | GPIO_BANK_USART3_FR_RX GPIOD /* PD9 */ |
| |
| #define | GPIO_BANK_USART3_FR_CK GPIOD /* PD10 */ |
| |
| #define | GPIO_BANK_USART3_FR_CTS GPIOD /* PD11 */ |
| |
| #define | GPIO_BANK_USART3_FR_RTS GPIOD /* PD12 */ |
| |
| #define | GPIO_USART2_CTS GPIO0 /* PA0 */ |
| |
| #define | GPIO_USART2_RTS GPIO1 /* PA1 */ |
| |
| #define | GPIO_USART2_TX GPIO2 /* PA2 */ |
| |
| #define | GPIO_USART2_RX GPIO3 /* PA3 */ |
| |
| #define | GPIO_USART2_CK GPIO4 /* PA4 */ |
| |
| #define | GPIO_USART2_RE_CTS GPIO3 /* PD3 */ |
| |
| #define | GPIO_USART2_RE_RTS GPIO4 /* PD4 */ |
| |
| #define | GPIO_USART2_RE_TX GPIO5 /* PD5 */ |
| |
| #define | GPIO_USART2_RE_RX GPIO6 /* PD6 */ |
| |
| #define | GPIO_USART2_RE_CK GPIO7 /* PD7 */ |
| |
| #define | GPIO_BANK_USART2_CTS GPIOA /* PA0 */ |
| |
| #define | GPIO_BANK_USART2_RTS GPIOA /* PA1 */ |
| |
| #define | GPIO_BANK_USART2_TX GPIOA /* PA2 */ |
| |
| #define | GPIO_BANK_USART2_RX GPIOA /* PA3 */ |
| |
| #define | GPIO_BANK_USART2_CK GPIOA /* PA4 */ |
| |
| #define | GPIO_BANK_USART2_RE_CTS GPIOD /* PD3 */ |
| |
| #define | GPIO_BANK_USART2_RE_RTS GPIOD /* PD4 */ |
| |
| #define | GPIO_BANK_USART2_RE_TX GPIOD /* PD5 */ |
| |
| #define | GPIO_BANK_USART2_RE_RX GPIOD /* PD6 */ |
| |
| #define | GPIO_BANK_USART2_RE_CK GPIOD /* PD7 */ |
| |
| #define | GPIO_USART1_CTS GPIO11 /* PA11 */ |
| |
| #define | GPIO_USART1_RTS GPIO12 /* PA12 */ |
| |
| #define | GPIO_USART1_TX GPIO9 /* PA9 */ |
| |
| #define | GPIO_USART1_RX GPIO10 /* PA10 */ |
| |
| #define | GPIO_USART1_CK GPIO8 /* PA8 */ |
| |
| #define | GPIO_USART1_RE_TX GPIO6 /* PB6 */ |
| |
| #define | GPIO_USART1_RE_RX GPIO7 /* PB7 */ |
| |
| #define | GPIO_BANK_USART1_CTS GPIOA /* PA11 */ |
| |
| #define | GPIO_BANK_USART1_RTS GPIOA /* PA12 */ |
| |
| #define | GPIO_BANK_USART1_TX GPIOA /* PA9 */ |
| |
| #define | GPIO_BANK_USART1_RX GPIOA /* PA10 */ |
| |
| #define | GPIO_BANK_USART1_CK GPIOA /* PA8 */ |
| |
| #define | GPIO_BANK_USART1_RE_TX GPIOB /* PB6 */ |
| |
| #define | GPIO_BANK_USART1_RE_RX GPIOB /* PB7 */ |
| |
| #define | GPIO_I2C1_SMBAI GPIO5 /* PB5 */ |
| |
| #define | GPIO_I2C1_SCL GPIO6 /* PB6 */ |
| |
| #define | GPIO_I2C1_SDA GPIO7 /* PB7 */ |
| |
| #define | GPIO_I2C1_RE_SMBAI GPIO5 /* PB5 */ |
| |
| #define | GPIO_I2C1_RE_SCL GPIO8 /* PB8 */ |
| |
| #define | GPIO_I2C1_RE_SDA GPIO9 /* PB9 */ |
| |
| #define | GPIO_BANK_I2C1_SMBAI GPIOB /* PB5 */ |
| |
| #define | GPIO_BANK_I2C1_SCL GPIOB /* PB6 */ |
| |
| #define | GPIO_BANK_I2C1_SDA GPIOB /* PB7 */ |
| |
| #define | GPIO_BANK_I2C1_RE_SMBAI GPIOB /* PB5 */ |
| |
| #define | GPIO_BANK_I2C1_RE_SCL GPIOB /* PB8 */ |
| |
| #define | GPIO_BANK_I2C1_RE_SDA GPIOB /* PB9 */ |
| |
| #define | GPIO_I2C2_SCL GPIO10 /* PB10 */ |
| |
| #define | GPIO_I2C2_SDA GPIO11 /* PB11 */ |
| |
| #define | GPIO_I2C2_SMBAI GPIO12 /* PB12 */ |
| |
| #define | GPIO_BANK_I2C2_SCL GPIOB /* PB10 */ |
| |
| #define | GPIO_BANK_I2C2_SDA GPIOB /* PB11 */ |
| |
| #define | GPIO_BANK_I2C2_SMBAI GPIOB /* PB12 */ |
| |
| #define | GPIO_SPI1_NSS GPIO4 /* PA4 */ |
| |
| #define | GPIO_SPI1_SCK GPIO5 /* PA5 */ |
| |
| #define | GPIO_SPI1_MISO GPIO6 /* PA6 */ |
| |
| #define | GPIO_SPI1_MOSI GPIO7 /* PA7 */ |
| |
| #define | GPIO_SPI1_RE_NSS GPIO15 /* PA15 */ |
| |
| #define | GPIO_SPI1_RE_SCK GPIO3 /* PB3 */ |
| |
| #define | GPIO_SPI1_RE_MISO GPIO4 /* PB4 */ |
| |
| #define | GPIO_SPI1_RE_MOSI GPIO5 /* PB5 */ |
| |
| #define | GPIO_BANK_SPI1_NSS GPIOA /* PA4 */ |
| |
| #define | GPIO_BANK_SPI1_SCK GPIOA /* PA5 */ |
| |
| #define | GPIO_BANK_SPI1_MISO GPIOA /* PA6 */ |
| |
| #define | GPIO_BANK_SPI1_MOSI GPIOA /* PA7 */ |
| |
| #define | GPIO_BANK_SPI1_RE_NSS GPIOA /* PA15 */ |
| |
| #define | GPIO_BANK_SPI1_RE_SCK GPIOB /* PB3 */ |
| |
| #define | GPIO_BANK_SPI1_RE_MISO GPIOB /* PB4 */ |
| |
| #define | GPIO_BANK_SPI1_RE_MOSI GPIOB /* PB5 */ |
| |
| #define | GPIO_SPI2_NSS GPIO12 /* PB12 */ |
| |
| #define | GPIO_SPI2_SCK GPIO13 /* PB13 */ |
| |
| #define | GPIO_SPI2_MISO GPIO14 /* PB14 */ |
| |
| #define | GPIO_SPI2_MOSI GPIO15 /* PB15 */ |
| |
| #define | GPIO_BANK_SPI2_NSS GPIOB /* PB12 */ |
| |
| #define | GPIO_BANK_SPI2_SCK GPIOB /* PB13 */ |
| |
| #define | GPIO_BANK_SPI2_MISO GPIOB /* PB14 */ |
| |
| #define | GPIO_BANK_SPI2_MOSI GPIOB /* PB15 */ |
| |
| #define | GPIO_SPI3_NSS GPIO15 /* PA15 */ |
| |
| #define | GPIO_SPI3_SCK GPIO3 /* PB3 */ |
| |
| #define | GPIO_SPI3_MISO GPIO4 /* PB4 */ |
| |
| #define | GPIO_SPI3_MOSI GPIO5 /* PB5 */ |
| |
| #define | GPIO_SPI3_RE_NSS GPIO4 /* PA4 */ |
| |
| #define | GPIO_SPI3_RE_SCK GPIO10 /* PC10 */ |
| |
| #define | GPIO_SPI3_RE_MISO GPIO11 /* PC11 */ |
| |
| #define | GPIO_SPI3_RE_MOSI GPIO12 /* PC12 */ |
| |
| #define | GPIO_BANK_SPI3_NSS GPIOA /* PA15 */ |
| |
| #define | GPIO_BANK_SPI3_SCK GPIOB /* PB3 */ |
| |
| #define | GPIO_BANK_SPI3_MISO GPIOB /* PB4 */ |
| |
| #define | GPIO_BANK_SPI3_MOSI GPIOB /* PB5 */ |
| |
| #define | GPIO_BANK_SPI3_RE_NSS GPIOA /* PA4 */ |
| |
| #define | GPIO_BANK_SPI3_RE_SCK GPIOC /* PC10 */ |
| |
| #define | GPIO_BANK_SPI3_RE_MISO GPIOC /* PC11 */ |
| |
| #define | GPIO_BANK_SPI3_RE_MOSI GPIOC /* PC12 */ |
| |
| #define | GPIO_ETH_RX_DV_CRS_DV GPIO7 /* PA7 */ |
| |
| #define | GPIO_ETH_RXD0 GPIO4 /* PC4 */ |
| |
| #define | GPIO_ETH_RXD1 GPIO5 /* PC5 */ |
| |
| #define | GPIO_ETH_RXD2 GPIO0 /* PB0 */ |
| |
| #define | GPIO_ETH_RXD3 GPIO1 /* PB1 */ |
| |
| #define | GPIO_ETH_RE_RX_DV_CRS_DV GPIO8 /* PD8 */ |
| |
| #define | GPIO_ETH_RE_RXD0 GPIO9 /* PD9 */ |
| |
| #define | GPIO_ETH_RE_RXD1 GPIO10 /* PD10 */ |
| |
| #define | GPIO_ETH_RE_RXD2 GPIO11 /* PD11 */ |
| |
| #define | GPIO_ETH_RE_RXD3 GPIO12 /* PD12 */ |
| |
| #define | GPIO_BANK_ETH_RX_DV_CRS_DV GPIOA /* PA7 */ |
| |
| #define | GPIO_BANK_ETH_RXD0 GPIOC /* PC4 */ |
| |
| #define | GPIO_BANK_ETH_RXD1 GPIOC /* PC5 */ |
| |
| #define | GPIO_BANK_ETH_RXD2 GPIOB /* PB0 */ |
| |
| #define | GPIO_BANK_ETH_RXD3 GPIOB /* PB1 */ |
| |
| #define | GPIO_BANK_ETH_RE_RX_DV_CRS_DV GPIOD /* PD8 */ |
| |
| #define | GPIO_BANK_ETH_RE_RXD0 GPIOD /* PD9 */ |
| |
| #define | GPIO_BANK_ETH_RE_RXD1 GPIOD /* PD10 */ |
| |
| #define | GPIO_BANK_ETH_RE_RXD2 GPIOD /* PD11 */ |
| |
| #define | GPIO_BANK_ETH_RE_RXD3 GPIOD /* PD12 */ |
| |
| #define | GPIO_CRL(port) MMIO32((port) + 0x00) |
| |
| #define | GPIOA_CRL GPIO_CRL(GPIOA) |
| |
| #define | GPIOB_CRL GPIO_CRL(GPIOB) |
| |
| #define | GPIOC_CRL GPIO_CRL(GPIOC) |
| |
| #define | GPIOD_CRL GPIO_CRL(GPIOD) |
| |
| #define | GPIOE_CRL GPIO_CRL(GPIOE) |
| |
| #define | GPIOF_CRL GPIO_CRL(GPIOF) |
| |
| #define | GPIOG_CRL GPIO_CRL(GPIOG) |
| |
| #define | GPIO_CRH(port) MMIO32((port) + 0x04) |
| |
| #define | GPIOA_CRH GPIO_CRH(GPIOA) |
| |
| #define | GPIOB_CRH GPIO_CRH(GPIOB) |
| |
| #define | GPIOC_CRH GPIO_CRH(GPIOC) |
| |
| #define | GPIOD_CRH GPIO_CRH(GPIOD) |
| |
| #define | GPIOE_CRH GPIO_CRH(GPIOE) |
| |
| #define | GPIOF_CRH GPIO_CRH(GPIOF) |
| |
| #define | GPIOG_CRH GPIO_CRH(GPIOG) |
| |
| #define | GPIO_IDR(port) MMIO32((port) + 0x08) |
| |
| #define | GPIOA_IDR GPIO_IDR(GPIOA) |
| |
| #define | GPIOB_IDR GPIO_IDR(GPIOB) |
| |
| #define | GPIOC_IDR GPIO_IDR(GPIOC) |
| |
| #define | GPIOD_IDR GPIO_IDR(GPIOD) |
| |
| #define | GPIOE_IDR GPIO_IDR(GPIOE) |
| |
| #define | GPIOF_IDR GPIO_IDR(GPIOF) |
| |
| #define | GPIOG_IDR GPIO_IDR(GPIOG) |
| |
| #define | GPIO_ODR(port) MMIO32((port) + 0x0c) |
| |
| #define | GPIOA_ODR GPIO_ODR(GPIOA) |
| |
| #define | GPIOB_ODR GPIO_ODR(GPIOB) |
| |
| #define | GPIOC_ODR GPIO_ODR(GPIOC) |
| |
| #define | GPIOD_ODR GPIO_ODR(GPIOD) |
| |
| #define | GPIOE_ODR GPIO_ODR(GPIOE) |
| |
| #define | GPIOF_ODR GPIO_ODR(GPIOF) |
| |
| #define | GPIOG_ODR GPIO_ODR(GPIOG) |
| |
| #define | GPIO_BSRR(port) MMIO32((port) + 0x10) |
| |
| #define | GPIOA_BSRR GPIO_BSRR(GPIOA) |
| |
| #define | GPIOB_BSRR GPIO_BSRR(GPIOB) |
| |
| #define | GPIOC_BSRR GPIO_BSRR(GPIOC) |
| |
| #define | GPIOD_BSRR GPIO_BSRR(GPIOD) |
| |
| #define | GPIOE_BSRR GPIO_BSRR(GPIOE) |
| |
| #define | GPIOF_BSRR GPIO_BSRR(GPIOF) |
| |
| #define | GPIOG_BSRR GPIO_BSRR(GPIOG) |
| |
| #define | GPIO_BRR(port) MMIO16((port) + 0x14) |
| |
| #define | GPIOA_BRR GPIO_BRR(GPIOA) |
| |
| #define | GPIOB_BRR GPIO_BRR(GPIOB) |
| |
| #define | GPIOC_BRR GPIO_BRR(GPIOC) |
| |
| #define | GPIOD_BRR GPIO_BRR(GPIOD) |
| |
| #define | GPIOE_BRR GPIO_BRR(GPIOE) |
| |
| #define | GPIOF_BRR GPIO_BRR(GPIOF) |
| |
| #define | GPIOG_BRR GPIO_BRR(GPIOG) |
| |
| #define | GPIO_LCKR(port) MMIO32((port) + 0x18) |
| |
| #define | GPIOA_LCKR GPIO_LCKR(GPIOA) |
| |
| #define | GPIOB_LCKR GPIO_LCKR(GPIOB) |
| |
| #define | GPIOC_LCKR GPIO_LCKR(GPIOC) |
| |
| #define | GPIOD_LCKR GPIO_LCKR(GPIOD) |
| |
| #define | GPIOE_LCKR GPIO_LCKR(GPIOE) |
| |
| #define | GPIOF_LCKR GPIO_LCKR(GPIOF) |
| |
| #define | GPIOG_LCKR GPIO_LCKR(GPIOG) |
| |
| #define | GPIO_CNF_INPUT_ANALOG 0x00 |
| | Analog Input. More...
|
| |
| #define | GPIO_CNF_INPUT_FLOAT 0x01 /* Default */ |
| | Digital Input Floating. More...
|
| |
| #define | GPIO_CNF_INPUT_PULL_UPDOWN 0x02 |
| | Digital Input Pull Up and Down. More...
|
| |
| #define | GPIO_CNF_OUTPUT_PUSHPULL 0x00 |
| | Digital Output Pushpull. More...
|
| |
| #define | GPIO_CNF_OUTPUT_OPENDRAIN 0x01 |
| | Digital Output Open Drain. More...
|
| |
| #define | GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02 |
| | Alternate Function Output Pushpull. More...
|
| |
| #define | GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03 |
| | Alternate Function Output Open Drain. More...
|
| |
| #define | GPIO_MODE_INPUT 0x00 /* Default */ |
| |
| #define | GPIO_MODE_OUTPUT_10_MHZ 0x01 |
| |
| #define | GPIO_MODE_OUTPUT_2_MHZ 0x02 |
| |
| #define | GPIO_MODE_OUTPUT_50_MHZ 0x03 |
| |
| #define | AFIO_EVCR MMIO32(AFIO_BASE + 0x00) |
| |
| #define | AFIO_MAPR MMIO32(AFIO_BASE + 0x04) |
| |
| #define | AFIO_EXTICR(i) MMIO32(AFIO_BASE + 0x08 + (i)*4) |
| |
| #define | AFIO_EXTICR1 AFIO_EXTICR(0) |
| |
| #define | AFIO_EXTICR2 AFIO_EXTICR(1) |
| |
| #define | AFIO_EXTICR3 AFIO_EXTICR(2) |
| |
| #define | AFIO_EXTICR4 AFIO_EXTICR(3) |
| |
| #define | AFIO_MAPR2 MMIO32(AFIO_BASE + 0x1C) |
| |
| #define | AFIO_EVCR_EVOE (1 << 7) |
| |
| #define | AFIO_EVCR_PORT_PA (0x0 << 4) |
| |
| #define | AFIO_EVCR_PORT_PB (0x1 << 4) |
| |
| #define | AFIO_EVCR_PORT_PC (0x2 << 4) |
| |
| #define | AFIO_EVCR_PORT_PD (0x3 << 4) |
| |
| #define | AFIO_EVCR_PORT_PE (0x4 << 4) |
| |
| #define | AFIO_EVCR_PIN_Px0 (0x0 << 0) |
| |
| #define | AFIO_EVCR_PIN_Px1 (0x1 << 0) |
| |
| #define | AFIO_EVCR_PIN_Px2 (0x2 << 0) |
| |
| #define | AFIO_EVCR_PIN_Px3 (0x3 << 0) |
| |
| #define | AFIO_EVCR_PIN_Px4 (0x4 << 0) |
| |
| #define | AFIO_EVCR_PIN_Px5 (0x5 << 0) |
| |
| #define | AFIO_EVCR_PIN_Px6 (0x6 << 0) |
| |
| #define | AFIO_EVCR_PIN_Px7 (0x7 << 0) |
| |
| #define | AFIO_EVCR_PIN_Px8 (0x8 << 0) |
| |
| #define | AFIO_EVCR_PIN_Px9 (0x9 << 0) |
| |
| #define | AFIO_EVCR_PIN_Px10 (0xA << 0) |
| |
| #define | AFIO_EVCR_PIN_Px11 (0xB << 0) |
| |
| #define | AFIO_EVCR_PIN_Px12 (0xC << 0) |
| |
| #define | AFIO_EVCR_PIN_Px13 (0xD << 0) |
| |
| #define | AFIO_EVCR_PIN_Px14 (0xE << 0) |
| |
| #define | AFIO_EVCR_PIN_Px15 (0xF << 0) |
| |
| #define | AFIO_MAPR_PTP_PPS_REMAP (1 << 30) |
| | Ethernet PTP PPS remapping (only connectivity line devices) More...
|
| |
| #define | AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29) |
| | TIM2 internal trigger 1 remapping (only connectivity line devices) More...
|
| |
| #define | AFIO_MAPR_SPI3_REMAP (1 << 28) |
| | SPI3/I2S3 remapping (only connectivity line devices) More...
|
| |
| #define | AFIO_MAPR_MII_RMII_SEL (1 << 23) |
| | MII or RMII selection (only connectivity line devices) More...
|
| |
| #define | AFIO_MAPR_CAN2_REMAP (1 << 22) |
| | CAN2 I/O remapping (only connectivity line devices) More...
|
| |
| #define | AFIO_MAPR_ETH_REMAP (1 << 21) |
| | Ethernet MAC I/O remapping (only connectivity line devices) More...
|
| |
| #define | AFIO_MAPR_SWJ_MASK (0x7 << 24) |
| |
| #define | AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24) |
| | Full Serial Wire JTAG capability. More...
|
| |
| #define | AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24) |
| | Full Serial Wire JTAG capability without JNTRST. More...
|
| |
| #define | AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24) |
| | JTAG-DP disabled with SW-DP enabled. More...
|
| |
| #define | AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24) |
| | JTAG-DP disabled and SW-DP disabled. More...
|
| |
| #define | AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20) |
| | ADC2 external trigger regulator conversion remapping (only low-, medium-, high- and XL-density devices) More...
|
| |
| #define | AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19) |
| | ADC2 external trigger injected conversion remapping (only low-, medium-, high- and XL-density devices) More...
|
| |
| #define | AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18) |
| | ADC1 external trigger regulator conversion remapping (only low-, medium-, high- and XL-density devices) More...
|
| |
| #define | AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17) |
| | ADC1 external trigger injected conversion remapping (only low-, medium-, high- and XL-density devices) More...
|
| |
| #define | AFIO_MAPR_TIM5CH4_IREMAP (1 << 16) |
| | TIM5 channel 4 internal remap. More...
|
| |
| #define | AFIO_MAPR_PD01_REMAP (1 << 15) |
| | Port D0/Port D1 mapping on OSC_IN/OSC_OUT. More...
|
| |
| #define | AFIO_MAPR_TIM4_REMAP (1 << 12) |
| | TIM4 remapping. More...
|
| |
| #define | AFIO_MAPR_USART2_REMAP (1 << 3) |
| | USART2 remapping. More...
|
| |
| #define | AFIO_MAPR_USART1_REMAP (1 << 2) |
| | USART1 remapping. More...
|
| |
| #define | AFIO_MAPR_I2C1_REMAP (1 << 1) |
| | I2C1 remapping. More...
|
| |
| #define | AFIO_MAPR_SPI1_REMAP (1 << 0) |
| | SPI1 remapping. More...
|
| |
| #define | AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13) |
| |
| #define | AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not 36pin pkg */ |
| |
| #define | AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13) |
| |
| #define | AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10) |
| |
| #define | AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10) |
| |
| #define | AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10) |
| |
| #define | AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8) |
| |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8) |
| |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8) |
| |
| #define | AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8) |
| |
| #define | AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6) |
| |
| #define | AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6) |
| |
| #define | AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6) |
| |
| #define | AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4) |
| |
| #define | AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4) |
| |
| #define | AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4) |
| |
| #define | AFIO_MAPR2_MISC_REMAP (1 << 13) |
| | various remaps, dma/dac/timer triggers (HD only) More...
|
| |
| #define | AFIO_MAPR2_TIM12_REMAP (1 << 12) |
| | TIM12_CH1 and TIM12_CH2 remapping (HD only) More...
|
| |
| #define | AFIO_MAPR2_TIM76_DAC_DMA_REMAPE (1 << 11) |
| | TIM76_DAC_DMA remap to DMA1/DMA2. More...
|
| |
| #define | AFIO_MAPR2_FSMC_NADV_DISCONNECT (1 << 10) |
| | The NADV is disconnected from its allocated pin. More...
|
| |
| #define | AFIO_MAPR2_TIM14_REMAP (1 << 9) |
| | TIM14 CH1 remapping (Clear: PA7 vs Set: PF9. More...
|
| |
| #define | AFIO_MAPR2_TIM13_REMAP (1 << 8) |
| | TIM13 CH1 remapping (Clear: PA6 vs Set: PF8. More...
|
| |
| #define | AFIO_MAPR2_TIM11_REMAP (1 << 7) |
| | TIM11 CH1 remapping (Clear: PB7 vs Set: PF7. More...
|
| |
| #define | AFIO_MAPR2_TIM10_REMAP (1 << 6) |
| | TIM10 CH1 remapping (Clear: PB8 vs Set: PF6. More...
|
| |
| #define | AFIO_MAPR2_TIM9_REMAP (1 << 5) |
| | TIM9 Ch1/2 remapping (Clear: PA2,PA3 vs Set: PE5,PE6. More...
|
| |
| #define | AFIO_MAPR2_TIM1_DMA_REMAP (1 << 4) |
| | TIM1_DMA channel remapping Clear: CH1->DMA1-ch2, CH2->DM1-ch3 Set: CH1->DMA1-ch6, CH2->DMA1-ch6. More...
|
| |
| #define | AFIO_MAPR2_CEC_REMAP (1 << 3) |
| | CEC remapping (Clear: PB8 vs Set: PB10) More...
|
| |
| #define | AFIO_MAPR2_TIM17_REMAP (1 << 2) |
| | TIM17 remapping (Clear: PB9 vs Set: PB7) More...
|
| |
| #define | AFIO_MAPR2_TIM16_REMAP (1 << 1) |
| | TIM16 remapping (Clear: PB8 vs Set: PA6) More...
|
| |
| #define | AFIO_MAPR2_TIM15_REMAP (1 << 0) |
| | TIM15 remapping (Clear: PA2, PA3 vs Set: PB14, PB15) More...
|
| |
| #define | AFIO_EXTICR_FIELDSIZE 4 |
| | EXTICR port selection bits
More...
|
| |
| #define | AFIO_EXTI0 0 |
| |
| #define | AFIO_EXTI1 1 |
| |
| #define | AFIO_EXTI2 2 |
| |
| #define | AFIO_EXTI3 3 |
| |
| #define | AFIO_EXTI4 4 |
| |
| #define | AFIO_EXTI5 5 |
| |
| #define | AFIO_EXTI6 6 |
| |
| #define | AFIO_EXTI7 7 |
| |
| #define | AFIO_EXTI8 8 |
| |
| #define | AFIO_EXTI9 9 |
| |
| #define | AFIO_EXTI10 10 |
| |
| #define | AFIO_EXTI11 11 |
| |
| #define | AFIO_EXTI12 12 |
| |
| #define | AFIO_EXTI13 13 |
| |
| #define | AFIO_EXTI14 14 |
| |
| #define | AFIO_EXTI15 15 |
| |
