CoreSight Lock Status Registers and Lock Access Registers are documented for the DWT, ITM, FPB and TPIU peripherals.
More...
CoreSight Lock Status Registers and Lock Access Registers are documented for the DWT, ITM, FPB and TPIU peripherals.
◆ CORESIGHT_LAR_KEY
#define CORESIGHT_LAR_KEY 0xC5ACCE55 |
CoreSight Lock Access key, common for all.
Definition at line 99 of file cm3/memorymap.h.
◆ CORESIGHT_LAR_OFFSET
#define CORESIGHT_LAR_OFFSET 0xfb0 |
◆ CORESIGHT_LSR_OFFSET
#define CORESIGHT_LSR_OFFSET 0xfb4 |
◆ CORESIGHT_LSR_SLI
#define CORESIGHT_LSR_SLI (1<<0) |
CoreSight Lock Status Register lock availability bit.
Definition at line 97 of file cm3/memorymap.h.
◆ CORESIGHT_LSR_SLK
#define CORESIGHT_LSR_SLK (1<<1) |
CoreSight Lock Status Register lock status bit.
Definition at line 95 of file cm3/memorymap.h.