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#define | DAC_CR(dac) MMIO32((dac) + 0x00) |
| DAC control register (DAC_CR) More...
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#define | DAC_SWTRIGR(dac) MMIO32((dac) + 0x04) |
| DAC software trigger register (DAC_SWTRIGR) More...
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#define | DAC_DHR12R1(dac) MMIO32((dac) + 0x08) |
| DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) More...
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#define | DAC_DHR12L1(dac) MMIO32((dac) + 0x0C) |
| DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) More...
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#define | DAC_DHR8R1(dac) MMIO32((dac) + 0x10) |
| DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) More...
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#define | DAC_DHR12R2(dac) MMIO32((dac) + 0x14) |
| DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) More...
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#define | DAC_DHR12L2(dac) MMIO32((dac) + 0x18) |
| DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) More...
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#define | DAC_DHR8R2(dac) MMIO32((dac) + 0x1C) |
| DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) More...
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#define | DAC_DHR12RD(dac) MMIO32((dac) + 0x20) |
| Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) More...
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#define | DAC_DHR12LD(dac) MMIO32((dac) + 0x24) |
| DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) More...
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#define | DAC_DHR8RD(dac) MMIO32((dac) + 0x28) |
| DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) More...
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#define | DAC_DOR1(dac) MMIO32((dac) + 0x2C) |
| DAC channel1 data output register (DAC_DOR1) More...
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#define | DAC_DOR2(dac) MMIO32((dac) + 0x30) |
| DAC channel2 data output register (DAC_DOR2) More...
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#define | DAC_SR(dac) MMIO32((dac) + 0x34) |
| DAC status register. More...
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