TIM5_OR Timer 5 Option Register Internal Trigger 4 Remap

Only available in F2 and F4 series. More...

Collaboration diagram for TIM5_OR Timer 5 Option Register Internal Trigger 4 Remap:

Macros
#define	TIM5_OR_TI4_RMP_GPIO   (0x0 << 6)
	Internal Trigger 4 remapped to GPIO (see reference manual) More...
#define	TIM5_OR_TI4_RMP_LSI   (0x1 << 6)
	Internal Trigger 4 remapped to LSI internal clock. More...
#define	TIM5_OR_TI4_RMP_LSE   (0x2 << 6)
	Internal Trigger 4 remapped to LSE internal clock. More...
#define	TIM5_OR_TI4_RMP_RTC   (0x3 << 6)
	Internal Trigger 4 remapped to RTC output event. More...

Detailed Description

Only available in F2 and F4 series.

Macro Definition Documentation

TIM5_OR_TI4_RMP_GPIO

#define TIM5_OR_TI4_RMP_GPIO   (0x0 << 6)

Internal Trigger 4 remapped to GPIO (see reference manual)

Definition at line 76 of file timer_common_f24.h.

TIM5_OR_TI4_RMP_LSE

#define TIM5_OR_TI4_RMP_LSE   (0x2 << 6)

Internal Trigger 4 remapped to LSE internal clock.

Definition at line 80 of file timer_common_f24.h.

TIM5_OR_TI4_RMP_LSI

#define TIM5_OR_TI4_RMP_LSI   (0x1 << 6)

Internal Trigger 4 remapped to LSI internal clock.

Definition at line 78 of file timer_common_f24.h.

TIM5_OR_TI4_RMP_RTC

#define TIM5_OR_TI4_RMP_RTC   (0x3 << 6)

Internal Trigger 4 remapped to RTC output event.

Definition at line 82 of file timer_common_f24.h.