libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
Cortex-M System Control Space

The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for configuration, status reporting and control. More...

Collaboration diagram for Cortex-M System Control Space:

Modules

 SCS Registers
 

Macros

#define SCS_DHCSR_DBGKEY   0xA05F0000
 
#define SCS_DHCSR_C_DEBUGEN   0x00000001
 
#define SCS_DHCSR_C_HALT   0x00000002
 
#define SCS_DHCSR_C_STEP   0x00000004
 
#define SCS_DHCSR_C_MASKINTS   0x00000008
 
#define SCS_DHCSR_C_SNAPSTALL   0x00000020
 
#define SCS_DHCSR_S_REGRDY   0x00010000
 
#define SCS_DHCSR_S_HALT   0x00020000
 
#define SCS_DHCSR_S_SLEEP   0x00040000
 
#define SCS_DHCSR_S_LOCKUP   0x00080000
 
#define SCS_DHCSR_S_RETIRE_ST   0x01000000
 
#define SCS_DHCSR_S_RESET_ST   0x02000000
 
#define SCS_DCRSR_REGSEL_MASK   0x0000001F
 
#define SCS_DCRSR_REGSEL_XPSR   0x00000010
 
#define SCS_DCRSR_REGSEL_MSP   0x00000011
 
#define SCS_DCRSR_REGSEL_PSP   0x00000012
 
#define SCS_DEMCR_TRCENA   (1 << 24)
 
#define SCS_DEMCR_MON_REQ   (1 << 19)
 
#define SCS_DEMCR_MON_STEP   (1 << 18)
 
#define SCS_DEMCR_VC_MON_PEND   (1 << 17)
 
#define SCS_DEMCR_VC_MON_EN   (1 << 16)
 
#define SCS_DEMCR_VC_HARDERR   (1 << 10)
 
#define SCS_DEMCR_VC_INTERR   (1 << 9)
 
#define SCS_DEMCR_VC_BUSERR   (1 << 8)
 
#define SCS_DEMCR_VC_STATERR   (1 << 7)
 
#define SCS_DEMCR_VC_CHKERR   (1 << 6)
 
#define SCS_DEMCR_VC_NOCPERR   (1 << 5)
 
#define SCS_DEMCR_VC_MMERR   (1 << 4)
 
#define SCS_DEMCR_VC_CORERESET   (1 << 0)
 
#define SCS_DWT_LSR   MMIO32(SCS_DWT_BASE + 0xFB4)
 
#define SCS_DWT_LAR   MMIO32(SCS_DWT_BASE + 0xFB0)
 

Detailed Description

The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for configuration, status reporting and control.

The SCS registers divide into the following groups:

Most portions of the SCS are covered by their own header files, eg systick.h, dwt.h, scb.h, itm.h, fpb.h

Macro Definition Documentation

◆ SCS_DCRSR_REGSEL_MASK

#define SCS_DCRSR_REGSEL_MASK   0x0000001F

Definition at line 124 of file scs.h.

◆ SCS_DCRSR_REGSEL_MSP

#define SCS_DCRSR_REGSEL_MSP   0x00000011

Definition at line 126 of file scs.h.

◆ SCS_DCRSR_REGSEL_PSP

#define SCS_DCRSR_REGSEL_PSP   0x00000012

Definition at line 127 of file scs.h.

◆ SCS_DCRSR_REGSEL_XPSR

#define SCS_DCRSR_REGSEL_XPSR   0x00000010

Definition at line 125 of file scs.h.

◆ SCS_DEMCR_MON_REQ

#define SCS_DEMCR_MON_REQ   (1 << 19)

Definition at line 133 of file scs.h.

◆ SCS_DEMCR_MON_STEP

#define SCS_DEMCR_MON_STEP   (1 << 18)

Definition at line 134 of file scs.h.

◆ SCS_DEMCR_TRCENA

#define SCS_DEMCR_TRCENA   (1 << 24)

Definition at line 131 of file scs.h.

◆ SCS_DEMCR_VC_BUSERR

#define SCS_DEMCR_VC_BUSERR   (1 << 8)

Definition at line 140 of file scs.h.

◆ SCS_DEMCR_VC_CHKERR

#define SCS_DEMCR_VC_CHKERR   (1 << 6)

Definition at line 142 of file scs.h.

◆ SCS_DEMCR_VC_CORERESET

#define SCS_DEMCR_VC_CORERESET   (1 << 0)

Definition at line 146 of file scs.h.

◆ SCS_DEMCR_VC_HARDERR

#define SCS_DEMCR_VC_HARDERR   (1 << 10)

Definition at line 138 of file scs.h.

◆ SCS_DEMCR_VC_INTERR

#define SCS_DEMCR_VC_INTERR   (1 << 9)

Definition at line 139 of file scs.h.

◆ SCS_DEMCR_VC_MMERR

#define SCS_DEMCR_VC_MMERR   (1 << 4)

Definition at line 144 of file scs.h.

◆ SCS_DEMCR_VC_MON_EN

#define SCS_DEMCR_VC_MON_EN   (1 << 16)

Definition at line 136 of file scs.h.

◆ SCS_DEMCR_VC_MON_PEND

#define SCS_DEMCR_VC_MON_PEND   (1 << 17)

Definition at line 135 of file scs.h.

◆ SCS_DEMCR_VC_NOCPERR

#define SCS_DEMCR_VC_NOCPERR   (1 << 5)

Definition at line 143 of file scs.h.

◆ SCS_DEMCR_VC_STATERR

#define SCS_DEMCR_VC_STATERR   (1 << 7)

Definition at line 141 of file scs.h.

◆ SCS_DHCSR_C_DEBUGEN

#define SCS_DHCSR_C_DEBUGEN   0x00000001

Definition at line 111 of file scs.h.

◆ SCS_DHCSR_C_HALT

#define SCS_DHCSR_C_HALT   0x00000002

Definition at line 112 of file scs.h.

◆ SCS_DHCSR_C_MASKINTS

#define SCS_DHCSR_C_MASKINTS   0x00000008

Definition at line 114 of file scs.h.

◆ SCS_DHCSR_C_SNAPSTALL

#define SCS_DHCSR_C_SNAPSTALL   0x00000020

Definition at line 115 of file scs.h.

◆ SCS_DHCSR_C_STEP

#define SCS_DHCSR_C_STEP   0x00000004

Definition at line 113 of file scs.h.

◆ SCS_DHCSR_DBGKEY

#define SCS_DHCSR_DBGKEY   0xA05F0000

Definition at line 110 of file scs.h.

◆ SCS_DHCSR_S_HALT

#define SCS_DHCSR_S_HALT   0x00020000

Definition at line 117 of file scs.h.

◆ SCS_DHCSR_S_LOCKUP

#define SCS_DHCSR_S_LOCKUP   0x00080000

Definition at line 119 of file scs.h.

◆ SCS_DHCSR_S_REGRDY

#define SCS_DHCSR_S_REGRDY   0x00010000

Definition at line 116 of file scs.h.

◆ SCS_DHCSR_S_RESET_ST

#define SCS_DHCSR_S_RESET_ST   0x02000000

Definition at line 121 of file scs.h.

◆ SCS_DHCSR_S_RETIRE_ST

#define SCS_DHCSR_S_RETIRE_ST   0x01000000

Definition at line 120 of file scs.h.

◆ SCS_DHCSR_S_SLEEP

#define SCS_DHCSR_S_SLEEP   0x00040000

Definition at line 118 of file scs.h.

◆ SCS_DWT_LAR

#define SCS_DWT_LAR   MMIO32(SCS_DWT_BASE + 0xFB0)

Definition at line 151 of file scs.h.

◆ SCS_DWT_LSR

#define SCS_DWT_LSR   MMIO32(SCS_DWT_BASE + 0xFB4)

Definition at line 149 of file scs.h.