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libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
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Modules | |
| Under-drive ready flag | |
Macros | |
| #define | PWR_CSR1_UDRDY_LSB 18 |
| #define | PWR_CSR1_UDRDY_MASK (0x3 << PWR_CSR1_UDRDY_LSB) |
| #define | PWR_CSR1_ODSWRDY (1 << 17) |
| ODSWRDY: Over-drive mode switching ready. More... | |
| #define | PWR_CSR1_ODRDY (1 << 16) |
| ODRDY: Over-drive mode ready. More... | |
| #define | PWR_CSR1_VOSRDY (1 << 14) |
| VOSRDY: Regulator voltage scaling output selection ready bit. More... | |
| #define | PWR_CSR1_BRE (1 << 9) |
| BRE: Backup regulator enable. More... | |
| #define | PWR_CSR1_EIWUP (1 << 8) |
| EIWUP: Enable internal wakeup. More... | |
| #define | PWR_CSR1_BRR (1 << 3) |
| BRR: Backup regulator ready. More... | |
| #define | PWR_CSR1_PVDO (1 << 2) |
| PVDO: PVD output. More... | |
| #define | PWR_CSR1_SBF (1 << 1) |
| SBF: Standby flag. More... | |
| #define | PWR_CSR1_WUIF (1 << 0) |
| WUIF: Wakeup internal flag. More... | |
| #define PWR_CSR1_BRE (1 << 9) |
| #define PWR_CSR1_EIWUP (1 << 8) |
| #define PWR_CSR1_ODRDY (1 << 16) |
| #define PWR_CSR1_ODSWRDY (1 << 17) |
| #define PWR_CSR1_UDRDY_MASK (0x3 << PWR_CSR1_UDRDY_LSB) |
| #define PWR_CSR1_VOSRDY (1 << 14) |