PWR Defines

Defined Constants and Types for the STM32H7xx Power Control More...

Collaboration diagram for PWR Defines:

Modules
	PWR Registers
	SMPS step-down converter voltage output level selection
	This setting is used when both the LDO and SMPS step-down converter are enabled with SMPSEN and LDOEN enabled or when SMPSEXTHP is enabled.
	PWR Peripheral API

Macros
#define	PWR_CR1_SVOS_SHIFT   14
	VOS[15:14]: Regulator voltage scaling output selection. More...
#define	PWR_CR1_SVOS_MASK   (0x3)
#define	PWR_CR1_SVOS_SCALE_3   (0x3)
#define	PWR_CR1_SVOS_SCALE_4   (0x2)
#define	PWR_CR1_SVOS_SCALE_5   (0x1)
#define	PWR_CR1_SRDRAMSO   BIT27
	SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode. More...
#define	PWR_CR1_HSITFSO   BIT26
	high-speed interfaces USB and FDCAN memory shut-off in DStop/DStop2 mode More...
#define	PWR_CR1_GFXSO   BIT25
	GFXMMU and JPEG memory shut-off in DStop/DStop2 mode. More...
#define	PWR_CR1_ITCMSO   BIT24
	instruction TCM and ETM memory shut-off in DStop/DStop2 mode More...
#define	PWR_CR1_AHBRAM2SO   BIT23
	AHB SRAM2 shut-off in DStop/DStop2 mode. More...
#define	PWR_CR1_AHBRAM1SO   BIT22
	AHB SRAM1 shut-off in DStop/DStop2 mode. More...
#define	PWR_CR1_AXIRAM3SO   BIT21
	AXI SRAM3 shut-off in DStop/DStop2 mode. More...
#define	PWR_CR1_AXIRAM2SO   BIT20
	AXI SRAM2 shut-off in DStop/DStop2 mode. More...
#define	PWR_CR1_AXIRAM1SO   BIT19
	AXI SRAM1 shut-off in DStop/DStop2 mode. More...
#define	PWR_CR1_ALS_SHIFT   17
	voltage threshold detected by the AVD. More...
#define	PWR_CR1_ALS_MASK   0x3
#define	PWR_CR1_ALS_1P7V   0x0
#define	PWR_CR1_ALS_2P1V   0x1
#define	PWR_CR1_ALS_2P5V   0x2
#define	PWR_CR1_ALS_2P8V   0x3
#define	PWR_CR1_AVDEN   BIT16
	peripheral voltage monitor on V DDA enable More...
#define	PWR_CR1_AVD_READY   BIT13
	analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit). More...
#define	PWR_CR1_BOOSTE   BIT12
	analog switch VBoost control This bit enables the booster to guarantee the analog switch AC performance when the V DD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The V DD supply voltage can be monitored through the PVD and the PLS bits. More...
#define	PWR_CR1_DBP   BIT8
	DBP[8]: Disable backup domain write protection. More...
#define	PWR_CSR1_MMCVDO   BIT17
	CSR1 Register Bits. More...
#define	PWR_CSR1_AVDO   BIT16
#define	PWR_CSR1_ACTVOS_SHIFT   14
#define	PWR_CSR1_ACTVOSRDY   BIT13
#define	PWR_CSR1_PVDO   BIT4
#define	PWR_CR2_TEMPH   BIT23
	CR2 Register Bits. More...
#define	PWR_CR2_TEMPL   BIT22
	temperature level monitoring versus low threshold More...
#define	PWR_CR2_BRRDY   BIT16
	backup regulator ready More...
#define	PWR_CR2_MONEN   BIT4
	V BAT and temperature monitoring enable. More...
#define	PWR_CR2_BREN   BIT0
	backup regulator enable More...
#define	PWR_CR3_USB33RDY   BIT26
	CR3 Register Bits. More...
#define	PWR_CR3_USBREGEN   BIT25
#define	PWR_CR3_USB33DEN   BIT24
#define	PWR_CR3_SMPSEXTRDY   BIT16
	SMPS step-down converter external supply ready. More...
#define	PWR_CR3_VBRS   BIT9
	V BAT charging resistor selection More...
#define	PWR_CR3_VBE   BIT8
	V BAT charging enable. More...
#define	PWR_CR3_SMPSLEVEL_SHIFT   4
#define	PWR_CR3_SMPSLEVEL_MASK   0x3
#define	PWR_CR3_SMPSEXTHP   BIT3
	SMPS step-down converter external power delivery selection. More...
#define	PWR_CR3_SCUEN   BIT2
#define	PWR_CR3_SMPSEN   BIT2
#define	PWR_CR3_LDOEN   BIT1
#define	PWR_CR3_BYPASS   BIT0
#define	PWR_D3CR_VOSRDY   BIT13
	D3CR Register Bits. More...
#define	PWR_D3CR_VOS_SHIFT   14
#define	PWR_D3CR_VOS_MASK   (0x03)
#define	PWR_D3CR_VOS_SCALE_0   (0x0)
	VOS0 is implemented on STM32H72x/3x with simple VOS setting. More...
#define	PWR_D3CR_VOS_SCALE_3   (0x1)
#define	PWR_D3CR_VOS_SCALE_2   (0x2)
#define	PWR_D3CR_VOS_SCALE_1   (0x3)
#define	PWR_SRDCR_VOSRDY   BIT13
	SRDCR Register Bits. More...
#define	PWR_SRDCR_VOS_SHIFT   14
#define	PWR_SRDCR_VOS_MASK   (0x03)
#define	PWR_SRDCR_VOS_SCALE_3   (0x0)
#define	PWR_SRDCR_VOS_SCALE_2   (0x1)
#define	PWR_SRDCR_VOS_SCALE_1   (0x2)
#define	PWR_SRDCR_VOS_SCALE_0   (0x3)

Enumerations
enum	pwr_sys_mode {   PWR_SYS_SCU_LDO = 0 , PWR_SYS_SCU_BYPASS , PWR_SYS_LDO , PWR_SYS_SMPS_DIRECT ,   PWR_SYS_SMPS_LDO , PWR_SYS_EXT_SMPS_LDO , PWR_SYS_EXT_SMPS_LDO_BYP , PWR_SYS_BYPASS }
enum	pwr_svos_scale { PWR_SVOS_SCALE3 = PWR_CR1_SVOS_SCALE_3 << PWR_CR1_SVOS_SHIFT , PWR_SVOS_SCALE4 = PWR_CR1_SVOS_SCALE_4 << PWR_CR1_SVOS_SHIFT , PWR_SVOS_SCALE5 = PWR_CR1_SVOS_SCALE_5 << PWR_CR1_SVOS_SHIFT }
enum	pwr_vos_scale {   PWR_VOS_SCALE_UNDEFINED = 0 , PWR_VOS_SCALE_0 , PWR_VOS_SCALE_1 , PWR_VOS_SCALE_2 ,   PWR_VOS_SCALE_3 }

Detailed Description

Defined Constants and Types for the STM32H7xx Power Control

Version

1.0.0

LGPL License Terms libopencm3 License

Macro Definition Documentation

PWR_CR1_AHBRAM1SO

#define PWR_CR1_AHBRAM1SO   BIT22

AHB SRAM1 shut-off in DStop/DStop2 mode.

Definition at line 80 of file h7/pwr.h.

PWR_CR1_AHBRAM2SO

#define PWR_CR1_AHBRAM2SO   BIT23

AHB SRAM2 shut-off in DStop/DStop2 mode.

Definition at line 78 of file h7/pwr.h.

PWR_CR1_ALS_1P7V

#define PWR_CR1_ALS_1P7V   0x0

Definition at line 90 of file h7/pwr.h.

PWR_CR1_ALS_2P1V

#define PWR_CR1_ALS_2P1V   0x1

Definition at line 91 of file h7/pwr.h.

PWR_CR1_ALS_2P5V

#define PWR_CR1_ALS_2P5V   0x2

Definition at line 92 of file h7/pwr.h.

PWR_CR1_ALS_2P8V

#define PWR_CR1_ALS_2P8V   0x3

Definition at line 93 of file h7/pwr.h.

PWR_CR1_ALS_MASK

#define PWR_CR1_ALS_MASK   0x3

Definition at line 89 of file h7/pwr.h.

PWR_CR1_ALS_SHIFT

#define PWR_CR1_ALS_SHIFT   17

voltage threshold detected by the AVD.

Definition at line 88 of file h7/pwr.h.

PWR_CR1_AVD_READY

#define PWR_CR1_AVD_READY   BIT13

analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit).

It must be set by software when the expected V DDA analog supply level is available. The correct analog supply level is indicated by the AVDO bit (PWR_CSR1 register) after setting the AVDEN bit and selecting the supply level to be monitored (ALS bits).

Definition at line 102 of file h7/pwr.h.

PWR_CR1_AVDEN

#define PWR_CR1_AVDEN   BIT16

peripheral voltage monitor on V DDA enable

Definition at line 95 of file h7/pwr.h.

PWR_CR1_AXIRAM1SO

#define PWR_CR1_AXIRAM1SO   BIT19

AXI SRAM1 shut-off in DStop/DStop2 mode.

Definition at line 86 of file h7/pwr.h.

PWR_CR1_AXIRAM2SO

#define PWR_CR1_AXIRAM2SO   BIT20

AXI SRAM2 shut-off in DStop/DStop2 mode.

Definition at line 84 of file h7/pwr.h.

PWR_CR1_AXIRAM3SO

#define PWR_CR1_AXIRAM3SO   BIT21

AXI SRAM3 shut-off in DStop/DStop2 mode.

Definition at line 82 of file h7/pwr.h.

PWR_CR1_BOOSTE

#define PWR_CR1_BOOSTE   BIT12

analog switch VBoost control This bit enables the booster to guarantee the analog switch AC performance when the V DD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The V DD supply voltage can be monitored through the PVD and the PLS bits.

Definition at line 109 of file h7/pwr.h.

PWR_CR1_DBP

#define PWR_CR1_DBP   BIT8

DBP[8]: Disable backup domain write protection.

Definition at line 111 of file h7/pwr.h.

PWR_CR1_GFXSO

#define PWR_CR1_GFXSO   BIT25

GFXMMU and JPEG memory shut-off in DStop/DStop2 mode.

Definition at line 74 of file h7/pwr.h.

PWR_CR1_HSITFSO

#define PWR_CR1_HSITFSO   BIT26

high-speed interfaces USB and FDCAN memory shut-off in DStop/DStop2 mode

Definition at line 72 of file h7/pwr.h.

PWR_CR1_ITCMSO

#define PWR_CR1_ITCMSO   BIT24

instruction TCM and ETM memory shut-off in DStop/DStop2 mode

Definition at line 76 of file h7/pwr.h.

PWR_CR1_SRDRAMSO

#define PWR_CR1_SRDRAMSO   BIT27

SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode.

Definition at line 70 of file h7/pwr.h.

PWR_CR1_SVOS_MASK

#define PWR_CR1_SVOS_MASK   (0x3)

Definition at line 64 of file h7/pwr.h.

PWR_CR1_SVOS_SCALE_3

#define PWR_CR1_SVOS_SCALE_3   (0x3)

Definition at line 65 of file h7/pwr.h.

PWR_CR1_SVOS_SCALE_4

#define PWR_CR1_SVOS_SCALE_4   (0x2)

Definition at line 66 of file h7/pwr.h.

PWR_CR1_SVOS_SCALE_5

#define PWR_CR1_SVOS_SCALE_5   (0x1)

Definition at line 67 of file h7/pwr.h.

PWR_CR1_SVOS_SHIFT

#define PWR_CR1_SVOS_SHIFT   14

VOS[15:14]: Regulator voltage scaling output selection.

Definition at line 63 of file h7/pwr.h.

PWR_CR2_BREN

#define PWR_CR2_BREN   BIT0

backup regulator enable

Definition at line 130 of file h7/pwr.h.

PWR_CR2_BRRDY

#define PWR_CR2_BRRDY   BIT16

backup regulator ready

Definition at line 126 of file h7/pwr.h.

PWR_CR2_MONEN

#define PWR_CR2_MONEN   BIT4

V BAT and temperature monitoring enable.

Definition at line 128 of file h7/pwr.h.

PWR_CR2_TEMPH

#define PWR_CR2_TEMPH   BIT23

CR2 Register Bits.

temperature level monitoring versus high threshold

Definition at line 122 of file h7/pwr.h.

PWR_CR2_TEMPL

#define PWR_CR2_TEMPL   BIT22

temperature level monitoring versus low threshold

Definition at line 124 of file h7/pwr.h.

PWR_CR3_BYPASS

#define PWR_CR3_BYPASS   BIT0

Definition at line 162 of file h7/pwr.h.

PWR_CR3_LDOEN

#define PWR_CR3_LDOEN   BIT1

Definition at line 161 of file h7/pwr.h.

PWR_CR3_SCUEN

#define PWR_CR3_SCUEN   BIT2

Definition at line 158 of file h7/pwr.h.

PWR_CR3_SMPSEN

#define PWR_CR3_SMPSEN   BIT2

Definition at line 160 of file h7/pwr.h.

PWR_CR3_SMPSEXTHP

#define PWR_CR3_SMPSEXTHP   BIT3

SMPS step-down converter external power delivery selection.

Definition at line 157 of file h7/pwr.h.

PWR_CR3_SMPSEXTRDY

#define PWR_CR3_SMPSEXTRDY   BIT16

SMPS step-down converter external supply ready.

Definition at line 137 of file h7/pwr.h.

PWR_CR3_SMPSLEVEL_MASK

#define PWR_CR3_SMPSLEVEL_MASK   0x3

Definition at line 154 of file h7/pwr.h.

PWR_CR3_SMPSLEVEL_SHIFT

#define PWR_CR3_SMPSLEVEL_SHIFT   4

Definition at line 153 of file h7/pwr.h.

PWR_CR3_USB33DEN

#define PWR_CR3_USB33DEN   BIT24

Definition at line 135 of file h7/pwr.h.

PWR_CR3_USB33RDY

#define PWR_CR3_USB33RDY   BIT26

CR3 Register Bits.

Definition at line 133 of file h7/pwr.h.

PWR_CR3_USBREGEN

#define PWR_CR3_USBREGEN   BIT25

Definition at line 134 of file h7/pwr.h.

PWR_CR3_VBE

#define PWR_CR3_VBE   BIT8

V BAT charging enable.

Definition at line 141 of file h7/pwr.h.

PWR_CR3_VBRS

#define PWR_CR3_VBRS   BIT9

V BAT charging resistor selection

Definition at line 139 of file h7/pwr.h.

PWR_CSR1_ACTVOS_SHIFT

#define PWR_CSR1_ACTVOS_SHIFT   14

Definition at line 116 of file h7/pwr.h.

PWR_CSR1_ACTVOSRDY

#define PWR_CSR1_ACTVOSRDY   BIT13

Definition at line 117 of file h7/pwr.h.

PWR_CSR1_AVDO

#define PWR_CSR1_AVDO   BIT16

Definition at line 115 of file h7/pwr.h.

PWR_CSR1_MMCVDO

#define PWR_CSR1_MMCVDO   BIT17

CSR1 Register Bits.

Definition at line 114 of file h7/pwr.h.

PWR_CSR1_PVDO

#define PWR_CSR1_PVDO   BIT4

Definition at line 118 of file h7/pwr.h.

PWR_D3CR_VOS_MASK

#define PWR_D3CR_VOS_MASK   (0x03)

Definition at line 167 of file h7/pwr.h.

PWR_D3CR_VOS_SCALE_0

#define PWR_D3CR_VOS_SCALE_0   (0x0)

VOS0 is implemented on STM32H72x/3x with simple VOS setting.

STM32H742/43/45/47/50/53/55/57 SCALE0 this as SCALE1 + SYSCFG.ODEN

Definition at line 170 of file h7/pwr.h.

PWR_D3CR_VOS_SCALE_1

#define PWR_D3CR_VOS_SCALE_1   (0x3)

Definition at line 173 of file h7/pwr.h.

PWR_D3CR_VOS_SCALE_2

#define PWR_D3CR_VOS_SCALE_2   (0x2)

Definition at line 172 of file h7/pwr.h.

PWR_D3CR_VOS_SCALE_3

#define PWR_D3CR_VOS_SCALE_3   (0x1)

Definition at line 171 of file h7/pwr.h.

PWR_D3CR_VOS_SHIFT

#define PWR_D3CR_VOS_SHIFT   14

Definition at line 166 of file h7/pwr.h.

PWR_D3CR_VOSRDY

#define PWR_D3CR_VOSRDY   BIT13

D3CR Register Bits.

Definition at line 165 of file h7/pwr.h.

PWR_SRDCR_VOS_MASK

#define PWR_SRDCR_VOS_MASK   (0x03)

Definition at line 177 of file h7/pwr.h.

PWR_SRDCR_VOS_SCALE_0

#define PWR_SRDCR_VOS_SCALE_0   (0x3)

Definition at line 181 of file h7/pwr.h.

PWR_SRDCR_VOS_SCALE_1

#define PWR_SRDCR_VOS_SCALE_1   (0x2)

Definition at line 180 of file h7/pwr.h.

PWR_SRDCR_VOS_SCALE_2

#define PWR_SRDCR_VOS_SCALE_2   (0x1)

Definition at line 179 of file h7/pwr.h.

PWR_SRDCR_VOS_SCALE_3

#define PWR_SRDCR_VOS_SCALE_3   (0x0)

Definition at line 178 of file h7/pwr.h.

PWR_SRDCR_VOS_SHIFT

#define PWR_SRDCR_VOS_SHIFT   14

Definition at line 176 of file h7/pwr.h.

PWR_SRDCR_VOSRDY

#define PWR_SRDCR_VOSRDY   BIT13

SRDCR Register Bits.

Definition at line 175 of file h7/pwr.h.

Enumeration Type Documentation

pwr_svos_scale

enum pwr_svos_scale

Enumerator
PWR_SVOS_SCALE3
PWR_SVOS_SCALE4
PWR_SVOS_SCALE5

Definition at line 194 of file h7/pwr.h.

pwr_sys_mode

enum pwr_sys_mode

Enumerator
PWR_SYS_SCU_LDO	STM32H742/43/50/53 has special SCUEN handling, use for LDO.
PWR_SYS_SCU_BYPASS	STM32H742/43/50/53 has special SCUEN handling, use for bypass.
PWR_SYS_LDO	Devices with SMPS use this to run from LDO only.
PWR_SYS_SMPS_DIRECT	Disable LDO, apply SMPS direct to CPU using VOS.
PWR_SYS_SMPS_LDO	SMPS supplies internal LDO.
PWR_SYS_EXT_SMPS_LDO	SMPS supplies external power, and CPU through LDO.
PWR_SYS_EXT_SMPS_LDO_BYP	SMPS supplies external power, bypasses LDO (e.g. external LDO)
PWR_SYS_BYPASS	Disable all internal power supplies.

Definition at line 183 of file h7/pwr.h.

pwr_vos_scale

enum pwr_vos_scale

Enumerator
PWR_VOS_SCALE_UNDEFINED
PWR_VOS_SCALE_0
PWR_VOS_SCALE_1
PWR_VOS_SCALE_2
PWR_VOS_SCALE_3

Definition at line 200 of file h7/pwr.h.