DMA library for the multi channel controller found in F0/1/3 & L/G parts. More...

Collaboration diagram for DMA peripheral API:

Functions
void	dma_set_channel_request (uint32_t dma, uint8_t channel, uint8_t request)
	DMA Channel Set Request Selection. More...

void	dma_channel_reset (uint32_t dma, uint8_t channel)
	DMA Channel Reset. More...

void	dma_clear_interrupt_flags (uint32_t dma, uint8_t channel, uint32_t interrupts)
	DMA Channel Clear Interrupt Flag. More...

bool	dma_get_interrupt_flag (uint32_t dma, uint8_t channel, uint32_t interrupt)
	DMA Channel Read Interrupt Flag. More...

void	dma_enable_mem2mem_mode (uint32_t dma, uint8_t channel)
	DMA Channel Enable Memory to Memory Transfers. More...

void	dma_set_priority (uint32_t dma, uint8_t channel, uint32_t prio)
	DMA Channel Set Priority. More...

void	dma_set_memory_size (uint32_t dma, uint8_t channel, uint32_t mem_size)
	DMA Channel Set Memory Word Width. More...

void	dma_set_peripheral_size (uint32_t dma, uint8_t channel, uint32_t peripheral_size)
	DMA Channel Set Peripheral Word Width. More...

void	dma_enable_memory_increment_mode (uint32_t dma, uint8_t channel)
	DMA Channel Enable Memory Increment after Transfer. More...

void	dma_disable_memory_increment_mode (uint32_t dma, uint8_t channel)
	DMA Channel Disable Memory Increment after Transfer. More...

void	dma_enable_peripheral_increment_mode (uint32_t dma, uint8_t channel)
	DMA Channel Enable Peripheral Increment after Transfer. More...

void	dma_disable_peripheral_increment_mode (uint32_t dma, uint8_t channel)
	DMA Channel Disable Peripheral Increment after Transfer. More...

void	dma_enable_circular_mode (uint32_t dma, uint8_t channel)
	DMA Channel Enable Memory Circular Mode. More...

void	dma_set_read_from_peripheral (uint32_t dma, uint8_t channel)
	DMA Channel Enable Transfers from a Peripheral. More...

void	dma_set_read_from_memory (uint32_t dma, uint8_t channel)
	DMA Channel Enable Transfers from Memory. More...

void	dma_enable_transfer_error_interrupt (uint32_t dma, uint8_t channel)
	DMA Channel Enable Interrupt on Transfer Error. More...

void	dma_disable_transfer_error_interrupt (uint32_t dma, uint8_t channel)
	DMA Channel Disable Interrupt on Transfer Error. More...

void	dma_enable_half_transfer_interrupt (uint32_t dma, uint8_t channel)
	DMA Channel Enable Interrupt on Transfer Half Complete. More...

void	dma_disable_half_transfer_interrupt (uint32_t dma, uint8_t channel)
	DMA Channel Disable Interrupt on Transfer Half Complete. More...

void	dma_enable_transfer_complete_interrupt (uint32_t dma, uint8_t channel)
	DMA Channel Enable Interrupt on Transfer Complete. More...

void	dma_disable_transfer_complete_interrupt (uint32_t dma, uint8_t channel)
	DMA Channel Disable Interrupt on Transfer Complete. More...

void	dma_enable_channel (uint32_t dma, uint8_t channel)
	DMA Channel Enable. More...

void	dma_disable_channel (uint32_t dma, uint8_t channel)
	DMA Channel Disable. More...

void	dma_set_peripheral_address (uint32_t dma, uint8_t channel, uint32_t address)
	DMA Channel Set the Peripheral Address. More...

void	dma_set_memory_address (uint32_t dma, uint8_t channel, uint32_t address)
	DMA Channel Set the Base Memory Address. More...

uint16_t	dma_get_number_of_data (uint32_t dma, uint8_t channel)
	DMA Channel Get the Transfer Block Size. More...

void	dma_set_number_of_data (uint32_t dma, uint8_t channel, uint16_t number)
	DMA Channel Set the Transfer Block Size. More...

Detailed Description

DMA library for the multi channel controller found in F0/1/3 & L/G parts.

Author: © 2010 Thomas Otto tommi.nosp@m.@via.nosp@m.dmin..nosp@m.org

This library supports the DMA Control System in the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics.

Up to two DMA controllers are supported. 12 DMA channels are allocated 7 to the first DMA controller and 5 to the second. Each channel is connected to between 3 and 6 hardware peripheral DMA signals in a logical OR arrangement.

DMA transfers can be configured to occur between peripheral and memory in any combination including memory to memory. Circular mode transfers are also supported in transfers involving a peripheral. An arbiter is provided to resolve priority DMA requests. Transfers can be made with 8, 16 or 32 bit words.

LGPL License Terms libopencm3 License

Function Documentation

◆ dma_channel_reset()

void dma_channel_reset	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Reset.

The channel is disabled and configuration registers are cleared.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Definition at line 54 of file dma_common_l1f013.c.

References DMA_CCR, DMA_CMAR, DMA_CNDTR, DMA_CPAR, DMA_IFCR, and DMA_IFCR_CIF.

◆ dma_clear_interrupt_flags()

void dma_clear_interrupt_flags	(	uint32_t	dma,
		uint8_t	channel,
		uint32_t	interrupts
	)

DMA Channel Clear Interrupt Flag.

The interrupt flag for the channel is cleared. More than one interrupt for the same channel may be cleared by using the logical OR of the interrupt flags.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: DMA Channel Number
[in]	interrupts	unsigned int32. Logical OR of interrupt numbers: DMA Interrupt Flag Offsets within channel flag

Definition at line 80 of file dma_common_l1f013.c.

References DMA_FLAG_OFFSET, and DMA_IFCR.

◆ dma_disable_channel()

void dma_disable_channel	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Disable.

Note: The DMA channel registers retain their values when the channel is disabled.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Definition at line 376 of file dma_common_l1f013.c.

References DMA_CCR.

◆ dma_disable_half_transfer_interrupt()

void dma_disable_half_transfer_interrupt	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Disable Interrupt on Transfer Half Complete.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Definition at line 325 of file dma_common_l1f013.c.

References DMA_CCR.

◆ dma_disable_memory_increment_mode()

void dma_disable_memory_increment_mode	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Disable Memory Increment after Transfer.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Definition at line 201 of file dma_common_l1f013.c.

References DMA_CCR.

◆ dma_disable_peripheral_increment_mode()

void dma_disable_peripheral_increment_mode	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Disable Peripheral Increment after Transfer.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Definition at line 229 of file dma_common_l1f013.c.

References DMA_CCR.

◆ dma_disable_transfer_complete_interrupt()

void dma_disable_transfer_complete_interrupt	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Disable Interrupt on Transfer Complete.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Definition at line 349 of file dma_common_l1f013.c.

References DMA_CCR.

◆ dma_disable_transfer_error_interrupt()

void dma_disable_transfer_error_interrupt	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Disable Interrupt on Transfer Error.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Definition at line 301 of file dma_common_l1f013.c.

References DMA_CCR.

◆ dma_enable_channel()

void dma_enable_channel	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Enable.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Definition at line 361 of file dma_common_l1f013.c.

References DMA_CCR, and DMA_CCR_EN.

◆ dma_enable_circular_mode()

void dma_enable_circular_mode	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Enable Memory Circular Mode.

After the number of bytes/words to be transferred has been completed, the original transfer block size, memory and peripheral base addresses are reloaded and the process repeats.

Note: This cannot be used with memory to memory mode, which is explicitly disabled here.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Definition at line 248 of file dma_common_l1f013.c.

References DMA_CCR, and DMA_CCR_CIRC.

◆ dma_enable_half_transfer_interrupt()

void dma_enable_half_transfer_interrupt	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Enable Interrupt on Transfer Half Complete.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Definition at line 313 of file dma_common_l1f013.c.

References DMA_CCR, and DMA_CCR_HTIE.

◆ dma_enable_mem2mem_mode()

void dma_enable_mem2mem_mode	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Enable Memory to Memory Transfers.

Memory to memory transfers do not require a trigger to activate each transfer. Transfers begin immediately the channel has been enabled, and proceed without intervention.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Definition at line 117 of file dma_common_l1f013.c.

References DMA_CCR, and DMA_CCR_MEM2MEM.

◆ dma_enable_memory_increment_mode()

void dma_enable_memory_increment_mode	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Enable Memory Increment after Transfer.

Following each transfer the current memory address is incremented by 1, 2 or 4 depending on the data size set in dma_set_memory_size. The value held by the base memory address register is unchanged.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Definition at line 189 of file dma_common_l1f013.c.

References DMA_CCR, and DMA_CCR_MINC.

◆ dma_enable_peripheral_increment_mode()

void dma_enable_peripheral_increment_mode	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Enable Peripheral Increment after Transfer.

Following each transfer the current peripheral address is incremented by 1, 2 or 4 depending on the data size set in dma_set_peripheral_size. The value held by the base peripheral address register is unchanged.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Definition at line 217 of file dma_common_l1f013.c.

References DMA_CCR, and DMA_CCR_PINC.

◆ dma_enable_transfer_complete_interrupt()

void dma_enable_transfer_complete_interrupt	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Enable Interrupt on Transfer Complete.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Definition at line 337 of file dma_common_l1f013.c.

References DMA_CCR, and DMA_CCR_TCIE.

◆ dma_enable_transfer_error_interrupt()

void dma_enable_transfer_error_interrupt	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Enable Interrupt on Transfer Error.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Definition at line 289 of file dma_common_l1f013.c.

References DMA_CCR, and DMA_CCR_TEIE.

◆ dma_get_interrupt_flag()

bool dma_get_interrupt_flag	(	uint32_t	dma,
		uint8_t	channel,
		uint32_t	interrupt
	)

DMA Channel Read Interrupt Flag.

The interrupt flag for the channel is returned.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: DMA Channel Number
[in]	interrupt	unsigned int32. Interrupt number: DMA Interrupt Flag Offsets within channel flag

Returns: bool interrupt flag is set.

Definition at line 99 of file dma_common_l1f013.c.

References DMA_FLAG_OFFSET, and DMA_ISR.

◆ dma_get_number_of_data()

uint16_t dma_get_number_of_data	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Get the Transfer Block Size.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Returns: unsigned int16. Number of remaining data words to transfer (65535 maximum).

Definition at line 429 of file dma_common_l1f013.c.

References DMA_CNDTR.

◆ dma_set_channel_request()

void dma_set_channel_request	(	uint32_t	dma,
		uint8_t	channel,
		uint8_t	request
	)

DMA Channel Set Request Selection.

Set DMA request mapping selection for given channel. Refer to datasheet for channel request mapping tables.

Parameters

[in]	dma	DMA controller base address: DMA1 or DMA2
[in]	channel	Channel number: 1-7 for DMA1 or 1-5 for DMA2
[in]	request	DMA request mapping.

Definition at line 37 of file dma_common_csel.c.

References DMA_CSELR, DMA_CSELR_CxS_MASK, and DMA_CSELR_CxS_SHIFT.

◆ dma_set_memory_address()

void dma_set_memory_address	(	uint32_t	dma,
		uint8_t	channel,
		uint32_t	address
	)

DMA Channel Set the Base Memory Address.

Note: The DMA channel must be disabled before setting this address. This function has no effect if the channel is enabled.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
[in]	address	unsigned int32. Memory Initial Address.

Definition at line 413 of file dma_common_l1f013.c.

References DMA_CCR, DMA_CCR_EN, and DMA_CMAR.

◆ dma_set_memory_size()

void dma_set_memory_size	(	uint32_t	dma,
		uint8_t	channel,
		uint32_t	mem_size
	)

DMA Channel Set Memory Word Width.

Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for alignment information if the source and destination widths do not match.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
[in]	mem_size	unsigned int32. Memory word width DMA Channel Memory Word Width.

Definition at line 151 of file dma_common_l1f013.c.

References DMA_CCR, and DMA_CCR_MSIZE_MASK.

◆ dma_set_number_of_data()

void dma_set_number_of_data	(	uint32_t	dma,
		uint8_t	channel,
		uint16_t	number
	)

DMA Channel Set the Transfer Block Size.

Note: The DMA channel must be disabled before setting this count value. The count is not changed if the channel is enabled.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
[in]	number	unsigned int16. Number of data words to transfer (65535 maximum).

Definition at line 446 of file dma_common_l1f013.c.

References DMA_CNDTR.

◆ dma_set_peripheral_address()

void dma_set_peripheral_address	(	uint32_t	dma,
		uint8_t	channel,
		uint32_t	address
	)

DMA Channel Set the Peripheral Address.

Set the address of the peripheral register to or from which data is to be transferred. Refer to the documentation for the specific peripheral.

Note: The DMA channel must be disabled before setting this address. This function has no effect if the channel is enabled.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
[in]	address	unsigned int32. Peripheral Address.

Definition at line 395 of file dma_common_l1f013.c.

References DMA_CCR, DMA_CCR_EN, and DMA_CPAR.

◆ dma_set_peripheral_size()

void dma_set_peripheral_size	(	uint32_t	dma,
		uint8_t	channel,
		uint32_t	peripheral_size
	)

DMA Channel Set Peripheral Word Width.

Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for alignment information if the source and destination widths do not match, or if the peripheral does not support byte or half-word writes.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
[in]	peripheral_size	unsigned int32. Peripheral word width DMA Channel Peripheral Word Width.

Definition at line 171 of file dma_common_l1f013.c.

References DMA_CCR, and DMA_CCR_PSIZE_MASK.

◆ dma_set_priority()

void dma_set_priority	(	uint32_t	dma,
		uint8_t	channel,
		uint32_t	prio
	)

DMA Channel Set Priority.

Channel Priority has four levels: low to very high. This has precedence over the hardware priority.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
[in]	prio	unsigned int32. Priority level DMA Channel Priority Levels.

Definition at line 134 of file dma_common_l1f013.c.

References DMA_CCR, and DMA_CCR_PL_MASK.

◆ dma_set_read_from_memory()

void dma_set_read_from_memory	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Enable Transfers from Memory.

The data direction is set to read from memory.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Definition at line 277 of file dma_common_l1f013.c.

References DMA_CCR, and DMA_CCR_DIR.

◆ dma_set_read_from_peripheral()

void dma_set_read_from_peripheral	(	uint32_t	dma,
		uint8_t	channel
	)

DMA Channel Enable Transfers from a Peripheral.

The data direction is set to read from a peripheral.

Parameters

[in]	dma	unsigned int32. DMA controller base address: DMA1 or DMA2
[in]	channel	unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2

Definition at line 263 of file dma_common_l1f013.c.

References DMA_CCR.

Functions

Detailed Description

Function Documentation

◆ dma_channel_reset()

◆ dma_clear_interrupt_flags()

◆ dma_disable_channel()

◆ dma_disable_half_transfer_interrupt()

◆ dma_disable_memory_increment_mode()

◆ dma_disable_peripheral_increment_mode()

◆ dma_disable_transfer_complete_interrupt()

◆ dma_disable_transfer_error_interrupt()

◆ dma_enable_channel()

◆ dma_enable_circular_mode()

◆ dma_enable_half_transfer_interrupt()

◆ dma_enable_mem2mem_mode()

◆ dma_enable_memory_increment_mode()

◆ dma_enable_peripheral_increment_mode()

◆ dma_enable_transfer_complete_interrupt()

◆ dma_enable_transfer_error_interrupt()

◆ dma_get_interrupt_flag()

◆ dma_get_number_of_data()

◆ dma_set_channel_request()

◆ dma_set_memory_address()

◆ dma_set_memory_size()

◆ dma_set_number_of_data()

◆ dma_set_peripheral_address()

◆ dma_set_peripheral_size()

◆ dma_set_priority()

◆ dma_set_read_from_memory()

◆ dma_set_read_from_peripheral()