PWR Defines

Defined Constants and Types for the STM32L4xx Power Control More...

Collaboration diagram for PWR Defines:

Modules
	PVD level selection

Macros
#define	PWR_CR1   MMIO32(POWER_CONTROL_BASE + 0x00)
#define	PWR_CR2   MMIO32(POWER_CONTROL_BASE + 0x04)
#define	PWR_CR3   MMIO32(POWER_CONTROL_BASE + 0x08)
#define	PWR_CR4   MMIO32(POWER_CONTROL_BASE + 0x0C)
#define	PWR_SR1   MMIO32(POWER_CONTROL_BASE + 0x10)
#define	PWR_SR2   MMIO32(POWER_CONTROL_BASE + 0x14)
#define	PWR_SCR   MMIO32(POWER_CONTROL_BASE + 0x18)
#define	PWR_PORT_A   MMIO32(POWER_CONTROL_BASE + 0x20)
#define	PWR_PORT_B   MMIO32(POWER_CONTROL_BASE + 0x28)
#define	PWR_PORT_C   MMIO32(POWER_CONTROL_BASE + 0x30)
#define	PWR_PORT_D   MMIO32(POWER_CONTROL_BASE + 0x38)
#define	PWR_PORT_E   MMIO32(POWER_CONTROL_BASE + 0x40)
#define	PWR_PORT_F   MMIO32(POWER_CONTROL_BASE + 0x48)
#define	PWR_PORT_G   MMIO32(POWER_CONTROL_BASE + 0x50)
#define	PWR_PORT_H   MMIO32(POWER_CONTROL_BASE + 0x58)
#define	PWR_PUCR(pwr_port)   MMIO32((pwr_port) + 0x00)
#define	PWR_PDCR(pwr_port)   MMIO32((pwr_port) + 0x04)
#define	PWR_CR1_LPR   (1 << 14)
#define	PWR_CR1_VOS_SHIFT   9
#define	PWR_CR1_VOS_MASK   0x3
#define	PWR_CR1_VOS_RANGE_1   1
#define	PWR_CR1_VOS_RANGE_2   2
#define	PWR_CR1_DBP   (1 << 8)
#define	PWR_CR1_LPMS_SHIFT   0
#define	PWR_CR1_LPMS_MASK   0x07
#define	PWR_CR1_LPMS_STOP_0   0
#define	PWR_CR1_LPMS_STOP_1   1
#define	PWR_CR1_LPMS_STOP_2   2
#define	PWR_CR1_LPMS_STANDBY   3
#define	PWR_CR1_LPMS_SHUTDOWN   4
#define	PWR_CR2_USV   (1 << 10)
#define	PWR_CR2_IOSV   (1 << 9)
#define	PWR_CR2_PVME4   (1 << 7)
#define	PWR_CR2_PVME3   (1 << 6)
#define	PWR_CR2_PVME2   (1 << 5)
#define	PWR_CR2_PVME1   (1 << 4)
#define	PWR_CR2_PLS_SHIFT   1
#define	PWR_CR2_PLS_MASK   0x07
#define	PWR_CR2_PVDE   (1 << 0)
#define	PWR_CR3_EIWUL   (1 << 15)
#define	PWR_CR3_APC   (1 << 10)
#define	PWR_CR3_RRS   (1 << 8)
#define	PWR_CR3_EWUP5   (1 << 4)
#define	PWR_CR3_EWUP4   (1 << 3)
#define	PWR_CR3_EWUP3   (1 << 2)
#define	PWR_CR3_EWUP2   (1 << 1)
#define	PWR_CR3_EWUP1   (1 << 0)
#define	PWR_CR4_VBRS   (1 << 9)
#define	PWR_CR4_VBE   (1 << 8)
#define	PWR_CR4_WP5   (1 << 4)
#define	PWR_CR4_WP4   (1 << 3)
#define	PWR_CR4_WP3   (1 << 2)
#define	PWR_CR4_WP2   (1 << 1)
#define	PWR_CR4_WP1   (1 << 0)
#define	PWR_SR1_WUFI   (1 << 15)
#define	PWR_SR1_SBF   (1 << 8)
#define	PWR_SR1_WUF5   (1 << 4)
#define	PWR_SR1_WUF4   (1 << 3)
#define	PWR_SR1_WUF3   (1 << 2)
#define	PWR_SR1_WUF2   (1 << 1)
#define	PWR_SR1_WUF1   (1 << 0)
#define	PWR_SR2_PVMO4   (1 << 15)
#define	PWR_SR2_PVMO3   (1 << 14)
#define	PWR_SR2_PVMO2   (1 << 13)
#define	PWR_SR2_PVMO1   (1 << 12)
#define	PWR_SR2_PVDO   (1 << 11)
#define	PWR_SR2_VOSF   (1 << 10)
#define	PWR_SR2_REGLPF   (1 << 9)
#define	PWR_SR2_REGLPS   (1 << 8)
#define	PWR_SCR_CSBF   (1 << 8)
#define	PWR_SCR_CWUF5   (1 << 4)
#define	PWR_SCR_CWUF4   (1 << 3)
#define	PWR_SCR_CWUF3   (1 << 2)
#define	PWR_SCR_CWUF2   (1 << 1)
#define	PWR_SCR_CWUF1   (1 << 0)

Enumerations
enum	pwr_vos_scale { PWR_SCALE1 , PWR_SCALE2 }

Functions
void	pwr_set_vos_scale (enum pwr_vos_scale scale)
void	pwr_disable_backup_domain_write_protect (void)
	Disable Backup Domain Write Protection. More...
void	pwr_enable_backup_domain_write_protect (void)
	Re-enable Backup Domain Write Protection. More...

Detailed Description

Defined Constants and Types for the STM32L4xx Power Control

Version

1.0.0

Author

© 2016 Benjamin Levine benja.nosp@m.min@.nosp@m.jesco.nosp@m..kar.nosp@m.oo.co.nosp@m..uk

Date

12 February 2016

LGPL License Terms libopencm3 License

Macro Definition Documentation

PWR_CR1

#define PWR_CR1   MMIO32(POWER_CONTROL_BASE + 0x00)

Definition at line 47 of file l4/pwr.h.

PWR_CR1_DBP

#define PWR_CR1_DBP   (1 << 8)

Definition at line 76 of file l4/pwr.h.

PWR_CR1_LPMS_MASK

#define PWR_CR1_LPMS_MASK   0x07

Definition at line 79 of file l4/pwr.h.

PWR_CR1_LPMS_SHIFT

#define PWR_CR1_LPMS_SHIFT   0

Definition at line 78 of file l4/pwr.h.

PWR_CR1_LPMS_SHUTDOWN

#define PWR_CR1_LPMS_SHUTDOWN   4

Definition at line 84 of file l4/pwr.h.

PWR_CR1_LPMS_STANDBY

#define PWR_CR1_LPMS_STANDBY   3

Definition at line 83 of file l4/pwr.h.

PWR_CR1_LPMS_STOP_0

#define PWR_CR1_LPMS_STOP_0   0

Definition at line 80 of file l4/pwr.h.

PWR_CR1_LPMS_STOP_1

#define PWR_CR1_LPMS_STOP_1   1

Definition at line 81 of file l4/pwr.h.

PWR_CR1_LPMS_STOP_2

#define PWR_CR1_LPMS_STOP_2   2

Definition at line 82 of file l4/pwr.h.

PWR_CR1_LPR

#define PWR_CR1_LPR   (1 << 14)

Definition at line 69 of file l4/pwr.h.

PWR_CR1_VOS_MASK

#define PWR_CR1_VOS_MASK   0x3

Definition at line 72 of file l4/pwr.h.

PWR_CR1_VOS_RANGE_1

#define PWR_CR1_VOS_RANGE_1   1

Definition at line 73 of file l4/pwr.h.

PWR_CR1_VOS_RANGE_2

#define PWR_CR1_VOS_RANGE_2   2

Definition at line 74 of file l4/pwr.h.

PWR_CR1_VOS_SHIFT

#define PWR_CR1_VOS_SHIFT   9

Definition at line 71 of file l4/pwr.h.

PWR_CR2

#define PWR_CR2   MMIO32(POWER_CONTROL_BASE + 0x04)

Definition at line 48 of file l4/pwr.h.

PWR_CR2_IOSV

#define PWR_CR2_IOSV   (1 << 9)

Definition at line 89 of file l4/pwr.h.

PWR_CR2_PLS_MASK

#define PWR_CR2_PLS_MASK   0x07

Definition at line 96 of file l4/pwr.h.

PWR_CR2_PLS_SHIFT

#define PWR_CR2_PLS_SHIFT   1

Definition at line 95 of file l4/pwr.h.

PWR_CR2_PVDE

#define PWR_CR2_PVDE   (1 << 0)

Definition at line 110 of file l4/pwr.h.

PWR_CR2_PVME1

#define PWR_CR2_PVME1   (1 << 4)

Definition at line 93 of file l4/pwr.h.

PWR_CR2_PVME2

#define PWR_CR2_PVME2   (1 << 5)

Definition at line 92 of file l4/pwr.h.

PWR_CR2_PVME3

#define PWR_CR2_PVME3   (1 << 6)

Definition at line 91 of file l4/pwr.h.

PWR_CR2_PVME4

#define PWR_CR2_PVME4   (1 << 7)

Definition at line 90 of file l4/pwr.h.

PWR_CR2_USV

#define PWR_CR2_USV   (1 << 10)

Definition at line 88 of file l4/pwr.h.

PWR_CR3

#define PWR_CR3   MMIO32(POWER_CONTROL_BASE + 0x08)

Definition at line 49 of file l4/pwr.h.

PWR_CR3_APC

#define PWR_CR3_APC   (1 << 10)

Definition at line 115 of file l4/pwr.h.

PWR_CR3_EIWUL

#define PWR_CR3_EIWUL   (1 << 15)

Definition at line 114 of file l4/pwr.h.

PWR_CR3_EWUP1

#define PWR_CR3_EWUP1   (1 << 0)

Definition at line 121 of file l4/pwr.h.

PWR_CR3_EWUP2

#define PWR_CR3_EWUP2   (1 << 1)

Definition at line 120 of file l4/pwr.h.

PWR_CR3_EWUP3

#define PWR_CR3_EWUP3   (1 << 2)

Definition at line 119 of file l4/pwr.h.

PWR_CR3_EWUP4

#define PWR_CR3_EWUP4   (1 << 3)

Definition at line 118 of file l4/pwr.h.

PWR_CR3_EWUP5

#define PWR_CR3_EWUP5   (1 << 4)

Definition at line 117 of file l4/pwr.h.

PWR_CR3_RRS

#define PWR_CR3_RRS   (1 << 8)

Definition at line 116 of file l4/pwr.h.

PWR_CR4

#define PWR_CR4   MMIO32(POWER_CONTROL_BASE + 0x0C)

Definition at line 50 of file l4/pwr.h.

PWR_CR4_VBE

#define PWR_CR4_VBE   (1 << 8)

Definition at line 126 of file l4/pwr.h.

PWR_CR4_VBRS

#define PWR_CR4_VBRS   (1 << 9)

Definition at line 125 of file l4/pwr.h.

PWR_CR4_WP1

#define PWR_CR4_WP1   (1 << 0)

Definition at line 131 of file l4/pwr.h.

PWR_CR4_WP2

#define PWR_CR4_WP2   (1 << 1)

Definition at line 130 of file l4/pwr.h.

PWR_CR4_WP3

#define PWR_CR4_WP3   (1 << 2)

Definition at line 129 of file l4/pwr.h.

PWR_CR4_WP4

#define PWR_CR4_WP4   (1 << 3)

Definition at line 128 of file l4/pwr.h.

PWR_CR4_WP5

#define PWR_CR4_WP5   (1 << 4)

Definition at line 127 of file l4/pwr.h.

PWR_PDCR

#define PWR_PDCR

(

pwr_port

)

MMIO32((pwr_port) + 0x04)

Definition at line 65 of file l4/pwr.h.

PWR_PORT_A

#define PWR_PORT_A   MMIO32(POWER_CONTROL_BASE + 0x20)

Definition at line 55 of file l4/pwr.h.

PWR_PORT_B

#define PWR_PORT_B   MMIO32(POWER_CONTROL_BASE + 0x28)

Definition at line 56 of file l4/pwr.h.

PWR_PORT_C

#define PWR_PORT_C   MMIO32(POWER_CONTROL_BASE + 0x30)

Definition at line 57 of file l4/pwr.h.

PWR_PORT_D

#define PWR_PORT_D   MMIO32(POWER_CONTROL_BASE + 0x38)

Definition at line 58 of file l4/pwr.h.

PWR_PORT_E

#define PWR_PORT_E   MMIO32(POWER_CONTROL_BASE + 0x40)

Definition at line 59 of file l4/pwr.h.

PWR_PORT_F

#define PWR_PORT_F   MMIO32(POWER_CONTROL_BASE + 0x48)

Definition at line 60 of file l4/pwr.h.

PWR_PORT_G

#define PWR_PORT_G   MMIO32(POWER_CONTROL_BASE + 0x50)

Definition at line 61 of file l4/pwr.h.

PWR_PORT_H

#define PWR_PORT_H   MMIO32(POWER_CONTROL_BASE + 0x58)

Definition at line 62 of file l4/pwr.h.

PWR_PUCR

#define PWR_PUCR

(

pwr_port

)

MMIO32((pwr_port) + 0x00)

Definition at line 64 of file l4/pwr.h.

PWR_SCR

#define PWR_SCR   MMIO32(POWER_CONTROL_BASE + 0x18)

Definition at line 53 of file l4/pwr.h.

PWR_SCR_CSBF

#define PWR_SCR_CSBF   (1 << 8)

Definition at line 156 of file l4/pwr.h.

PWR_SCR_CWUF1

#define PWR_SCR_CWUF1   (1 << 0)

Definition at line 161 of file l4/pwr.h.

PWR_SCR_CWUF2

#define PWR_SCR_CWUF2   (1 << 1)

Definition at line 160 of file l4/pwr.h.

PWR_SCR_CWUF3

#define PWR_SCR_CWUF3   (1 << 2)

Definition at line 159 of file l4/pwr.h.

PWR_SCR_CWUF4

#define PWR_SCR_CWUF4   (1 << 3)

Definition at line 158 of file l4/pwr.h.

PWR_SCR_CWUF5

#define PWR_SCR_CWUF5   (1 << 4)

Definition at line 157 of file l4/pwr.h.

PWR_SR1

#define PWR_SR1   MMIO32(POWER_CONTROL_BASE + 0x10)

Definition at line 51 of file l4/pwr.h.

PWR_SR1_SBF

#define PWR_SR1_SBF   (1 << 8)

Definition at line 136 of file l4/pwr.h.

PWR_SR1_WUF1

#define PWR_SR1_WUF1   (1 << 0)

Definition at line 141 of file l4/pwr.h.

PWR_SR1_WUF2

#define PWR_SR1_WUF2   (1 << 1)

Definition at line 140 of file l4/pwr.h.

PWR_SR1_WUF3

#define PWR_SR1_WUF3   (1 << 2)

Definition at line 139 of file l4/pwr.h.

PWR_SR1_WUF4

#define PWR_SR1_WUF4   (1 << 3)

Definition at line 138 of file l4/pwr.h.

PWR_SR1_WUF5

#define PWR_SR1_WUF5   (1 << 4)

Definition at line 137 of file l4/pwr.h.

PWR_SR1_WUFI

#define PWR_SR1_WUFI   (1 << 15)

Definition at line 135 of file l4/pwr.h.

PWR_SR2

#define PWR_SR2   MMIO32(POWER_CONTROL_BASE + 0x14)

Definition at line 52 of file l4/pwr.h.

PWR_SR2_PVDO

#define PWR_SR2_PVDO   (1 << 11)

Definition at line 149 of file l4/pwr.h.

PWR_SR2_PVMO1

#define PWR_SR2_PVMO1   (1 << 12)

Definition at line 148 of file l4/pwr.h.

PWR_SR2_PVMO2

#define PWR_SR2_PVMO2   (1 << 13)

Definition at line 147 of file l4/pwr.h.

PWR_SR2_PVMO3

#define PWR_SR2_PVMO3   (1 << 14)

Definition at line 146 of file l4/pwr.h.

PWR_SR2_PVMO4

#define PWR_SR2_PVMO4   (1 << 15)

Definition at line 145 of file l4/pwr.h.

PWR_SR2_REGLPF

#define PWR_SR2_REGLPF   (1 << 9)

Definition at line 151 of file l4/pwr.h.

PWR_SR2_REGLPS

#define PWR_SR2_REGLPS   (1 << 8)

Definition at line 152 of file l4/pwr.h.

PWR_SR2_VOSF

#define PWR_SR2_VOSF   (1 << 10)

Definition at line 150 of file l4/pwr.h.

Enumeration Type Documentation

pwr_vos_scale

enum pwr_vos_scale

Enumerator
PWR_SCALE1
PWR_SCALE2

Definition at line 165 of file l4/pwr.h.

Function Documentation

pwr_disable_backup_domain_write_protect()

void pwr_disable_backup_domain_write_protect

(

void

)

Disable Backup Domain Write Protection.

This allows backup domain registers to be changed. These registers are write protected after a reset.

Definition at line 61 of file pwr.c.

References PWR_CR1, and PWR_CR1_DBP.

pwr_enable_backup_domain_write_protect()

void pwr_enable_backup_domain_write_protect

(

void

)

Re-enable Backup Domain Write Protection.

This protects backup domain registers from inadvertent change.

Definition at line 70 of file pwr.c.

References PWR_CR1.

pwr_set_vos_scale()

void pwr_set_vos_scale

(

enum pwr_vos_scale

scale

)

Definition at line 39 of file pwr.c.

References PWR_CR1, PWR_CR1_VOS_MASK, PWR_CR1_VOS_RANGE_1, PWR_CR1_VOS_RANGE_2, PWR_CR1_VOS_SHIFT, PWR_SCALE1, and PWR_SCALE2.

Referenced by rcc_clock_setup_pll().

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