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Macros | |
| #define | USART_CR1(usart_base) MMIO32((usart_base) + 0x00) |
| Control register 1 (USARTx_CR1) More... | |
| #define | USART1_CR1 USART_CR1(USART1_BASE) |
| #define | USART2_CR1 USART_CR1(USART2_BASE) |
| #define | USART3_CR1 USART_CR1(USART3_BASE) |
| #define | USART_CR2(usart_base) MMIO32((usart_base) + 0x04) |
| Control register 2 (USARTx_CR2) More... | |
| #define | USART1_CR2 USART_CR2(USART1_BASE) |
| #define | USART2_CR2 USART_CR2(USART2_BASE) |
| #define | USART3_CR2 USART_CR2(USART3_BASE) |
| #define | USART_CR3(usart_base) MMIO32((usart_base) + 0x08) |
| Control register 3 (USARTx_CR3) More... | |
| #define | USART1_CR3 USART_CR3(USART1_BASE) |
| #define | USART2_CR3 USART_CR3(USART2_BASE) |
| #define | USART3_CR3 USART_CR3(USART3_BASE) |
| #define | USART_BRR(usart_base) MMIO32((usart_base) + 0x0C) |
| Baud rate register (USARTx_BRR) More... | |
| #define | USART1_BRR USART_BRR(USART1_BASE) |
| #define | USART2_BRR USART_BRR(USART2_BASE) |
| #define | USART3_BRR USART_BRR(USART3_BASE) |
| #define | USART_GTPR(usart_base) MMIO32((usart_base) + 0x10) |
| Guard time and prescaler register (USARTx_GTPR) More... | |
| #define | USART1_GTPR USART_GTPR(USART1_BASE) |
| #define | USART2_GTPR USART_GTPR(USART2_BASE) |
| #define | USART3_GTPR USART_GTPR(USART3_BASE) |
| #define | USART_RTOR(usart_base) MMIO32((usart_base) + 0x14) |
| Receiver timeout register (USART_RTOR) More... | |
| #define | USART1_RTOR USART_RTOR(USART1_BASE) |
| #define | USART2_RTOR USART_RTOR(USART2_BASE) |
| #define | USART3_RTOR USART_RTOR(USART3_BASE) |
| #define | USART_RQR(usart_base) MMIO32((usart_base) + 0x18) |
| Request register (USART_RQR) More... | |
| #define | USART1_RQR USART_RQR(USART1_BASE) |
| #define | USART2_RQR USART_RQR(USART2_BASE) |
| #define | USART3_RQR USART_RQR(USART3_BASE) |
| #define | USART_ISR(usart_base) MMIO32((usart_base) + 0x1C) |
| Interrupt & status register (USART_ISR) More... | |
| #define | USART1_ISR USART_ISR(USART1_BASE) |
| #define | USART2_ISR USART_ISR(USART2_BASE) |
| #define | USART3_ISR USART_ISR(USART3_BASE) |
| #define | USART_ICR(usart_base) MMIO32((usart_base) + 0x20) |
| Interrupt flag clear register (USART_ICR) More... | |
| #define | USART1_ICR USART_ICR(USART1_BASE) |
| #define | USART2_ICR USART_ICR(USART2_BASE) |
| #define | USART3_ICR USART_ICR(USART3_BASE) |
| #define | USART_RDR(usart_base) MMIO32((usart_base) + 0x24) |
| Receive data register (USART_RDR) More... | |
| #define | USART1_RDR USART_RDR(USART1_BASE) |
| #define | USART2_RDR USART_RDR(USART2_BASE) |
| #define | USART3_RDR USART_RDR(USART3_BASE) |
| #define | USART_TDR(usart_base) MMIO32((usart_base) + 0x28) |
| Transmit data register (USART_TDR) More... | |
| #define | USART1_TDR USART_TDR(USART1_BASE) |
| #define | USART2_TDR USART_TDR(USART2_BASE) |
| #define | USART3_TDR USART_TDR(USART3_BASE) |
| #define | USART_FLAG_PE USART_ISR_PE |
| #define | USART_FLAG_FE USART_ISR_FE |
| #define | USART_FLAG_NF USART_ISR_NF |
| #define | USART_FLAG_ORE USART_ISR_ORE |
| #define | USART_FLAG_IDLE USART_ISR_IDLE |
| #define | USART_FLAG_RXNE USART_ISR_RXNE |
| #define | USART_FLAG_TC USART_ISR_TC |
| #define | USART_FLAG_TXE USART_ISR_TXE |
| #define | USART_CR1_M1 (1 << 28) /* F07x */ |
| M1: Wordlength. More... | |
| #define | USART_CR1_EOBIE (1 << 27) |
| EOBIE: End of Block interrupt enable. More... | |
| #define | USART_CR1_RTOIE (1 << 26) |
| RTOIE: Receiver timeout interrupt enable. More... | |
| #define | USART_CR1_DEAT_SHIFT 21 |
| #define | USART_CR1_DEAT (0x1F << USART_CR1_DEAT_SHIFT) |
| #define | USART_CR1_DEAT_VAL(x) ((x) << USART_CR1_DEAT_SHIFT) |
| DEAT[4:0]: Driver Enable assertion time. More... | |
| #define | USART_CR1_DEDT_SHIFT 16 |
| #define | USART_CR1_DEDT (0x1F << USART_CR1_DEDT_SHIFT) |
| #define | USART_CR1_DEDT_VAL(x) ((x) << USART_CR1_DEDT_SHIFT) |
| DEDT[4:0]: Driver Enable deassertion time. More... | |
| #define | USART_CR1_OVER8 (1 << 15) |
| OVER8: Oversampling mode. More... | |
| #define | USART_CR1_CMIE (1 << 14) |
| CMIE: Character match interrupt enable. More... | |
| #define | USART_CR1_MME (1 << 13) |
| MME: Mute mode enable. More... | |
| #define | USART_CR1_M0 (1 << 12) |
| M0: Word length. More... | |
| #define | USART_CR1_M USART_CR1_M0 |
| #define | USART_CR1_WAKE (1 << 11) |
| WAKE: Receiver wakeup method. More... | |
| #define | USART_CR1_PCE (1 << 10) |
| PCE: Parity control enable. More... | |
| #define | USART_CR1_PS (1 << 9) |
| PS: Parity selection. More... | |
| #define | USART_CR1_PEIE (1 << 8) |
| PEIE: PE interrupt enable. More... | |
| #define | USART_CR1_TXEIE (1 << 7) |
| TXEIE: Interrupt enable. More... | |
| #define | USART_CR1_TCIE (1 << 6) |
| TCIE: Transmission complete interrupt enable. More... | |
| #define | USART_CR1_RXNEIE (1 << 5) |
| RXNEIE: RXNE interrupt enable. More... | |
| #define | USART_CR1_IDLEIE (1 << 4) |
| IDLEIE: IDLE interrupt enable. More... | |
| #define | USART_CR1_TE (1 << 3) |
| TE: Transmitter enable. More... | |
| #define | USART_CR1_RE (1 << 2) |
| RE: Receiver enable. More... | |
| #define | USART_CR1_UESM (1 << 1) |
| UESM: USART enable in Stop mode. More... | |
| #define | USART_CR1_UE (1 << 0) |
| UE: USART enable. More... | |
| #define | USART_CR2_ADD_SHIFT 24 |
| ADD[7:0]: Address of the USART node. More... | |
| #define | USART_CR2_ADD (0xFF << USART_CR2_ADD_SHIFT) |
| #define | USART_CR2_ADD_VAL(x) ((x) << USART_CR2_ADD_SHIFT) |
| #define | USART_CR2_ABRMOD_MASK 3 |
| #define | USART_CR2_ABRMOD_SHIFT 21 |
| #define | USART_CR2_ABRMOD_STARTBIT (0x0 << USART_CR2_ABRMOD_SHIFT) |
| #define | USART_CR2_ABRMOD_FALL_EDGE (0x1 << USART_CR2_ABRMOD_SHIFT) |
| #define | USART_CR2_ABRMOD_FRAME_0x7F (0x2 << USART_CR2_ABRMOD_SHIFT) |
| #define | USART_CR2_ABRMOD_FRAME_0x55 (0x3 << USART_CR2_ABRMOD_SHIFT) |
| #define | USART_CR2_RTOEN (1 << 23) |
| RTOEN: Receiver timeout enable. More... | |
| #define | USART_CR2_ABREN (1 << 20) |
| ABREN: Auto baud rate enable. More... | |
| #define | USART_CR2_MSBFIRST (1 << 19) |
| MSBFIRST: Most significant bit first. More... | |
| #define | USART_CR2_DATAINV (1 << 18) |
| DATAINV: Binary data inversion. More... | |
| #define | USART_CR2_TXINV (1 << 17) |
| TXINV: TX pin active level inversion. More... | |
| #define | USART_CR2_RXINV (1 << 16) |
| RXINV: RX pin active level inversion. More... | |
| #define | USART_CR2_SWAP (1 << 15) |
| SWAP: Swap TX/RX pins. More... | |
| #define | USART_CR2_LINEN (1 << 14) |
| LINEN: LIN mode enable. More... | |
| #define | USART_CR2_CLKEN (1 << 11) |
| CLKEN: Clock enable. More... | |
| #define | USART_CR2_CPOL (1 << 10) |
| CPOL: Clock polarity. More... | |
| #define | USART_CR2_CPHA (1 << 9) |
| CPHA: Clock phase. More... | |
| #define | USART_CR2_LBCL (1 << 8) |
| LBCL: Last bit clock pulse. More... | |
| #define | USART_CR2_LBDIE (1 << 6) |
| LBDIE: LIN break detection interrupt enable. More... | |
| #define | USART_CR2_LBDL (1 << 5) |
| LBDL: LIN break detection length. More... | |
| #define | USART_CR2_ADDM7 (1 << 4) |
| ADDM7:7-bit Address Detection/4-bit Address Detection. More... | |
| #define | USART_CR3_WUFIE (1 << 22) |
| WUFIE: Wakeup from Stop mode interrupt enable. More... | |
| #define | USART_CR3_WUS_ADDRMATCH (0x0 << 20) |
| WUS[1:0]: Wakeup from Stop mode interrupt flag selection. More... | |
| #define | USART_CR3_WUS_START_BIT (0x2 << 20) |
| #define | USART_CR3_WUS_RXNE (0x3 << 20) |
| #define | USART_CR3_SCARCNT_SHIFT 17 |
| #define | USART_CR3_SCARCNT_MASK 0x7 |
| #define | USART_CR3_SCARCNT_DISABLE (0 << USART_CR3_SCARCNT_SHIFT) |
| SCARCNT[2:0]: Smartcard auto retry count. More... | |
| #define | USART_CR3_SCARCNT_VAL(x) ((x) << USART_CR3_SCARCNT_SHIFT) |
| #define | USART_CR3_DEP (1 << 15) |
| DEP: Driver enable polarity selection. More... | |
| #define | USART_CR3_DEM (1 << 14) |
| DEM: Driver enable mode. More... | |
| #define | USART_CR3_DDRE (1 << 13) |
| DDRE: DMA Disable on Reception Error. More... | |
| #define | USART_CR3_OVRDIS (1 << 12) |
| OVRDIS: Overrun Disable. More... | |
| #define | USART_CR3_ONEBIT (1 << 11) |
| ONEBIT: One sample bit method enable. More... | |
| #define | USART_CR3_CTSIE (1 << 10) |
| CTSIE: CTS interrupt enable. More... | |
| #define | USART_CR3_CTSE (1 << 9) |
| CTSE: CTS enable. More... | |
| #define | USART_CR3_RTSE (1 << 8) |
| RTSE: RTS enable. More... | |
| #define | USART_CR3_DMAT (1 << 7) |
| DMAT: DMA enable transmitter. More... | |
| #define | USART_CR3_DMAR (1 << 6) |
| DMAR: DMA enable receiver. More... | |
| #define | USART_CR3_SCEN (1 << 5) |
| SCEN: Smartcard mode enable. More... | |
| #define | USART_CR3_NACK (1 << 4) |
| NACK: Smartcard NACK enable. More... | |
| #define | USART_CR3_HDSEL (1 << 3) |
| HDSEL: Half-duplex selection. More... | |
| #define | USART_CR3_IRLP (1 << 2) |
| IRLP: IrDA low-power. More... | |
| #define | USART_CR3_IREN (1 << 1) |
| IREN: IrDA mode enable. More... | |
| #define | USART_CR3_EIE (1 << 0) |
| EIE: Error interrupt enable. More... | |
| #define | USART_GTPR_GT_SHIFT 8 |
| #define | USART_GTPR_GT (0xFF << USART_GTPR_GT_SHIFT) |
| #define | USART_GTPR_GT_VAL(x) ((x) << USART_GTPR_GT_SHIFT) |
| #define | USART_GTPR_PSC_SHIFT 0 |
| #define | USART_GTPR_PSC (0xFF << USART_GTPR_PSC_SHIFT) |
| #define | USART_GTPR_PSC_VAL(x) ((x) << USART_GTPR_PSC_SHIFT) |
| #define | USART_RTOR_BLEN_SHIFT 24 |
| BLEN[7:0]: Block Length. More... | |
| #define | USART_RTOR_BLEN_MASK (0xFF << USART_RTOR_BLEN_SHIFT) |
| #define | USART_RTOR_BLEN_VAL(x) ((x) << USART_RTOR_BLEN_SHIFT) |
| #define | USART_RTOR_RTO_SHIFT 0 |
| RTO[23:0]: Receiver timeout value. More... | |
| #define | USART_RTOR_RTO_MASK (0xFFFFF << USART_RTOR_RTO_SHIFT) |
| #define | USART_RTOR_RTO_VAL(x) ((x) << USART_RTOR_RTO_SHIFT) |
| #define | USART_RQR_TXFRQ (1 << 4) |
| TXFRQ: Transmit data flush request. More... | |
| #define | USART_RQR_RXFRQ (1 << 3) |
| RXFRQ: Receive data flush request. More... | |
| #define | USART_RQR_MMRQ (1 << 2) |
| MMRQ: Mute mode request. More... | |
| #define | USART_RQR_SBKRQ (1 << 1) |
| SBKRQ: Send break request. More... | |
| #define | USART_RQR_ABRRQ (1 << 0) |
| ABRRQ: Auto baud rate request. More... | |
| #define | USART_ISR_REACK (1 << 22) |
| REACK: Receive enable acknowledge flag. More... | |
| #define | USART_ISR_TEACK (1 << 21) |
| TEACK: Transmit enable acknowledge flag. More... | |
| #define | USART_ISR_WUF (1 << 20) |
| WUF: Wakeup from Stop mode flag. More... | |
| #define | USART_ISR_RWU (1 << 19) |
| RWU: Receiver wakeup from Mute mode. More... | |
| #define | USART_ISR_SBKF (1 << 18) |
| SBKF: Send break flag. More... | |
| #define | USART_ISR_CMF (1 << 17) |
| CMF: Character match flag. More... | |
| #define | USART_ISR_BUSY (1 << 16) |
| BUSY: Busy flag. More... | |
| #define | USART_ISR_ABRF (1 << 15) |
| ABRF: Auto baud rate flag. More... | |
| #define | USART_ISR_ABRE (1 << 14) |
| ABRE: Auto baud rate error. More... | |
| #define | USART_ISR_EOBF (1 << 12) |
| EOBF: End of block flag. More... | |
| #define | USART_ISR_RTOF (1 << 11) |
| RTOF: Receiver timeout. More... | |
| #define | USART_ISR_CTS (1 << 10) |
| CTS: CTS flag. More... | |
| #define | USART_ISR_CTSIF (1 << 9) |
| CTSIF: CTS interrupt flag. More... | |
| #define | USART_ISR_LBDF (1 << 8) |
| LBDF: LIN break detection flag. More... | |
| #define | USART_ISR_TXE (1 << 7) |
| TXE: Transmit data register empty. More... | |
| #define | USART_ISR_TC (1 << 6) |
| TC: Transmission complete. More... | |
| #define | USART_ISR_RXNE (1 << 5) |
| RXNE: Read data register not empty. More... | |
| #define | USART_ISR_IDLE (1 << 4) |
| IDLE: Idle line detected. More... | |
| #define | USART_ISR_ORE (1 << 3) |
| ORE: Overrun error. More... | |
| #define | USART_ISR_NF (1 << 2) |
| NF: Noise detected flag. More... | |
| #define | USART_ISR_FE (1 << 1) |
| FE: Framing error. More... | |
| #define | USART_ISR_PE (1 << 0) |
| PE: Parity error. More... | |
| #define | USART_ICR_WUCF (1 << 20) |
| WUCF: Wakeup from Stop mode clear flag. More... | |
| #define | USART_ICR_CMCF (1 << 17) |
| CMCF: Character match clear flag. More... | |
| #define | USART_ICR_EOBCF (1 << 12) |
| EOBCF: End of timeout clear flag. More... | |
| #define | USART_ICR_RTOCF (1 << 11) |
| RTOCF: Receiver timeout clear flag. More... | |
| #define | USART_ICR_CTSCF (1 << 9) |
| CTSCF: CTS clear flag. More... | |
| #define | USART_ICR_LBDCF (1 << 8) |
| LBDCF: LIN break detection clear flag. More... | |
| #define | USART_ICR_TCCF (1 << 6) |
| TCCF: Transmission complete clear flag. More... | |
| #define | USART_ICR_IDLECF (1 << 4) |
| IDLECF: Idle line detected clear flag. More... | |
| #define | USART_ICR_ORECF (1 << 3) |
| ORECF: Overrun error clear flag. More... | |
| #define | USART_ICR_NCF (1 << 2) |
| NCF: Noise detected clear flag. More... | |
| #define | USART_ICR_FECF (1 << 1) |
| FECF: Framing error clear flag. More... | |
| #define | USART_ICR_PECF (1 << 0) |
| PECF: Parity error clear flag. More... | |
| #define | USART_RDR_MASK (0x1FF << 0) |
| RDR[8:0]: Receive data value. More... | |
| #define | USART_TDR_MASK (0x1FF << 0) |
| TDR[8:0]: Transmit data value. More... | |
Functions | |
| void | usart_enable_data_inversion (uint32_t usart) |
| USART enable data inversion. More... | |
| void | usart_disable_data_inversion (uint32_t usart) |
| USART disable data inversion. More... | |
| void | usart_enable_tx_inversion (uint32_t usart) |
| USART Enable TX pin active level inversion. More... | |
| void | usart_disable_tx_inversion (uint32_t usart) |
| USART Disable TX pin active level inversion. More... | |
| void | usart_enable_rx_inversion (uint32_t usart) |
| USART Enable RX pin active level inversion. More... | |
| void | usart_disable_rx_inversion (uint32_t usart) |
| USART Disable RX pin active level inversion. More... | |
| void | usart_enable_halfduplex (uint32_t usart) |
| USART Enable Half-duplex. More... | |
| void | usart_disable_halfduplex (uint32_t usart) |
| USART Disable Half-duplex. More... | |
| void | usart_set_rx_timeout_value (uint32_t usart, uint32_t value) |
| USART Set receiver timeout value. More... | |
| void | usart_enable_rx_timeout (uint32_t usart) |
| USART enable receive timeout function. More... | |
| void | usart_disable_rx_timeout (uint32_t usart) |
| USART disable receive timeout function. More... | |
| void | usart_enable_rx_timeout_interrupt (uint32_t usart) |
| USART enable receive timeout interrupt. More... | |
| void | usart_disable_rx_timeout_interrupt (uint32_t usart) |
| USART disable receive timeout interrupt. More... | |
