libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
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Configuring interrupts from GPIO pins More...
Functions | |
void | gpio_configure_trigger (uint32_t gpioport, enum gpio_trigger trigger, uint8_t gpios) |
Configure the interrupt trigger on the given GPIO pins. More... | |
void | gpio_enable_interrupts (uint32_t gpioport, uint8_t gpios) |
Enable interrupts on specified GPIO pins. More... | |
void | gpio_disable_interrupts (uint32_t gpioport, uint8_t gpios) |
Disable interrupts on specified GPIO pins. More... | |
static bool | gpio_is_interrupt_source (uint32_t gpioport, uint8_t srcpins) |
Determine if interrupt is generated by the given pin. More... | |
static void | gpio_clear_interrupt_flag (uint32_t gpioport, uint8_t gpios) |
Mark interrupt as serviced. More... | |
Configuring interrupts from GPIO pins
GPIO pins can trigger interrupts on either edges or levels. The type of trigger can be configured with gpio_configure_int_trigger(). To have an event on the given pin generate an interrupt, its interrupt source must be unmasked. This can be achieved with gpio_enable_interrupts(). Interrupts which are no longer needed can be disabled through gpio_disable_interrupts().
In order for the interrupt to generate an IRQ and a call to the interrupt service routine, the interrupt for the GPIO port must be routed through the NVIC with nvic_enable_irq(). For this last step, the nvic.h header is needed:
Enabling an interrupt is as simple as configuring the desired trigger, unmasking the desired interrupt, and routing the desired GPIO port's interrupt through the NVIC.
After interrupts are properly enabled and routed through the NVIC, when an event occurs, the appropriate IRQ flag is set by hardware, and execution jumps to the GPIO ISR. The ISR should query the IRQ flags to determine which event caused the interrupt. For this, use gpio_is_interrupt_source(), with the desired GPIO flag. After one or more interrupt sources are serviced, the IRQ flags must be cleared by the ISR. This can be done with gpio_clear_interrupt_flag().
A typical GPIO ISR may look like the following:
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inlinestatic |
Mark interrupt as serviced.
After an interrupt is services, its flag must be cleared. If the flag is not cleared, then execution will jump back to the start of the ISR after the ISR returns.
[in] | gpioport | GPIO block register address base GPIO register base addresses |
[in] | gpios | GPIO pin identifiers. Any combination of pins may be specified by OR'ing then together. |
Definition at line 369 of file gpio.h.
References GPIO_ICR.
void gpio_configure_trigger | ( | uint32_t | gpioport, |
enum gpio_trigger | trigger, | ||
uint8_t | gpios | ||
) |
Configure the interrupt trigger on the given GPIO pins.
Sets the Pin direction, analog/digital mode, and pull-up configuration of or a set of GPIO pins on a given GPIO port.
[in] | gpioport | GPIO block register address base GPIO register base addresses |
[in] | trigger | Trigger configuration (gpio_trigger)
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[in] | gpios | GPIO pin identifiers. Any combination of pins may be specified by OR'ing then together |
Definition at line 527 of file gpio.c.
References GPIO_IBE, GPIO_IEV, GPIO_IS, GPIO_TRIG_EDGE_BOTH, GPIO_TRIG_EDGE_FALL, GPIO_TRIG_EDGE_RISE, GPIO_TRIG_LVL_HIGH, and GPIO_TRIG_LVL_LOW.
void gpio_disable_interrupts | ( | uint32_t | gpioport, |
uint8_t | gpios | ||
) |
Disable interrupts on specified GPIO pins.
Disable interrupts on the specified GPIO pins
Note that the NVIC must be enabled and properly configured for the interrupt to be routed to the CPU.
[in] | gpioport | GPIO block register address base GPIO register base addresses |
[in] | gpios | GPIO pin identifiers. Pins whose interrupts to disable. Any combination of pins may be specified by OR'ing them together. |
Definition at line 590 of file gpio.c.
References GPIO_IM.
void gpio_enable_interrupts | ( | uint32_t | gpioport, |
uint8_t | gpios | ||
) |
Enable interrupts on specified GPIO pins.
Enable interrupts on the specified GPIO pins
Note that the NVIC must be enabled and properly configured for the interrupt to be routed to the CPU.
[in] | gpioport | GPIO block register address base GPIO register base addresses |
[in] | gpios | GPIO pin identifiers. Pins whose interrupts to enable. Any combination of pins may be specified by OR'ing them together. |
Definition at line 572 of file gpio.c.
References GPIO_IM.
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inlinestatic |
Determine if interrupt is generated by the given pin.
[in] | gpioport | GPIO block register address base GPIO register base addresses |
[in] | srcpins | source pin or group of pins to check. |
Definition at line 353 of file gpio.h.
References GPIO_MIS.