Defined Constants and Types for the LM4F Reset and Clock Control More...

Collaboration diagram for Reset and Clock Control:

Enumerations
enum	osc_src { OSCSRC_MOSC = SYSCTL_RCC2_OSCSRC2_MOSC , OSCSRC_PIOSC = SYSCTL_RCC2_OSCSRC2_PIOSC , OSCSRC_PIOSC_D4 = SYSCTL_RCC2_OSCSRC2_PIOSC_D4 , OSCSRC_30K_INT = SYSCTL_RCC2_OSCSRC2_30K , OSCSRC_32K_EXT = SYSCTL_RCC2_OSCSRC2_32K768 }
	Oscillator source values. More...

enum	pwm_clkdiv { PWMDIV_2 = SYSCTL_RCC_PWMDIV_2 , PWMDIV_4 = SYSCTL_RCC_PWMDIV_4 , PWMDIV_8 = SYSCTL_RCC_PWMDIV_8 , PWMDIV_16 = SYSCTL_RCC_PWMDIV_16 , PWMDIV_32 = SYSCTL_RCC_PWMDIV_32 , PWMDIV_64 = SYSCTL_RCC_PWMDIV_64 }
	PWM clock divisor values. More...

enum	xtal_t { XTAL_4M = SYSCTL_RCC_XTAL_4M , XTAL_4M_096 = SYSCTL_RCC_XTAL_4M_096 , XTAL_4M_9152 = SYSCTL_RCC_XTAL_4M_9152 , XTAL_5M = SYSCTL_RCC_XTAL_5M , XTAL_5M_12 = SYSCTL_RCC_XTAL_5M_12 , XTAL_6M = SYSCTL_RCC_XTAL_6M , XTAL_6M_144 = SYSCTL_RCC_XTAL_6M_144 , XTAL_7M_3728 = SYSCTL_RCC_XTAL_7M_3728 , XTAL_8M = SYSCTL_RCC_XTAL_8M , XTAL_8M_192 = SYSCTL_RCC_XTAL_8M_192 , XTAL_10M = SYSCTL_RCC_XTAL_10M , XTAL_12M = SYSCTL_RCC_XTAL_12M , XTAL_12M_288 = SYSCTL_RCC_XTAL_12M_288 , XTAL_13M_56 = SYSCTL_RCC_XTAL_13M_56 , XTAL_14M_31818 = SYSCTL_RCC_XTAL_14M_31818 , XTAL_16M = SYSCTL_RCC_XTAL_16M , XTAL_16M_384 = SYSCTL_RCC_XTAL_16M_384 , XTAL_18M = SYSCTL_RCC_XTAL_18M , XTAL_20M = SYSCTL_RCC_XTAL_20M , XTAL_24M = SYSCTL_RCC_XTAL_24M , XTAL_25M = SYSCTL_RCC_XTAL_25M }
	Predefined crystal values. More...

Functions
void	rcc_configure_xtal (enum xtal_t xtal)
	Configure the crystal type connected to the device. More...

void	rcc_disable_main_osc (void)
	Disable the main oscillator. More...

void	rcc_disable_interal_osc (void)
	Disable the internal oscillator. More...

void	rcc_enable_main_osc (void)
	Enable the main oscillator. More...

void	rcc_enable_interal_osc (void)
	Enable the internal oscillator. More...

void	rcc_enable_rcc2 (void)
	Enable the use of SYSCTL_RCC2 register for clock control. More...

void	rcc_pll_off (void)
	Power down the main PLL. More...

void	rcc_pll_on (void)
	Power up the main PLL. More...

void	rcc_set_osc_source (enum osc_src src)
	Set the oscillator source to be used by the system clock. More...

void	rcc_pll_bypass_disable (void)
	Disable the PLL bypass and use the PLL clock. More...

void	rcc_pll_bypass_enable (void)
	Enable the PLL bypass and use the oscillator clock. More...

void	rcc_set_pll_divisor (uint8_t div400)
	Set the PLL clock divisor (from 400MHz) More...

void	rcc_set_pwm_divisor (enum pwm_clkdiv div)
	Set the PWM unit clock divisor. More...

void	rcc_usb_pll_off (void)
	Power down the USB PLL. More...

void	rcc_usb_pll_on (void)
	Power up the USB PLL. More...

void	rcc_wait_for_pll_ready (void)
	Wait for main PLL to lock. More...

void	rcc_change_pll_divisor (uint8_t plldiv400)
	Change the PLL divisor. More...

uint32_t	rcc_get_system_clock_frequency (void)
	Get the system clock frequency. More...

void	rcc_sysclk_config (enum osc_src src, enum xtal_t xtal, uint8_t pll_div400)
	Configure the system clock source. More...

Detailed Description

Defined Constants and Types for the LM4F Reset and Clock Control

Version: 1.0.0

Author: © 2012 Alexandru Gagniuc mr.nu.nosp@m.ke.m.nosp@m.e@gma.nosp@m.il.c.nosp@m.om

Date: 10 March 2013

LGPL License Terms libopencm3 License

Enumeration Type Documentation

◆ osc_src

enum osc_src

Oscillator source values.

Possible values of the oscillator source.

Enumerator
OSCSRC_MOSC
OSCSRC_PIOSC
OSCSRC_PIOSC_D4
OSCSRC_30K_INT
OSCSRC_32K_EXT

Definition at line 48 of file rcc.h.

◆ pwm_clkdiv

enum pwm_clkdiv

PWM clock divisor values.

Possible values of the binary divisor used to predivide the system clock down for use as the timing reference for the PWM module.

Enumerator
PWMDIV_2
PWMDIV_4
PWMDIV_8
PWMDIV_16
PWMDIV_32
PWMDIV_64

Definition at line 62 of file rcc.h.

◆ xtal_t

enum xtal_t

Predefined crystal values.

Predefined crystal values for the XTAL field in SYSCTL_RCC. Using these predefined values in the XTAL field, the SYSCTL_PLLFREQ0 and SYSCTL_PLLFREQ1 are automatically adjusted in hardware to provide a PLL clock of 400MHz.

Enumerator
XTAL_4M
XTAL_4M_096
XTAL_4M_9152
XTAL_5M
XTAL_5M_12
XTAL_6M
XTAL_6M_144
XTAL_7M_3728
XTAL_8M
XTAL_8M_192
XTAL_10M
XTAL_12M
XTAL_12M_288
XTAL_13M_56
XTAL_14M_31818
XTAL_16M
XTAL_16M_384
XTAL_18M
XTAL_20M
XTAL_24M
XTAL_25M

Definition at line 79 of file rcc.h.

Function Documentation

◆ rcc_change_pll_divisor()

void rcc_change_pll_divisor ( uint8_t pll_div400 )

Change the PLL divisor.

Changes the divisor applied to the 400MHz PLL clock. The PLL must have previously been configured by selecting an appropriate XTAL value, and turning on the PLL. This function does not reconfigure the XTAL value or oscillator source. It only changes the PLL divisor.

The PLL is bypassed before modifying the divisor, and the function blocks until the PLL is locked, then the bypass is disabled, before returning.

Parameters

[in] pll_div400 The clock divisor to apply to the 400MHz PLL clock.

Definition at line 364 of file rcc.c.

References lm4f_rcc_sysclk_freq, rcc_pll_bypass_disable(), rcc_pll_bypass_enable(), rcc_set_pll_divisor(), and rcc_wait_for_pll_ready().

Referenced by rcc_sysclk_config().

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◆ rcc_configure_xtal()

void rcc_configure_xtal ( enum xtal_t xtal )

Configure the crystal type connected to the device.

Configure the crystal type connected between the OSCO and OSCI pins by writing the appropriate value to the XTAL field in SYSCTL_RCC. The PLL parameters are automatically adjusted in hardware to provide a PLL clock of 400MHz.

Parameters

[in] xtal predefined crystal type

See also: xtal_t

Definition at line 119 of file rcc.c.

References SYSCTL_RCC, and SYSCTL_RCC_XTAL_MASK.

Referenced by rcc_sysclk_config().

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◆ rcc_disable_interal_osc()

void rcc_disable_interal_osc ( void )

Disable the internal oscillator.

Sets the IOSCDIS bit in SYSCTL_RCC, disabling the internal oscillator.

Definition at line 144 of file rcc.c.

References SYSCTL_RCC, and SYSCTL_RCC_IOSCDIS.

◆ rcc_disable_main_osc()

void rcc_disable_main_osc ( void )

Disable the main oscillator.

Sets the IOSCDIS bit in SYSCTL_RCC, disabling the main oscillator.

Definition at line 134 of file rcc.c.

References SYSCTL_RCC, and SYSCTL_RCC_MOSCDIS.

◆ rcc_enable_interal_osc()

void rcc_enable_interal_osc ( void )

Enable the internal oscillator.

Clears the IOSCDIS bit in SYSCTL_RCC, enabling the internal oscillator.

Definition at line 164 of file rcc.c.

References SYSCTL_RCC.

◆ rcc_enable_main_osc()

void rcc_enable_main_osc ( void )

Enable the main oscillator.

Clears the MOSCDIS bit in SYSCTL_RCC, enabling the main oscillator.

Definition at line 154 of file rcc.c.

References SYSCTL_RCC.

Referenced by rcc_sysclk_config().

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◆ rcc_enable_rcc2()

void rcc_enable_rcc2 ( void )

Enable the use of SYSCTL_RCC2 register for clock control.

Enables the USERCC2 bit in SYSCTTL_RCC2. Settings in SYSCTL_RCC2 will override settings in SYSCTL_RCC. This function must be called before other calls to manipulate the clock, as libopencm3 uses the SYSCTL_RCC2 register.

Definition at line 177 of file rcc.c.

References SYSCTL_RCC2, and SYSCTL_RCC2_USERCC2.

Referenced by rcc_sysclk_config().

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◆ rcc_get_system_clock_frequency()

uint32_t rcc_get_system_clock_frequency ( void )

Get the system clock frequency.

Returns: System clock frequency in Hz

Definition at line 383 of file rcc.c.

References lm4f_rcc_sysclk_freq.

Referenced by uart_set_baudrate().

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◆ rcc_pll_bypass_disable()

void rcc_pll_bypass_disable ( void )

Disable the PLL bypass and use the PLL clock.

Clear BYPASS2 in SYSCTL_RCC2. The system clock is derived from the PLL clock divided by the divisor specified in SYSDIV2.

USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this function.

Definition at line 235 of file rcc.c.

References SYSCTL_RCC2.

Referenced by rcc_change_pll_divisor().

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◆ rcc_pll_bypass_enable()

void rcc_pll_bypass_enable ( void )

Enable the PLL bypass and use the oscillator clock.

Set BYPASS2 in SYSCTL_RCC2. The system clock is derived from the oscillator clock divided by the divisor specified in SYSDIV2.

USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this function.

Definition at line 249 of file rcc.c.

References SYSCTL_RCC2, and SYSCTL_RCC2_BYPASS2.

Referenced by rcc_change_pll_divisor(), and rcc_sysclk_config().

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◆ rcc_pll_off()

void rcc_pll_off ( void )

Power down the main PLL.

Sets the SYSCTL_RCC2_PWRDN2 in SYSCTL_RCC2 to power down the PLL.

USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this function.

Definition at line 190 of file rcc.c.

References SYSCTL_RCC2, and SYSCTL_RCC2_PWRDN2.

◆ rcc_pll_on()

void rcc_pll_on ( void )

Power up the main PLL.

Clears the PWRDN2 in SYSCTL_RCC2 to power on the PLL.

USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this function.

Definition at line 203 of file rcc.c.

References SYSCTL_RCC2.

Referenced by rcc_sysclk_config().

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◆ rcc_set_osc_source()

void rcc_set_osc_source ( enum osc_src src )

Set the oscillator source to be used by the system clock.

Set the clock source for the system clock.

USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this function.

Definition at line 216 of file rcc.c.

References SYSCTL_RCC2, and SYSCTL_RCC2_OSCSRC2_MASK.

Referenced by rcc_sysclk_config().

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◆ rcc_set_pll_divisor()

void rcc_set_pll_divisor ( uint8_t div400 )

Set the PLL clock divisor (from 400MHz)

Set the binary divisor used to predivide the system clock down for use as the timing reference for the PWM module. The divisor is expected to be a divisor from 400MHz, not 200MHz. The DIV400 is also set.

Specifies the divisor that used to generate the system clock from either the PLL output or the oscillator source (depending on the BYPASS2 bit in SYSCTL_RCC2). SYSDIV2 is used for the divisor when both the USESYSDIV bit in SYSCTL_RCC is set.

USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this function.

Parameters

[in] div clock divisor to apply to the 400MHz PLL clock. It is the caller's responsibility to ensure that the divisor will not create a system clock that is out of spec.

Definition at line 273 of file rcc.c.

References SYSCTL_RCC, SYSCTL_RCC2, SYSCTL_RCC2_DIV400, SYSCTL_RCC2_SYSDIV400_MASK, and SYSCTL_RCC_USESYSDIV.

Referenced by rcc_change_pll_divisor().

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◆ rcc_set_pwm_divisor()

void rcc_set_pwm_divisor ( enum pwm_clkdiv div )

Set the PWM unit clock divisor.

Set the binary divisor used to predivide the system clock down for use as the timing reference for the PWM module.

Parameters

[in] div clock divisor to use

See also: pwm_clkdiv_t

Definition at line 294 of file rcc.c.

References SYSCTL_RCC, and SYSCTL_RCC_PWMDIV_MASK.

◆ rcc_sysclk_config()

void rcc_sysclk_config	(	enum osc_src	src,
		enum xtal_t	xtal,
		uint8_t	pll_div400
	)

Configure the system clock source.

Sets up the system clock, including configuring the oscillator source, and PLL to achieve the desired system clock frequency. Where applicable, The LM4F clock API uses the new RCC2 register to configure clock parameters.

Enables the main oscillator if the clock source is OSCSRC_MOSC. If the main oscillator was previously enabled, it will not be disabled. If desired, it can be separately disabled by a call to rcc_disable_main_osc().

Configures the system clock to run from the 400MHz PLL with a divisor of pll_div400 applied. If pll_div400 is 0, then the PLL is disabled, and the system clock is configured to run off a "raw" clock. If the PLL was previously powered on, it will not be disabled. If desired, it can de powered off by a call to rcc_pll_off().

Parameters

[in]	osc_src	Oscillator from where to derive the system clock.
[in]	xtal	Type of crystal connected to the OSCO/OSCI pins
[in]	pll_div400	The clock divisor to apply to the 400MHz PLL clock. If 0, then the PLL is disabled, and the system runs off a "raw" clock.

Returns: System clock frequency in Hz

Definition at line 443 of file rcc.c.

References lm4f_rcc_sysclk_freq, OSCSRC_30K_INT, OSCSRC_32K_EXT, OSCSRC_MOSC, OSCSRC_PIOSC, OSCSRC_PIOSC_D4, rcc_change_pll_divisor(), rcc_configure_xtal(), rcc_enable_main_osc(), rcc_enable_rcc2(), rcc_pll_bypass_enable(), rcc_pll_on(), rcc_set_osc_source(), and xtal_to_freq().

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◆ rcc_usb_pll_off()

void rcc_usb_pll_off ( void )

Power down the USB PLL.

Sets the USBPWRDN in SYSCTL_RCC2 to power down the USB PLL.

USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this function.

Definition at line 312 of file rcc.c.

References SYSCTL_RCC2, and SYSCTL_RCC2_USBPWRDN.

◆ rcc_usb_pll_on()

void rcc_usb_pll_on ( void )

Power up the USB PLL.

Clears the USBPWRDN in SYSCTL_RCC2 to power on the USB PLL.

USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this function.

Definition at line 325 of file rcc.c.

References SYSCTL_RCC2.

◆ rcc_wait_for_pll_ready()

void rcc_wait_for_pll_ready ( void )

Wait for main PLL to lock.

Waits until the LOCK bit in SYSCTL_PLLSTAT is set. This guarantees that the PLL is locked, and ready to use.

Definition at line 336 of file rcc.c.

References SYSCTL_PLLSTAT, and SYSCTL_PLLSTAT_LOCK.

Referenced by rcc_change_pll_divisor().

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Enumerations

Functions

Detailed Description

Enumeration Type Documentation

◆ osc_src

◆ pwm_clkdiv

◆ xtal_t

Function Documentation

◆ rcc_change_pll_divisor()

◆ rcc_configure_xtal()

◆ rcc_disable_interal_osc()

◆ rcc_disable_main_osc()

◆ rcc_enable_interal_osc()

◆ rcc_enable_main_osc()

◆ rcc_enable_rcc2()

◆ rcc_get_system_clock_frequency()

◆ rcc_pll_bypass_disable()

◆ rcc_pll_bypass_enable()

◆ rcc_pll_off()

◆ rcc_pll_on()

◆ rcc_set_osc_source()

◆ rcc_set_pll_divisor()

◆ rcc_set_pwm_divisor()

◆ rcc_sysclk_config()

◆ rcc_usb_pll_off()

◆ rcc_usb_pll_on()

◆ rcc_wait_for_pll_ready()