libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
clock.h
Go to the documentation of this file.
1/** @defgroup clock_defines Clock Defines
2
3@brief <b>Defined Constants and Types for the LPC17xx Clock</b>
4
5@ingroup LPC17xx_defines
6
7@version 1.0.0
8
9@author @htmlonly &copy; @endhtmlonly 2013 Silvio Gissi <silvio.gissi@outlook.com>
10
11@date 17 August 2013
12
13LGPL License Terms @ref lgpl_license
14 */
15/*
16 * This file is part of the libopencm3 project.
17 *
18 * Copyright (C) 2013 Silvio Gissi <silvio.gissi@outlook.com>
19 *
20 * This library is free software: you can redistribute it and/or modify
21 * it under the terms of the GNU Lesser General Public License as published by
22 * the Free Software Foundation, either version 3 of the License, or
23 * (at your option) any later version.
24 *
25 * This library is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU Lesser General Public License for more details.
29 *
30 * You should have received a copy of the GNU Lesser General Public License
31 * along with this library. If not, see <http://www.gnu.org/licenses/>.
32 */
33
34#ifndef LPC17XX_CLOCK_H
35#define LPC17XX_CLOCK_H
36
37#include <libopencm3/lpc17xx/memorymap.h>
38#include <libopencm3/cm3/common.h>
39
40/* --- Clock registers ----------------------------------------------------- */
41/* System Control and Status */
42#define CLK_SCS MMIO32(SYSCON_BASE + 0x1a0)
43/* Clock Source Selection */
44#define CLK_CLKSRCSEL MMIO32(SYSCON_BASE + 0x10c)
45/* PLL0: Main */
46#define CLK_PLL0CON MMIO32(SYSCON_BASE + 0x080)
47#define CLK_PLL0CFG MMIO32(SYSCON_BASE + 0x084)
48#define CLK_PLL0STAT MMIO32(SYSCON_BASE + 0x088)
49#define CLK_PLL0FEED MMIO32(SYSCON_BASE + 0x08c)
50/* PLL1: USB */
51#define CLK_PLL1CON MMIO32(SYSCON_BASE + 0x0a0)
52#define CLK_PLL1CFG MMIO32(SYSCON_BASE + 0x0a4)
53#define CLK_PLL1STAT MMIO32(SYSCON_BASE + 0x0a8)
54#define CLK_PLL1FEED MMIO32(SYSCON_BASE + 0x0ac)
55/* Clock Dividers */
56#define CLK_CCLKCFG MMIO32(SYSCON_BASE + 0x104)
57#define CLK_USBCLKCFG MMIO32(SYSCON_BASE + 0x108)
58#define CLK_PCLKSEL0 MMIO32(SYSCON_BASE + 0x1a8)
59#define CLK_PCLKSEL1 MMIO32(SYSCON_BASE + 0x1ac)
60/* Clock Output */
61#define CLK_CLKOUTCFG MMIO32(SYSCON_BASE + 0x1c8)
62
63/* CLK_SCS Values*/
64/* Reserved: [3:0] */
65#define CLK_SCS_OSCRANGE_01_TO_20MHZ (0)
66#define CLK_SCS_OSCRANGE_15_TO_25MHZ (1 << 4)
67#define CLK_SCS_OSCEN (1 << 5)
68#define CLK_SCS_OSCSTAT (1 << 6)
69/* Reserved: [31:7] */
70
71/* CLK_CLKSRCSEL Values*/
72#define CLK_CLKSRCSEL_IRC (0)
73#define CLK_CLKSRCSEL_MAIN (1 << 0)
74#define CLK_CLKSRCSEL_RTC (1 << 1)
75/* Reserved: value 11b */
76/* Reserved: [31:2] */
77
78/* CLK_PLL0CON and CLK_PLL1CON Values */
79#define CLK_PLLCON_ENABLE (1 << 0)
80#define CLK_PLLCON_CONNECT (1 << 1)
81/* Reserved: [31:2] */
82
83/* CLK_PLL0CFG and CLK_PLL0STAT Values */
84#define CLK_PLL0_MSEL_SHIFT 0
85#define CLK_PLL0_MSEL_MASK 0x7fff
86/* Reserved: [15] */
87#define CLK_PLL0_NSEL_SHIFT 16
88#define CLK_PLL0_NSEL_MASK 0xff
89/* CFG Reserved: [31:24] */
90#define CLK_PLL0STAT_ENABLE (1 << 24)
91#define CLK_PLL0STAT_CONNECT (1 << 25)
92#define CLK_PLL0STAT_PLOCK (1 << 26)
93/* STAT Reserved: [31:27] */
94
95/* CLK_PLL1CFG and CLK_PLL1STAT Values */
96#define CLK_PLL1_MSEL_SHIFT 0
97#define CLK_PLL1_MSEL_MASK 0x1f
98#define CLK_PLL1_PSEL_SHIFT 5
99#define CLK_PLL1_PSEL_MASK 0x3
100/* CFG Reserved: [31:7] */
101#define CLK_PLL1STAT_ENABLE (1 << 8)
102#define CLK_PLL1STAT_CONNECT (1 << 9)
103#define CLK_PLL1STAT_PLOCK (1 << 10)
104/* STAT Reserved: [31:11] */
105
106/* CLK_USBCLKCFG Values */
107#define CLK_USBCLKCFG_DIV6 0x5
108#define CLK_USBCLKCFG_DIV8 0x7
109#define CLK_USBCLKCFG_DIV10 0x9
110
111/* CLK_PCLKSEL0 and CLK_PCLKSEL1 Values */
112#define CLK_PCLKSEL_DIV4 0x00
113#define CLK_PCLKSEL_DIV1 0x01
114#define CLK_PCLKSEL_DIV2 0x02
115#define CLK_PCLKSEL_DIV8 0x03
116#define CLK_PCLKSEL0_WDT_SHIFT 0
117#define CLK_PCLKSEL0_TIMER0_SHIFT 2
118#define CLK_PCLKSEL0_TIMER1_SHIFT 4
119#define CLK_PCLKSEL0_UART0_SHIFT 6
120#define CLK_PCLKSEL0_UART1_SHIFT 8
121/* Reserved: [11:10]*/
122#define CLK_PCLKSEL0_PWM1_SHIFT 12
123#define CLK_PCLKSEL0_I2C0_SHIFT 14
124#define CLK_PCLKSEL0_SPI_SHIFT 16
125/* Reserved: [19:18]*/
126#define CLK_PCLKSEL0_SSP1_SHIFT 20
127#define CLK_PCLKSEL0_DAC_SHIFT 22
128#define CLK_PCLKSEL0_ADC_SHIFT 24
129#define CLK_PCLKSEL0_CAN1_SHIFT 26
130#define CLK_PCLKSEL0_CAN2_SHIFT 28
131#define CLK_PCLKSEL0_ACF_SHIFT 30
132#define CLK_PCLKSEL1_QEI_SHIFT 0
133#define CLK_PCLKSEL1_GPIOINT_SHIFT 2
134#define CLK_PCLKSEL1_PCB_SHIFT 4
135#define CLK_PCLKSEL1_I2C1_SHIFT 6
136/* Reserved: [9:8]*/
137#define CLK_PCLKSEL1_SSP0_SHIFT 10
138#define CLK_PCLKSEL1_TIMER2_SHIFT 12
139#define CLK_PCLKSEL1_TIMER3_SHIFT 14
140#define CLK_PCLKSEL1_UART2_SHIFT 16
141#define CLK_PCLKSEL1_UART3_SHIFT 18
142#define CLK_PCLKSEL1_I2C2_SHIFT 20
143#define CLK_PCLKSEL1_I2S_SHIFT 22
144/* Reserved: [25:24]*/
145#define CLK_PCLKSEL1_RIT_SHIFT 26
146#define CLK_PCLKSEL1_SYSCON_SHIFT 28
147#define CLK_PCLKSEL1_MCPWM_SHIFT 30
148
149/* CLK_CLKOUTCFG Values */
150#define CLK_CLKOUTCFG_SEL_CPU 0x00
151#define CLK_CLKOUTCFG_SEL_MAIN 0x01
152#define CLK_CLKOUTCFG_SEL_IRC 0x02
153#define CLK_CLKOUTCFG_SEL_USB 0x03
154#define CLK_CLKOUTCFG_SEL_RTC 0x04
155#define CLK_CLKOUTCFG_DIV_SHIFT 4
156#define CLK_CLKOUTCFG_ENABLE (1 << 8)
157#define CLK_CLKOUTCFG_ACTIVITY (1 << 9)
158/* Reserved: [31:10]*/
159
160#endif