Memory map for the MSP432E4xx devices. More...
Macros | |
| #define | SYSCTL_BASE (0x400FE000U) |
| System Control Base Address. More... | |
| #define | HIB_BASE (0x400FC000U) |
| Hibernation Module Base Address. More... | |
| #define | FLASH_CTRL_BASE (0x400FD000U) |
| Flash Controller Base Address. More... | |
| #define | EEPROM_BASE (0x400AF000U) |
| EEPROM Controller Base Address. More... | |
| #define | DMA_BASE (0x400FF000U) |
| Micro Direct Memory Access Base Address. More... | |
| #define | AES_BASE (0x44036000U) |
| Advance Encryption Standard Accelerator Base Address. More... | |
| #define | ADC0_BASE (0x40038000U) |
| Analog-to-Digital Converter Base Address. More... | |
| #define | ADC1_BASE (0x40039000U) |
| #define | CAN0_BASE (0x40040000U) |
| Controller Area Network Base Address. More... | |
| #define | CAN1_BASE (0x40041000U) |
| #define | ACMP_BASE (0x4003C000U) |
| Analog Comparator Base Address. More... | |
| #define | CRC_BASE (0x44030000U) |
| Cyclical Redundancy Check Base Address. More... | |
| #define | DES_BASE (0x44038000U) |
| Data Encryption Standard Accelerator Base Address. More... | |
| #define | EMAC_BASE (0x400EC000U) |
| Ethernet Controller Base Address. More... | |
| #define | EPI0_BASE (0x400D0000U) |
| External Peripheral Interface Base Address. More... | |
| #define | GPIOA_APB_BASE (0x40004000U) |
| General-Purpose Input/Outputs Base Address. More... | |
| #define | GPIOB_APB_BASE (0x40005000U) |
| #define | GPIOC_APB_BASE (0x40006000U) |
| #define | GPIOD_APB_BASE (0x40007000U) |
| #define | GPIOE_APB_BASE (0x40024000U) |
| #define | GPIOF_APB_BASE (0x40025000U) |
| #define | GPIOG_APB_BASE (0x40026000U) |
| #define | GPIOH_APB_BASE (0x40027000U) |
| #define | GPIOJ_APB_BASE (0x4003D000U) |
| #define | GPIOA_BASE (0x40058000U) |
| General-Purpose Input/Outputs (AHB) Base Address. More... | |
| #define | GPIOB_BASE (0x40059000U) |
| #define | GPIOC_BASE (0x4005A000U) |
| #define | GPIOD_BASE (0x4005B000U) |
| #define | GPIOE_BASE (0x4005C000U) |
| #define | GPIOF_BASE (0x4005D000U) |
| #define | GPIOG_BASE (0x4005E000U) |
| #define | GPIOH_BASE (0x4005F000U) |
| #define | GPIOJ_BASE (0x40060000U) |
| #define | GPIOK_BASE (0x40061000U) |
| #define | GPIOL_BASE (0x40062000U) |
| #define | GPIOM_BASE (0x40063000U) |
| #define | GPION_BASE (0x40064000U) |
| #define | GPIOP_BASE (0x40065000U) |
| #define | GPIOQ_BASE (0x40066000U) |
| #define | TIM0_BASE (0x40030000U) |
| General-Purpose Timers Base Address. More... | |
| #define | TIM1_BASE (0x40031000U) |
| #define | TIM2_BASE (0x40032000U) |
| #define | TIM3_BASE (0x40033000U) |
| #define | TIM4_BASE (0x40034000U) |
| #define | TIM5_BASE (0x40035000U) |
| #define | TIM6_BASE (0x400E0000U) |
| #define | TIM7_BASE (0x400E1000U) |
| #define | I2C0_BASE (0x40020000U) |
| Inter-Integrated Circuit Base Address. More... | |
| #define | I2C1_BASE (0x40021000U) |
| #define | I2C2_BASE (0x40022000U) |
| #define | I2C3_BASE (0x40023000U) |
| #define | I2C4_BASE (0x400C0000U) |
| #define | I2C5_BASE (0x400C1000U) |
| #define | I2C6_BASE (0x400C2000U) |
| #define | I2C7_BASE (0x400C3000U) |
| #define | I2C8_BASE (0x400B8000U) |
| #define | I2C9_BASE (0x400B9000U) |
| #define | LCD_BASE (0x44050000U) |
| LCD Controller Base Address. More... | |
| #define | PWM0_BASE (0x40028000U) |
| Pulse Width Modulator Base Address. More... | |
| #define | ONEWIRE_BASE (0x400B6000U) |
| 1-Wire Master Module Base Address More... | |
| #define | SSI0_BASE (0x40008000U) |
| Quad Synchronous Serial Interface Base Address. More... | |
| #define | SSI1_BASE (0x40009000U) |
| #define | SSI2_BASE (0x4000A000U) |
| #define | SSI3_BASE (0x4000B000U) |
| #define | QEI0_BASE (0x4002C000U) |
| Quadrature Encoder Interface Base Address. More... | |
| #define | SHA_BASE (0x44034000U) |
| SHA/MD5 Accelerator Base Address. More... | |
| #define | UART0_BASE (0x4000C000U) |
| Universal Asynchronous Receiver/Transmitter Base Address. More... | |
| #define | UART1_BASE (0x4000D000U) |
| #define | UART2_BASE (0x4000E000U) |
| #define | UART3_BASE (0x4000F000U) |
| #define | UART4_BASE (0x40010000U) |
| #define | UART5_BASE (0x40011000U) |
| #define | UART6_BASE (0x40012000U) |
| #define | UART7_BASE (0x40013000U) |
| #define | USB_BASE (0x40050000U) |
| Universal Serial Bus Controller Base Address. More... | |
| #define | WDT0_BASE (0x40000000U) |
| Watchdog Timers Base Address. More... | |
| #define | WDT1_BASE (0x40001000U) |
Detailed Description
Memory map for the MSP432E4xx devices.
- Version
- 1.0.0
- Date
- 22 July 2018
LGPL License Terms libopencm3 License
Macro Definition Documentation
◆ ACMP_BASE
| #define ACMP_BASE (0x4003C000U) |
Analog Comparator Base Address.
Definition at line 70 of file msp432/e4/memorymap.h.
◆ ADC0_BASE
| #define ADC0_BASE (0x40038000U) |
Analog-to-Digital Converter Base Address.
Definition at line 62 of file msp432/e4/memorymap.h.
◆ ADC1_BASE
| #define ADC1_BASE (0x40039000U) |
Definition at line 63 of file msp432/e4/memorymap.h.
◆ AES_BASE
| #define AES_BASE (0x44036000U) |
Advance Encryption Standard Accelerator Base Address.
Definition at line 59 of file msp432/e4/memorymap.h.
◆ CAN0_BASE
| #define CAN0_BASE (0x40040000U) |
Controller Area Network Base Address.
Definition at line 66 of file msp432/e4/memorymap.h.
◆ CAN1_BASE
| #define CAN1_BASE (0x40041000U) |
Definition at line 67 of file msp432/e4/memorymap.h.
◆ CRC_BASE
| #define CRC_BASE (0x44030000U) |
Cyclical Redundancy Check Base Address.
Definition at line 73 of file msp432/e4/memorymap.h.
◆ DES_BASE
| #define DES_BASE (0x44038000U) |
Data Encryption Standard Accelerator Base Address.
Definition at line 76 of file msp432/e4/memorymap.h.
◆ DMA_BASE
| #define DMA_BASE (0x400FF000U) |
Micro Direct Memory Access Base Address.
Definition at line 56 of file msp432/e4/memorymap.h.
◆ EEPROM_BASE
| #define EEPROM_BASE (0x400AF000U) |
EEPROM Controller Base Address.
Definition at line 53 of file msp432/e4/memorymap.h.
◆ EMAC_BASE
| #define EMAC_BASE (0x400EC000U) |
Ethernet Controller Base Address.
Definition at line 79 of file msp432/e4/memorymap.h.
◆ EPI0_BASE
| #define EPI0_BASE (0x400D0000U) |
External Peripheral Interface Base Address.
Definition at line 82 of file msp432/e4/memorymap.h.
◆ FLASH_CTRL_BASE
| #define FLASH_CTRL_BASE (0x400FD000U) |
Flash Controller Base Address.
Definition at line 50 of file msp432/e4/memorymap.h.
◆ GPIOA_APB_BASE
| #define GPIOA_APB_BASE (0x40004000U) |
General-Purpose Input/Outputs Base Address.
Definition at line 85 of file msp432/e4/memorymap.h.
◆ GPIOA_BASE
| #define GPIOA_BASE (0x40058000U) |
General-Purpose Input/Outputs (AHB) Base Address.
Definition at line 96 of file msp432/e4/memorymap.h.
◆ GPIOB_APB_BASE
| #define GPIOB_APB_BASE (0x40005000U) |
Definition at line 86 of file msp432/e4/memorymap.h.
◆ GPIOB_BASE
| #define GPIOB_BASE (0x40059000U) |
Definition at line 97 of file msp432/e4/memorymap.h.
◆ GPIOC_APB_BASE
| #define GPIOC_APB_BASE (0x40006000U) |
Definition at line 87 of file msp432/e4/memorymap.h.
◆ GPIOC_BASE
| #define GPIOC_BASE (0x4005A000U) |
Definition at line 98 of file msp432/e4/memorymap.h.
◆ GPIOD_APB_BASE
| #define GPIOD_APB_BASE (0x40007000U) |
Definition at line 88 of file msp432/e4/memorymap.h.
◆ GPIOD_BASE
| #define GPIOD_BASE (0x4005B000U) |
Definition at line 99 of file msp432/e4/memorymap.h.
◆ GPIOE_APB_BASE
| #define GPIOE_APB_BASE (0x40024000U) |
Definition at line 89 of file msp432/e4/memorymap.h.
◆ GPIOE_BASE
| #define GPIOE_BASE (0x4005C000U) |
Definition at line 100 of file msp432/e4/memorymap.h.
◆ GPIOF_APB_BASE
| #define GPIOF_APB_BASE (0x40025000U) |
Definition at line 90 of file msp432/e4/memorymap.h.
◆ GPIOF_BASE
| #define GPIOF_BASE (0x4005D000U) |
Definition at line 101 of file msp432/e4/memorymap.h.
◆ GPIOG_APB_BASE
| #define GPIOG_APB_BASE (0x40026000U) |
Definition at line 91 of file msp432/e4/memorymap.h.
◆ GPIOG_BASE
| #define GPIOG_BASE (0x4005E000U) |
Definition at line 102 of file msp432/e4/memorymap.h.
◆ GPIOH_APB_BASE
| #define GPIOH_APB_BASE (0x40027000U) |
Definition at line 92 of file msp432/e4/memorymap.h.
◆ GPIOH_BASE
| #define GPIOH_BASE (0x4005F000U) |
Definition at line 103 of file msp432/e4/memorymap.h.
◆ GPIOJ_APB_BASE
| #define GPIOJ_APB_BASE (0x4003D000U) |
Definition at line 93 of file msp432/e4/memorymap.h.
◆ GPIOJ_BASE
| #define GPIOJ_BASE (0x40060000U) |
Definition at line 104 of file msp432/e4/memorymap.h.
◆ GPIOK_BASE
| #define GPIOK_BASE (0x40061000U) |
Definition at line 105 of file msp432/e4/memorymap.h.
◆ GPIOL_BASE
| #define GPIOL_BASE (0x40062000U) |
Definition at line 106 of file msp432/e4/memorymap.h.
◆ GPIOM_BASE
| #define GPIOM_BASE (0x40063000U) |
Definition at line 107 of file msp432/e4/memorymap.h.
◆ GPION_BASE
| #define GPION_BASE (0x40064000U) |
Definition at line 108 of file msp432/e4/memorymap.h.
◆ GPIOP_BASE
| #define GPIOP_BASE (0x40065000U) |
Definition at line 109 of file msp432/e4/memorymap.h.
◆ GPIOQ_BASE
| #define GPIOQ_BASE (0x40066000U) |
Definition at line 110 of file msp432/e4/memorymap.h.
◆ HIB_BASE
| #define HIB_BASE (0x400FC000U) |
Hibernation Module Base Address.
Definition at line 47 of file msp432/e4/memorymap.h.
◆ I2C0_BASE
| #define I2C0_BASE (0x40020000U) |
Inter-Integrated Circuit Base Address.
Definition at line 123 of file msp432/e4/memorymap.h.
◆ I2C1_BASE
| #define I2C1_BASE (0x40021000U) |
Definition at line 124 of file msp432/e4/memorymap.h.
◆ I2C2_BASE
| #define I2C2_BASE (0x40022000U) |
Definition at line 125 of file msp432/e4/memorymap.h.
◆ I2C3_BASE
| #define I2C3_BASE (0x40023000U) |
Definition at line 126 of file msp432/e4/memorymap.h.
◆ I2C4_BASE
| #define I2C4_BASE (0x400C0000U) |
Definition at line 127 of file msp432/e4/memorymap.h.
◆ I2C5_BASE
| #define I2C5_BASE (0x400C1000U) |
Definition at line 128 of file msp432/e4/memorymap.h.
◆ I2C6_BASE
| #define I2C6_BASE (0x400C2000U) |
Definition at line 129 of file msp432/e4/memorymap.h.
◆ I2C7_BASE
| #define I2C7_BASE (0x400C3000U) |
Definition at line 130 of file msp432/e4/memorymap.h.
◆ I2C8_BASE
| #define I2C8_BASE (0x400B8000U) |
Definition at line 131 of file msp432/e4/memorymap.h.
◆ I2C9_BASE
| #define I2C9_BASE (0x400B9000U) |
Definition at line 132 of file msp432/e4/memorymap.h.
◆ LCD_BASE
| #define LCD_BASE (0x44050000U) |
LCD Controller Base Address.
Definition at line 135 of file msp432/e4/memorymap.h.
◆ ONEWIRE_BASE
| #define ONEWIRE_BASE (0x400B6000U) |
1-Wire Master Module Base Address
Definition at line 141 of file msp432/e4/memorymap.h.
◆ PWM0_BASE
| #define PWM0_BASE (0x40028000U) |
Pulse Width Modulator Base Address.
Definition at line 138 of file msp432/e4/memorymap.h.
◆ QEI0_BASE
| #define QEI0_BASE (0x4002C000U) |
Quadrature Encoder Interface Base Address.
Definition at line 150 of file msp432/e4/memorymap.h.
◆ SHA_BASE
| #define SHA_BASE (0x44034000U) |
SHA/MD5 Accelerator Base Address.
Definition at line 153 of file msp432/e4/memorymap.h.
◆ SSI0_BASE
| #define SSI0_BASE (0x40008000U) |
Quad Synchronous Serial Interface Base Address.
Definition at line 144 of file msp432/e4/memorymap.h.
◆ SSI1_BASE
| #define SSI1_BASE (0x40009000U) |
Definition at line 145 of file msp432/e4/memorymap.h.
◆ SSI2_BASE
| #define SSI2_BASE (0x4000A000U) |
Definition at line 146 of file msp432/e4/memorymap.h.
◆ SSI3_BASE
| #define SSI3_BASE (0x4000B000U) |
Definition at line 147 of file msp432/e4/memorymap.h.
◆ SYSCTL_BASE
| #define SYSCTL_BASE (0x400FE000U) |
System Control Base Address.
Definition at line 44 of file msp432/e4/memorymap.h.
◆ TIM0_BASE
| #define TIM0_BASE (0x40030000U) |
General-Purpose Timers Base Address.
Definition at line 113 of file msp432/e4/memorymap.h.
◆ TIM1_BASE
| #define TIM1_BASE (0x40031000U) |
Definition at line 114 of file msp432/e4/memorymap.h.
◆ TIM2_BASE
| #define TIM2_BASE (0x40032000U) |
Definition at line 115 of file msp432/e4/memorymap.h.
◆ TIM3_BASE
| #define TIM3_BASE (0x40033000U) |
Definition at line 116 of file msp432/e4/memorymap.h.
◆ TIM4_BASE
| #define TIM4_BASE (0x40034000U) |
Definition at line 117 of file msp432/e4/memorymap.h.
◆ TIM5_BASE
| #define TIM5_BASE (0x40035000U) |
Definition at line 118 of file msp432/e4/memorymap.h.
◆ TIM6_BASE
| #define TIM6_BASE (0x400E0000U) |
Definition at line 119 of file msp432/e4/memorymap.h.
◆ TIM7_BASE
| #define TIM7_BASE (0x400E1000U) |
Definition at line 120 of file msp432/e4/memorymap.h.
◆ UART0_BASE
| #define UART0_BASE (0x4000C000U) |
Universal Asynchronous Receiver/Transmitter Base Address.
Definition at line 156 of file msp432/e4/memorymap.h.
◆ UART1_BASE
| #define UART1_BASE (0x4000D000U) |
Definition at line 157 of file msp432/e4/memorymap.h.
◆ UART2_BASE
| #define UART2_BASE (0x4000E000U) |
Definition at line 158 of file msp432/e4/memorymap.h.
◆ UART3_BASE
| #define UART3_BASE (0x4000F000U) |
Definition at line 159 of file msp432/e4/memorymap.h.
◆ UART4_BASE
| #define UART4_BASE (0x40010000U) |
Definition at line 160 of file msp432/e4/memorymap.h.
◆ UART5_BASE
| #define UART5_BASE (0x40011000U) |
Definition at line 161 of file msp432/e4/memorymap.h.
◆ UART6_BASE
| #define UART6_BASE (0x40012000U) |
Definition at line 162 of file msp432/e4/memorymap.h.
◆ UART7_BASE
| #define UART7_BASE (0x40013000U) |
Definition at line 163 of file msp432/e4/memorymap.h.
◆ USB_BASE
| #define USB_BASE (0x40050000U) |
Universal Serial Bus Controller Base Address.
Definition at line 166 of file msp432/e4/memorymap.h.
◆ WDT0_BASE
| #define WDT0_BASE (0x40000000U) |
Watchdog Timers Base Address.
Definition at line 169 of file msp432/e4/memorymap.h.
◆ WDT1_BASE
| #define WDT1_BASE (0x40001000U) |
Definition at line 170 of file msp432/e4/memorymap.h.
