libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
msp432/e4/memorymap.h
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1/** @defgroup msp432e4_memorymap MSP432E4xx Memory Map
2 *
3 * @ingroup MSP432E4xx_defines
4 *
5 * @brief Memory map for the MSP432E4xx devices
6 *
7 * @version 1.0.0
8 *
9 * @date 22 July 2018
10 *
11 * LGPL License Terms @ref lgpl_license
12 */
13
14/*
15 * This file is part of the libopencm3 project.
16 *
17 * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
18 * Copyright (C) 2018 Dmitry Rezvanov <dmitry.rezvanov@yandex.ru>
19 *
20 * This library is free software: you can redistribute it and/or modify
21 * it under the terms of the GNU Lesser General Public License as published by
22 * the Free Software Foundation, either version 3 of the License, or
23 * (at your option) any later version.
24 *
25 * This library is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU Lesser General Public License for more details.
29 *
30 * You should have received a copy of the GNU Lesser General Public License
31 * along with this library. If not, see <http://www.gnu.org/licenses/>.
32 */
33
34/**@{*/
35
36#ifndef MSP432E4_MEMORYMAP_H
37#define MSP432E4_MEMORYMAP_H
38
39#include <libopencm3/cm3/common.h>
40
41/* --- MSP432E4xx specific peripheral definitions --------------------------- */
42
43/** System Control Base Address */
44#define SYSCTL_BASE (0x400FE000U)
45
46/** Hibernation Module Base Address */
47#define HIB_BASE (0x400FC000U)
48
49/** Flash Controller Base Address */
50#define FLASH_CTRL_BASE (0x400FD000U)
51
52/** EEPROM Controller Base Address */
53#define EEPROM_BASE (0x400AF000U)
54
55/** Micro Direct Memory Access Base Address */
56#define DMA_BASE (0x400FF000U)
57
58/** Advance Encryption Standard Accelerator Base Address */
59#define AES_BASE (0x44036000U)
60
61/** Analog-to-Digital Converter Base Address */
62#define ADC0_BASE (0x40038000U)
63#define ADC1_BASE (0x40039000U)
64
65/** Controller Area Network Base Address */
66#define CAN0_BASE (0x40040000U)
67#define CAN1_BASE (0x40041000U)
68
69/** Analog Comparator Base Address */
70#define ACMP_BASE (0x4003C000U)
71
72/** Cyclical Redundancy Check Base Address */
73#define CRC_BASE (0x44030000U)
74
75/** Data Encryption Standard Accelerator Base Address */
76#define DES_BASE (0x44038000U)
77
78/** Ethernet Controller Base Address */
79#define EMAC_BASE (0x400EC000U)
80
81/** External Peripheral Interface Base Address */
82#define EPI0_BASE (0x400D0000U)
83
84/** General-Purpose Input/Outputs Base Address */
85#define GPIOA_APB_BASE (0x40004000U)
86#define GPIOB_APB_BASE (0x40005000U)
87#define GPIOC_APB_BASE (0x40006000U)
88#define GPIOD_APB_BASE (0x40007000U)
89#define GPIOE_APB_BASE (0x40024000U)
90#define GPIOF_APB_BASE (0x40025000U)
91#define GPIOG_APB_BASE (0x40026000U)
92#define GPIOH_APB_BASE (0x40027000U)
93#define GPIOJ_APB_BASE (0x4003D000U)
94
95/** General-Purpose Input/Outputs (AHB) Base Address */
96#define GPIOA_BASE (0x40058000U)
97#define GPIOB_BASE (0x40059000U)
98#define GPIOC_BASE (0x4005A000U)
99#define GPIOD_BASE (0x4005B000U)
100#define GPIOE_BASE (0x4005C000U)
101#define GPIOF_BASE (0x4005D000U)
102#define GPIOG_BASE (0x4005E000U)
103#define GPIOH_BASE (0x4005F000U)
104#define GPIOJ_BASE (0x40060000U)
105#define GPIOK_BASE (0x40061000U)
106#define GPIOL_BASE (0x40062000U)
107#define GPIOM_BASE (0x40063000U)
108#define GPION_BASE (0x40064000U)
109#define GPIOP_BASE (0x40065000U)
110#define GPIOQ_BASE (0x40066000U)
111
112/** General-Purpose Timers Base Address */
113#define TIM0_BASE (0x40030000U)
114#define TIM1_BASE (0x40031000U)
115#define TIM2_BASE (0x40032000U)
116#define TIM3_BASE (0x40033000U)
117#define TIM4_BASE (0x40034000U)
118#define TIM5_BASE (0x40035000U)
119#define TIM6_BASE (0x400E0000U)
120#define TIM7_BASE (0x400E1000U)
121
122/** Inter-Integrated Circuit Base Address */
123#define I2C0_BASE (0x40020000U)
124#define I2C1_BASE (0x40021000U)
125#define I2C2_BASE (0x40022000U)
126#define I2C3_BASE (0x40023000U)
127#define I2C4_BASE (0x400C0000U)
128#define I2C5_BASE (0x400C1000U)
129#define I2C6_BASE (0x400C2000U)
130#define I2C7_BASE (0x400C3000U)
131#define I2C8_BASE (0x400B8000U)
132#define I2C9_BASE (0x400B9000U)
133
134/** LCD Controller Base Address */
135#define LCD_BASE (0x44050000U)
136
137/** Pulse Width Modulator Base Address */
138#define PWM0_BASE (0x40028000U)
139
140/** 1-Wire Master Module Base Address */
141#define ONEWIRE_BASE (0x400B6000U)
142
143/** Quad Synchronous Serial Interface Base Address */
144#define SSI0_BASE (0x40008000U)
145#define SSI1_BASE (0x40009000U)
146#define SSI2_BASE (0x4000A000U)
147#define SSI3_BASE (0x4000B000U)
148
149/** Quadrature Encoder Interface Base Address */
150#define QEI0_BASE (0x4002C000U)
151
152/** SHA/MD5 Accelerator Base Address */
153#define SHA_BASE (0x44034000U)
154
155/** Universal Asynchronous Receiver/Transmitter Base Address */
156#define UART0_BASE (0x4000C000U)
157#define UART1_BASE (0x4000D000U)
158#define UART2_BASE (0x4000E000U)
159#define UART3_BASE (0x4000F000U)
160#define UART4_BASE (0x40010000U)
161#define UART5_BASE (0x40011000U)
162#define UART6_BASE (0x40012000U)
163#define UART7_BASE (0x40013000U)
164
165/** Universal Serial Bus Controller Base Address */
166#define USB_BASE (0x40050000U)
167
168/** Watchdog Timers Base Address */
169#define WDT0_BASE (0x40000000U)
170#define WDT1_BASE (0x40001000U)
171
172#endif /* MSP432E4_MEMORYMAP_H */
173
174/**@}*/