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#define | DAC_CR(dac) MMIO32((dac) + 0x00) |
| DAC control register (DAC_CR) More...
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#define | DAC_SWTRIGR(dac) MMIO32((dac) + 0x04) |
| DAC software trigger register (DAC_SWTRIGR) More...
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#define | DAC_DHR12R1(dac) MMIO32((dac) + 0x08) |
| DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) More...
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#define | DAC_DHR12L1(dac) MMIO32((dac) + 0x0C) |
| DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) More...
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#define | DAC_DHR8R1(dac) MMIO32((dac) + 0x10) |
| DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) More...
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#define | DAC_DHR12R2(dac) MMIO32((dac) + 0x14) |
| DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) More...
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#define | DAC_DHR12L2(dac) MMIO32((dac) + 0x18) |
| DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) More...
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#define | DAC_DHR8R2(dac) MMIO32((dac) + 0x1C) |
| DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) More...
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#define | DAC_DHR12RD(dac) MMIO32((dac) + 0x20) |
| Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) More...
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#define | DAC_DHR12LD(dac) MMIO32((dac) + 0x24) |
| DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) More...
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#define | DAC_DHR8RD(dac) MMIO32((dac) + 0x28) |
| DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) More...
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#define | DAC_DOR1(dac) MMIO32((dac) + 0x2C) |
| DAC channel1 data output register (DAC_DOR1) More...
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#define | DAC_DOR2(dac) MMIO32((dac) + 0x30) |
| DAC channel2 data output register (DAC_DOR2) More...
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#define | DAC_SR(dac) MMIO32((dac) + 0x34) |
| DAC status register. More...
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#define | DAC_CR_DMAUDRIE2 (1 << 29) |
| DMAUDRIE2: DAC channel2 DMA underrun interrupt enable. More...
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#define | DAC_CR_DMAEN2 (1 << 28) |
| DMAEN2: DAC channel2 DMA enable. More...
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#define | DAC_CR_MAMP2_SHIFT 24 |
| MAMP2[3:0]: DAC channel2 mask/amplitude selector field position. More...
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#define | DAC_CR_WAVEx_MASK 0x3 |
| Wave generation mode mask size. More...
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#define | DAC_CR_WAVE2_SHIFT 22 |
| WAVE2[1:0]: DAC channel2 wave generation mode. More...
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#define | DAC_CR_EN2 (1 << 16) |
| EN2: DAC channel2 enable. More...
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#define | DAC_CR_DMAUDRIE1 (1 << 13) |
| DMAUDRIE1: DAC channel1 DMA underrun interrupt enable. More...
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#define | DAC_CR_DMAEN1 (1 << 12) |
| DMAEN1: DAC channel1 DMA enable. More...
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#define | DAC_CR_MAMP1_SHIFT 8 |
| MAMP1[3:0]: DAC channel1 mask/amplitude selector field position. More...
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#define | DAC_CR_MAMPx_MASK 0xf |
| MAMP Mask/Amplitude selector field size. More...
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#define | DAC_CR_WAVE1_SHIFT 6 |
| WAVE1[1:0]: DAC channel1 wave generation mode. More...
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#define | DAC_CR_EN1 (1 << 0) |
| EN1: DAC channel1 enable. More...
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#define | DAC_SWTRIGR_SWTRIG2 (1 << 1) |
| SWTRIG2: DAC channel2 software trigger. More...
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#define | DAC_SWTRIGR_SWTRIG1 (1 << 0) |
| SWTRIG1: DAC channel1 software trigger. More...
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#define | DAC_DHR12R1_DACC1DHR_SHIFT 0 |
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#define | DAC_DHR12R1_DACC1DHR_MASK 0xFFF |
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#define | DAC_DHR12L1_DACC1DHR_SHIFT 4 |
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#define | DAC_DHR12L1_DACC1DHR_MASK 0xFFF |
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#define | DAC_DHR8R1_DACC1DHR_SHIFT 0 |
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#define | DAC_DHR8R1_DACC1DHR_MASK 0xFF |
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#define | DAC_DHR12R2_DACC2DHR_SHIFT 0 |
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#define | DAC_DHR12R2_DACC2DHR_MASK 0xFFF |
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#define | DAC_DHR12L2_DACC2DHR_SHIFT 4 |
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#define | DAC_DHR12L2_DACC2DHR_MASK 0xFFF |
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#define | DAC_DHR8R2_DACC2DHR_SHIFT 0 |
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#define | DAC_DHR8R2_DACC2DHR_MASK 0xFF |
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#define | DAC_DHR12RD_DACC2DHR_SHIFT 16 |
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#define | DAC_DHR12RD_DACC2DHR_MASK 0xFFF |
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#define | DAC_DHR12RD_DACC1DHR_SHIFT 0 |
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#define | DAC_DHR12RD_DACC1DHR_MSK 0xFFF |
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#define | DAC_DHR12LD_DACC2DHR_SHIFT 16 |
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#define | DAC_DHR12LD_DACC2DHR_MSK 0xFFF |
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#define | DAC_DHR12LD_DACC1DHR_SHIFT 0 |
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#define | DAC_DHR12LD_DACC1DHR_MSK 0xFFF |
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#define | DAC_DHR8RD_DACC2DHR_SHIFT 8 |
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#define | DAC_DHR8RD_DACC2DHR_MSK 0xFF |
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#define | DAC_DHR8RD_DACC1DHR_SHIFT 0 |
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#define | DAC_DHR8RD_DACC1DHR_MSK 0xFF |
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#define | DAC_DOR1_DACC1DOR_SHIFT 0 |
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#define | DAC_DOR1_DACC1DOR_MSK 0xFFF |
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#define | DAC_DOR2_DACC2DOR_SHIFT 0 |
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#define | DAC_DOR2_DACC2DOR_MSK 0xFFF |
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#define | DAC_SR_DMAUDR1 (1 << 13) |
| DAC channel 1 DMA underrun flag. More...
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#define | DAC_SR_DMAUDR2 (1 << 29) |
| DAC channel 2 DMA underrun flag. More...
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#define | DAC_CHANNEL1 (1 << 0) |
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#define | DAC_CHANNEL2 (1 << 1) |
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#define | DAC_CHANNEL_BOTH (DAC_CHANNEL1 | DAC_CHANNEL2) |
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