Collaboration diagram for ADC Injected Trigger Identifier for ADC1:

Macros
#define	ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
	Timer 1 Trigger Output. More...

#define	ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
	Timer 1 Trigger Output. More...

#define	ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
	Timer 1 Compare Output 4. More...

#define	ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
	Timer 1 Compare Output 4. More...

#define	ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12)
	Timer 2 Trigger Output. More...

#define	ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12)
	Timer 2 Compare Output 1. More...

#define	ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12)
	Timer 3 Compare Output 4. More...

#define	ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12)
	Timer 4 Trigger Output. More...

#define	ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12)
	External Interrupt 15. More...

#define	ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
	Injected Software Trigger. More...

#define	ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
	Injected Software Trigger. More...

Detailed Description

and ADC2

Macro Definition Documentation

◆ ADC_CR2_JEXTSEL_EXTI15

#define ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12)

External Interrupt 15.

Definition at line 221 of file f1/adc.h.

◆ ADC_CR2_JEXTSEL_JSWSTART [1/2]

#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */

Injected Software Trigger.

Definition at line 248 of file f1/adc.h.

◆ ADC_CR2_JEXTSEL_JSWSTART [2/2]

#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */

Injected Software Trigger.

Definition at line 248 of file f1/adc.h.

◆ ADC_CR2_JEXTSEL_TIM1_CC4 [1/2]

#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)

Timer 1 Compare Output 4.

Definition at line 236 of file f1/adc.h.

◆ ADC_CR2_JEXTSEL_TIM1_CC4 [2/2]

#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)

Timer 1 Compare Output 4.

Definition at line 236 of file f1/adc.h.

◆ ADC_CR2_JEXTSEL_TIM1_TRGO [1/2]

#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)

Timer 1 Trigger Output.

Definition at line 234 of file f1/adc.h.

◆ ADC_CR2_JEXTSEL_TIM1_TRGO [2/2]

#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)

Timer 1 Trigger Output.

Definition at line 234 of file f1/adc.h.

◆ ADC_CR2_JEXTSEL_TIM2_CC1

#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12)

Timer 2 Compare Output 1.

Definition at line 215 of file f1/adc.h.

◆ ADC_CR2_JEXTSEL_TIM2_TRGO

#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12)

Timer 2 Trigger Output.

Definition at line 213 of file f1/adc.h.

◆ ADC_CR2_JEXTSEL_TIM3_CC4

#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12)

Timer 3 Compare Output 4.

Definition at line 217 of file f1/adc.h.

◆ ADC_CR2_JEXTSEL_TIM4_TRGO

#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12)

Timer 4 Trigger Output.

Definition at line 219 of file f1/adc.h.

Macros