Defined Constants and Types for the STM32F1xx Analog to Digital Converters More...

Collaboration diagram for ADC Defines:

Modules
	ADC Mode Selection

	ADC Trigger Identifier for ADC1 and ADC2

	ADC Trigger Identifier for ADC3

	ADC Injected Trigger Identifier for ADC1
	and ADC2

	ADC Injected Trigger Identifier for ADC3

	ADC Sample Time Selection for All Channels

	ADC Channel Numbers

	ADC register base addresses

	ADC Status Register Flags

	ADC Number of channels in discontinuous mode.

	ADC watchdog channel

	ADC Number of channels in discontinuous injected mode

Macros
#define	ADC_JOFR1(block) MMIO32((block) + 0x14)

#define	ADC_JOFR2(block) MMIO32((block) + 0x18)

#define	ADC_JOFR3(block) MMIO32((block) + 0x1c)

#define	ADC_JOFR4(block) MMIO32((block) + 0x20)

#define	ADC_HTR(block) MMIO32((block) + 0x24)

#define	ADC_LTR(block) MMIO32((block) + 0x28)

#define	ADC_SQR1(block) MMIO32((block) + 0x2c)

#define	ADC_SQR2(block) MMIO32((block) + 0x30)

#define	ADC_SQR3(block) MMIO32((block) + 0x34)

#define	ADC_JSQR(block) MMIO32((block) + 0x38)

#define	ADC_JDR1(block) MMIO32((block) + 0x3c)

#define	ADC_JDR2(block) MMIO32((block) + 0x40)

#define	ADC_JDR3(block) MMIO32((block) + 0x44)

#define	ADC_JDR4(block) MMIO32((block) + 0x48)

#define	ADC_DR(block) MMIO32((block) + 0x4c)

#define	ADC_CR1_DUALMOD_MASK (0xF << 16)

#define	ADC_CR1_DUALMOD_SHIFT 16

#define	ADC_CR1_AWDCH_MAX 17

#define	ADC_CR2_TSVREFE (1 << 23)
	Temperature sensor and V_REFINT enable. More...

#define	ADC_CR2_SWSTART (1 << 22)
	Start conversion of regular channels. More...

#define	ADC_CR2_JSWSTART (1 << 21)
	Start conversion of injected channels. More...

#define	ADC_CR2_EXTTRIG (1 << 20)
	External trigger conversion mode for regular channels. More...

#define	ADC_CR2_EXTSEL_MASK (0x7 << 17)

#define	ADC_CR2_EXTSEL_SHIFT 17

#define	ADC_CR2_JEXTTRIG (1 << 15)

#define	ADC_CR2_JEXTSEL_MASK (0x7 << 12)

#define	ADC_CR2_JEXTSEL_SHIFT 12

#define	ADC_CR2_ALIGN_RIGHT (0 << 11)

#define	ADC_CR2_ALIGN_LEFT (1 << 11)

#define	ADC_CR2_ALIGN (1 << 11)

#define	ADC_CR2_DMA (1 << 8)

#define	ADC_CR2_RSTCAL (1 << 3)

#define	ADC_CR2_CAL (1 << 2)

#define	ADC_CR2_CONT (1 << 1)

#define	ADC_CR2_ADON (1 << 0)

#define	ADC_SMPR1_SMP17_LSB 21

#define	ADC_SMPR1_SMP16_LSB 18

#define	ADC_SMPR1_SMP15_LSB 15

#define	ADC_SMPR1_SMP14_LSB 12

#define	ADC_SMPR1_SMP13_LSB 9

#define	ADC_SMPR1_SMP12_LSB 6

#define	ADC_SMPR1_SMP11_LSB 3

#define	ADC_SMPR1_SMP10_LSB 0

#define	ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMPR1_SMP17_LSB)

#define	ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMPR1_SMP16_LSB)

#define	ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMPR1_SMP15_LSB)

#define	ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMPR1_SMP14_LSB)

#define	ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMPR1_SMP13_LSB)

#define	ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMPR1_SMP12_LSB)

#define	ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMPR1_SMP11_LSB)

#define	ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMPR1_SMP10_LSB)

#define	ADC_SMPR2_SMP9_LSB 27

#define	ADC_SMPR2_SMP8_LSB 24

#define	ADC_SMPR2_SMP7_LSB 21

#define	ADC_SMPR2_SMP6_LSB 18

#define	ADC_SMPR2_SMP5_LSB 15

#define	ADC_SMPR2_SMP4_LSB 12

#define	ADC_SMPR2_SMP3_LSB 9

#define	ADC_SMPR2_SMP2_LSB 6

#define	ADC_SMPR2_SMP1_LSB 3

#define	ADC_SMPR2_SMP0_LSB 0

#define	ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMPR2_SMP9_LSB)

#define	ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMPR2_SMP8_LSB)

#define	ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMPR2_SMP7_LSB)

#define	ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMPR2_SMP6_LSB)

#define	ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMPR2_SMP5_LSB)

#define	ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMPR2_SMP4_LSB)

#define	ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMPR2_SMP3_LSB)

#define	ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMPR2_SMP2_LSB)

#define	ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMPR2_SMP1_LSB)

#define	ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMPR2_SMP0_LSB)

#define	ADC_SQR_MAX_CHANNELS_REGULAR 16

#define	ADC_SQR1_SQ16_LSB 15

#define	ADC_SQR1_SQ15_LSB 10

#define	ADC_SQR1_SQ14_LSB 5

#define	ADC_SQR1_SQ13_LSB 0

#define	ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)

#define	ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB)

#define	ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB)

#define	ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB)

#define	ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB)

#define	ADC_SQR2_SQ12_LSB 25

#define	ADC_SQR2_SQ11_LSB 20

#define	ADC_SQR2_SQ10_LSB 15

#define	ADC_SQR2_SQ9_LSB 10

#define	ADC_SQR2_SQ8_LSB 5

#define	ADC_SQR2_SQ7_LSB 0

#define	ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB)

#define	ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB)

#define	ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB)

#define	ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB)

#define	ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB)

#define	ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB)

#define	ADC_SQR3_SQ6_LSB 25

#define	ADC_SQR3_SQ5_LSB 20

#define	ADC_SQR3_SQ4_LSB 15

#define	ADC_SQR3_SQ3_LSB 10

#define	ADC_SQR3_SQ2_LSB 5

#define	ADC_SQR3_SQ1_LSB 0

#define	ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB)

#define	ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB)

#define	ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB)

#define	ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB)

#define	ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB)

#define	ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB)

#define	ADC_JDATA_LSB 0

#define	ADC_DATA_LSB 0

#define	ADC_ADC2DATA_LSB 16 /* ADC1 only (dual mode) */

#define	ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB)

#define	ADC_DATA_MSK (0xffff << ADC_DA)

#define	ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB)

#define	ADC_SR(block) MMIO32((block) + 0x00)

#define	ADC_CR1(block) MMIO32((block) + 0x04)

#define	ADC_CR2(block) MMIO32((block) + 0x08)

#define	ADC_SMPR1(block) MMIO32((block) + 0x0c)

#define	ADC_SMPR2(block) MMIO32((block) + 0x10)

#define	ADC1_SR ADC_SR(ADC1)

#define	ADC1_CR1 ADC_CR1(ADC1)

#define	ADC1_CR2 ADC_CR2(ADC1)

#define	ADC1_SMPR1 ADC_SMPR1(ADC1)

#define	ADC1_SMPR2 ADC_SMPR2(ADC1)

#define	ADC1_JOFR1 ADC_JOFR1(ADC1)

#define	ADC1_JOFR2 ADC_JOFR2(ADC1)

#define	ADC1_JOFR3 ADC_JOFR3(ADC1)

#define	ADC1_JOFR4 ADC_JOFR4(ADC1)

#define	ADC1_HTR ADC_HTR(ADC1)

#define	ADC1_LTR ADC_LTR(ADC1)

#define	ADC1_SQR1 ADC_SQR1(ADC1)

#define	ADC1_SQR2 ADC_SQR2(ADC1)

#define	ADC1_SQR3 ADC_SQR3(ADC1)

#define	ADC1_JSQR ADC_JSQR(ADC1)

#define	ADC1_JDR1 ADC_JDR1(ADC1)

#define	ADC1_JDR2 ADC_JDR2(ADC1)

#define	ADC1_JDR3 ADC_JDR3(ADC1)

#define	ADC1_JDR4 ADC_JDR4(ADC1)

#define	ADC1_DR ADC_DR(ADC1)

#define	ADC_CHANNEL_MASK 0x1F

#define	ADC_CR1_AWDEN (1 << 23)

#define	ADC_CR1_JAWDEN (1 << 22)

#define	ADC_CR1_DISCNUM_MASK (0x7 << 13)

#define	ADC_CR1_DISCNUM_SHIFT 13

#define	ADC_CR1_JDISCEN (1 << 12)
	Discontinuous mode on injected channels. More...

#define	ADC_CR1_DISCEN (1 << 11)
	Discontinuous mode on regular channels. More...

#define	ADC_CR1_JAUTO (1 << 10)
	Automatic Injection Group conversion. More...

#define	ADC_CR1_AWDSGL (1 << 9)
	Enable the watchdog on a single channel in scan mode. More...

#define	ADC_CR1_SCAN (1 << 8)
	Scan mode. More...

#define	ADC_CR1_JEOCIE (1 << 7)
	Interrupt enable for injected channels. More...

#define	ADC_CR1_AWDIE (1 << 6)
	Analog watchdog interrupt enable. More...

#define	ADC_CR1_EOCIE (1 << 5)
	Interrupt enable EOC. More...

#define	ADC_CR1_AWDCH_MASK (0x1F << 0)

#define	ADC_CR1_AWDCH_SHIFT 0

#define	ADC_CR2_ALIGN_RIGHT (0 << 11)

#define	ADC_CR2_ALIGN_LEFT (1 << 11)

#define	ADC_CR2_ALIGN (1 << 11)

#define	ADC_CR2_DMA (1 << 8)

#define	ADC_CR2_CONT (1 << 1)

#define	ADC_CR2_ADON (1 << 0)

#define	ADC_JOFFSET_LSB 0

#define	ADC_JOFFSET_MSK 0xfff

#define	ADC_HT_LSB 0

#define	ADC_HT_MSK 0xfff

#define	ADC_LT_LSB 0

#define	ADC_LT_MSK 0xfff

#define	ADC_SQR1_L_LSB 20

#define	ADC_JSQR_JL_LSB 20

#define	ADC_JSQR_JSQ4_LSB 15

#define	ADC_JSQR_JSQ3_LSB 10

#define	ADC_JSQR_JSQ2_LSB 5

#define	ADC_JSQR_JSQ1_LSB 0

#define	ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB)

#define	ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB)

#define	ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB)

#define	ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)

#define	ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)

#define	ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 5))

#define	ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_LSB)

Functions
void	adc_start_conversion_direct (uint32_t adc)
	ADC Start a Conversion Without Trigger. More...

void	adc_set_dual_mode (uint32_t mode)
	ADC Set Dual A/D Mode. More...

void	adc_enable_temperature_sensor (void)
	ADC Enable The Temperature Sensor. More...

void	adc_disable_temperature_sensor (void)
	ADC Disable The Temperature Sensor. More...

void	adc_enable_external_trigger_regular (uint32_t adc, uint32_t trigger)
	ADC Enable an External Trigger for Regular Channels. More...

void	adc_enable_external_trigger_injected (uint32_t adc, uint32_t trigger)
	ADC Enable an External Trigger for Injected Channels. More...

void	adc_reset_calibration (uint32_t adc)
	ADC Initialize Calibration Registers. More...

void	adc_calibration (uint32_t adc) LIBOPENCM3_DEPRECATED("see adc_calibrate/_async")
	ADC Calibration. More...

void	adc_calibrate_async (uint32_t adc)
	Start the ADC calibration and immediately return. More...

bool	adc_is_calibrating (uint32_t adc)
	Is the ADC Calibrating? More...

void	adc_calibrate (uint32_t adc)
	Start ADC calibration and wait for it to finish. More...

void	adc_power_on (uint32_t adc)
	ADC Power On. More...

void	adc_power_off (uint32_t adc)
	ADC Off. More...

void	adc_enable_analog_watchdog_regular (uint32_t adc)
	ADC Enable Analog Watchdog for Regular Conversions. More...

void	adc_disable_analog_watchdog_regular (uint32_t adc)
	ADC Disable Analog Watchdog for Regular Conversions. More...

void	adc_enable_analog_watchdog_injected (uint32_t adc)
	ADC Enable Analog Watchdog for Injected Conversions. More...

void	adc_disable_analog_watchdog_injected (uint32_t adc)
	ADC Disable Analog Watchdog for Injected Conversions. More...

void	adc_enable_discontinuous_mode_regular (uint32_t adc, uint8_t length)
	ADC Enable Discontinuous Mode for Regular Conversions. More...

void	adc_disable_discontinuous_mode_regular (uint32_t adc)
	ADC Disable Discontinuous Mode for Regular Conversions. More...

void	adc_enable_discontinuous_mode_injected (uint32_t adc)
	ADC Enable Discontinuous Mode for Injected Conversions. More...

void	adc_disable_discontinuous_mode_injected (uint32_t adc)
	ADC Disable Discontinuous Mode for Injected Conversions. More...

void	adc_enable_automatic_injected_group_conversion (uint32_t adc)
	ADC Enable Automatic Injected Conversions. More...

void	adc_disable_automatic_injected_group_conversion (uint32_t adc)
	ADC Disable Automatic Injected Conversions. More...

void	adc_enable_analog_watchdog_on_all_channels (uint32_t adc)
	ADC Enable Analog Watchdog for All Regular and/or Injected Channels. More...

void	adc_enable_analog_watchdog_on_selected_channel (uint32_t adc, uint8_t channel)
	ADC Enable Analog Watchdog for a Selected Channel. More...

void	adc_enable_scan_mode (uint32_t adc)
	ADC Set Scan Mode. More...

void	adc_disable_scan_mode (uint32_t adc)
	ADC Disable Scan Mode. More...

void	adc_enable_eoc_interrupt_injected (uint32_t adc)
	ADC Enable Injected End-Of-Conversion Interrupt. More...

void	adc_disable_eoc_interrupt_injected (uint32_t adc)
	ADC Disable Injected End-Of-Conversion Interrupt. More...

void	adc_enable_awd_interrupt (uint32_t adc)
	ADC Enable Analog Watchdog Interrupt. More...

void	adc_disable_awd_interrupt (uint32_t adc)
	ADC Disable Analog Watchdog Interrupt. More...

void	adc_enable_eoc_interrupt (uint32_t adc)
	ADC Enable Regular End-Of-Conversion Interrupt. More...

void	adc_disable_eoc_interrupt (uint32_t adc)
	ADC Disable Regular End-Of-Conversion Interrupt. More...

void	adc_set_left_aligned (uint32_t adc)
	ADC Set the Data as Left Aligned. More...

void	adc_set_right_aligned (uint32_t adc)
	ADC Set the Data as Right Aligned. More...

bool	adc_eoc (uint32_t adc)
	ADC Read the End-of-Conversion Flag. More...

bool	adc_eoc_injected (uint32_t adc)
	ADC Read the End-of-Conversion Flag for Injected Conversion. More...

uint32_t	adc_read_regular (uint32_t adc)
	ADC Read from the Regular Conversion Result Register. More...

uint32_t	adc_read_injected (uint32_t adc, uint8_t reg)
	ADC Read from an Injected Conversion Result Register. More...

void	adc_set_continuous_conversion_mode (uint32_t adc)
	ADC Enable Continuous Conversion Mode. More...

void	adc_set_single_conversion_mode (uint32_t adc)
	ADC Enable Single Conversion Mode. More...

void	adc_set_regular_sequence (uint32_t adc, uint8_t length, uint8_t channel[])
	ADC Set a Regular Channel Conversion Sequence. More...

void	adc_set_injected_sequence (uint32_t adc, uint8_t length, uint8_t channel[])
	ADC Set an Injected Channel Conversion Sequence. More...

void	adc_set_injected_offset (uint32_t adc, uint8_t reg, uint32_t offset)
	ADC Set the Injected Channel Data Offset. More...

void	adc_set_watchdog_high_threshold (uint32_t adc, uint16_t threshold)
	ADC Set Analog Watchdog Upper Threshold. More...

void	adc_set_watchdog_low_threshold (uint32_t adc, uint16_t threshold)
	ADC Set Analog Watchdog Lower Threshold. More...

void	adc_start_conversion_regular (uint32_t adc)
	ADC Software Triggered Conversion on Regular Channels. More...

void	adc_start_conversion_injected (uint32_t adc)
	ADC Software Triggered Conversion on Injected Channels. More...

void	adc_enable_dma (uint32_t adc)
	ADC Enable DMA Transfers. More...

void	adc_disable_dma (uint32_t adc)
	ADC Disable DMA Transfers. More...

bool	adc_get_flag (uint32_t adc, uint32_t flag)
	Read a Status Flag. More...

void	adc_clear_flag (uint32_t adc, uint32_t flag)
	Clear a Status Flag. More...

void	adc_set_sample_time (uint32_t adc, uint8_t channel, uint8_t time)
	ADC Set the Sample Time for a Single Channel. More...

void	adc_set_sample_time_on_all_channels (uint32_t adc, uint8_t time)
	ADC Set the Sample Time for All Channels. More...

void	adc_disable_external_trigger_regular (uint32_t adc)
	ADC Disable an External Trigger for Regular Channels. More...

void	adc_disable_external_trigger_injected (uint32_t adc)
	ADC Disable an External Trigger for Injected Channels. More...

Detailed Description

Defined Constants and Types for the STM32F1xx Analog to Digital Converters

Version: 1.0.0

Author: © 2009 Edward Cheeseman evbui.nosp@m.lder.nosp@m.@user.nosp@m.s.so.nosp@m.urcef.nosp@m.orge.nosp@m..net

Date: 18 August 2012

LGPL License Terms libopencm3 License

Author: © 2014 Karl Palsson karlp.nosp@m.@twe.nosp@m.ak.ne.nosp@m.t.au

Macro Definition Documentation

◆ ADC1_CR1

#define ADC1_CR1 ADC_CR1(ADC1)

Definition at line 67 of file adc_common_v1.h.

◆ ADC1_CR2

#define ADC1_CR2 ADC_CR2(ADC1)

Definition at line 68 of file adc_common_v1.h.

◆ ADC1_DR

#define ADC1_DR ADC_DR(ADC1)

Definition at line 89 of file adc_common_v1.h.

◆ ADC1_HTR

#define ADC1_HTR ADC_HTR(ADC1)

Definition at line 77 of file adc_common_v1.h.

◆ ADC1_JDR1

#define ADC1_JDR1 ADC_JDR1(ADC1)

Definition at line 85 of file adc_common_v1.h.

◆ ADC1_JDR2

#define ADC1_JDR2 ADC_JDR2(ADC1)

Definition at line 86 of file adc_common_v1.h.

◆ ADC1_JDR3

#define ADC1_JDR3 ADC_JDR3(ADC1)

Definition at line 87 of file adc_common_v1.h.

◆ ADC1_JDR4

#define ADC1_JDR4 ADC_JDR4(ADC1)

Definition at line 88 of file adc_common_v1.h.

◆ ADC1_JOFR1

#define ADC1_JOFR1 ADC_JOFR1(ADC1)

Definition at line 72 of file adc_common_v1.h.

◆ ADC1_JOFR2

#define ADC1_JOFR2 ADC_JOFR2(ADC1)

Definition at line 73 of file adc_common_v1.h.

◆ ADC1_JOFR3

#define ADC1_JOFR3 ADC_JOFR3(ADC1)

Definition at line 74 of file adc_common_v1.h.

◆ ADC1_JOFR4

#define ADC1_JOFR4 ADC_JOFR4(ADC1)

Definition at line 75 of file adc_common_v1.h.

◆ ADC1_JSQR

#define ADC1_JSQR ADC_JSQR(ADC1)

Definition at line 83 of file adc_common_v1.h.

◆ ADC1_LTR

#define ADC1_LTR ADC_LTR(ADC1)

Definition at line 78 of file adc_common_v1.h.

◆ ADC1_SMPR1

#define ADC1_SMPR1 ADC_SMPR1(ADC1)

Definition at line 69 of file adc_common_v1.h.

◆ ADC1_SMPR2

#define ADC1_SMPR2 ADC_SMPR2(ADC1)

Definition at line 70 of file adc_common_v1.h.

◆ ADC1_SQR1

#define ADC1_SQR1 ADC_SQR1(ADC1)

Definition at line 80 of file adc_common_v1.h.

◆ ADC1_SQR2

#define ADC1_SQR2 ADC_SQR2(ADC1)

Definition at line 81 of file adc_common_v1.h.

◆ ADC1_SQR3

#define ADC1_SQR3 ADC_SQR3(ADC1)

Definition at line 82 of file adc_common_v1.h.

◆ ADC1_SR

#define ADC1_SR ADC_SR(ADC1)

Definition at line 66 of file adc_common_v1.h.

◆ ADC_ADC2DATA_LSB

#define ADC_ADC2DATA_LSB 16 /* ADC1 only (dual mode) */

Definition at line 390 of file f1/adc.h.

◆ ADC_ADC2DATA_MSK

#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB)

Definition at line 393 of file f1/adc.h.

◆ ADC_CHANNEL_MASK

#define ADC_CHANNEL_MASK 0x1F

Definition at line 184 of file adc_common_v1.h.

◆ ADC_CR1

#define ADC_CR1 ( block ) MMIO32((block) + 0x04)

Definition at line 55 of file adc_common_v1.h.

◆ ADC_CR1_AWDCH_MASK

#define ADC_CR1_AWDCH_MASK (0x1F << 0)

Definition at line 292 of file adc_common_v1.h.

◆ ADC_CR1_AWDCH_MAX

#define ADC_CR1_AWDCH_MAX 17

Definition at line 126 of file f1/adc.h.

◆ ADC_CR1_AWDCH_SHIFT

#define ADC_CR1_AWDCH_SHIFT 0

Definition at line 293 of file adc_common_v1.h.

◆ ADC_CR1_AWDEN

#define ADC_CR1_AWDEN (1 << 23)

Definition at line 213 of file adc_common_v1.h.

◆ ADC_CR1_AWDIE

#define ADC_CR1_AWDIE (1 << 6)

Analog watchdog interrupt enable.

Definition at line 258 of file adc_common_v1.h.

◆ ADC_CR1_AWDSGL

#define ADC_CR1_AWDSGL (1 << 9)

Enable the watchdog on a single channel in scan mode.

Definition at line 249 of file adc_common_v1.h.

◆ ADC_CR1_DISCEN

#define ADC_CR1_DISCEN (1 << 11)

Discontinuous mode on regular channels.

Definition at line 243 of file adc_common_v1.h.

◆ ADC_CR1_DISCNUM_MASK

#define ADC_CR1_DISCNUM_MASK (0x7 << 13)

Definition at line 236 of file adc_common_v1.h.

◆ ADC_CR1_DISCNUM_SHIFT

#define ADC_CR1_DISCNUM_SHIFT 13

Definition at line 237 of file adc_common_v1.h.

◆ ADC_CR1_DUALMOD_MASK

#define ADC_CR1_DUALMOD_MASK (0xF << 16)

Definition at line 123 of file f1/adc.h.

◆ ADC_CR1_DUALMOD_SHIFT

#define ADC_CR1_DUALMOD_SHIFT 16

Definition at line 124 of file f1/adc.h.

◆ ADC_CR1_EOCIE

#define ADC_CR1_EOCIE (1 << 5)

Interrupt enable EOC.

Definition at line 261 of file adc_common_v1.h.

◆ ADC_CR1_JAUTO

#define ADC_CR1_JAUTO (1 << 10)

Automatic Injection Group conversion.

Definition at line 246 of file adc_common_v1.h.

◆ ADC_CR1_JAWDEN

#define ADC_CR1_JAWDEN (1 << 22)

Definition at line 216 of file adc_common_v1.h.

◆ ADC_CR1_JDISCEN

#define ADC_CR1_JDISCEN (1 << 12)

Discontinuous mode on injected channels.

Definition at line 240 of file adc_common_v1.h.

◆ ADC_CR1_JEOCIE

#define ADC_CR1_JEOCIE (1 << 7)

Interrupt enable for injected channels.

Definition at line 255 of file adc_common_v1.h.

◆ ADC_CR1_SCAN

#define ADC_CR1_SCAN (1 << 8)

Scan mode.

Definition at line 252 of file adc_common_v1.h.

◆ ADC_CR2

#define ADC_CR2 ( block ) MMIO32((block) + 0x08)

Definition at line 58 of file adc_common_v1.h.

◆ ADC_CR2_ADON [1/2]

#define ADC_CR2_ADON (1 << 0)

Definition at line 314 of file adc_common_v1.h.

◆ ADC_CR2_ADON [2/2]

#define ADC_CR2_ADON (1 << 0)

Definition at line 281 of file f1/adc.h.

◆ ADC_CR2_ALIGN [1/2]

#define ADC_CR2_ALIGN (1 << 11)

Definition at line 300 of file adc_common_v1.h.

◆ ADC_CR2_ALIGN [2/2]

#define ADC_CR2_ALIGN (1 << 11)

Definition at line 257 of file f1/adc.h.

◆ ADC_CR2_ALIGN_LEFT [1/2]

#define ADC_CR2_ALIGN_LEFT (1 << 11)

Definition at line 299 of file adc_common_v1.h.

◆ ADC_CR2_ALIGN_LEFT [2/2]

#define ADC_CR2_ALIGN_LEFT (1 << 11)

Definition at line 256 of file f1/adc.h.

◆ ADC_CR2_ALIGN_RIGHT [1/2]

#define ADC_CR2_ALIGN_RIGHT (0 << 11)

Definition at line 298 of file adc_common_v1.h.

◆ ADC_CR2_ALIGN_RIGHT [2/2]

#define ADC_CR2_ALIGN_RIGHT (0 << 11)

Definition at line 255 of file f1/adc.h.

◆ ADC_CR2_CAL

#define ADC_CR2_CAL (1 << 2)

Definition at line 270 of file f1/adc.h.

◆ ADC_CR2_CONT [1/2]

#define ADC_CR2_CONT (1 << 1)

Definition at line 306 of file adc_common_v1.h.

◆ ADC_CR2_CONT [2/2]

#define ADC_CR2_CONT (1 << 1)

Definition at line 273 of file f1/adc.h.

◆ ADC_CR2_DMA [1/2]

#define ADC_CR2_DMA (1 << 8)

Definition at line 303 of file adc_common_v1.h.

◆ ADC_CR2_DMA [2/2]

#define ADC_CR2_DMA (1 << 8)

Definition at line 262 of file f1/adc.h.

◆ ADC_CR2_EXTSEL_MASK

#define ADC_CR2_EXTSEL_MASK (0x7 << 17)

Definition at line 191 of file f1/adc.h.

◆ ADC_CR2_EXTSEL_SHIFT

#define ADC_CR2_EXTSEL_SHIFT 17

Definition at line 192 of file f1/adc.h.

◆ ADC_CR2_EXTTRIG

#define ADC_CR2_EXTTRIG (1 << 20)

External trigger conversion mode for regular channels.

Definition at line 140 of file f1/adc.h.

◆ ADC_CR2_JEXTSEL_MASK

#define ADC_CR2_JEXTSEL_MASK (0x7 << 12)

Definition at line 251 of file f1/adc.h.

◆ ADC_CR2_JEXTSEL_SHIFT

#define ADC_CR2_JEXTSEL_SHIFT 12

Definition at line 252 of file f1/adc.h.

◆ ADC_CR2_JEXTTRIG

#define ADC_CR2_JEXTTRIG (1 << 15)

Definition at line 197 of file f1/adc.h.

◆ ADC_CR2_JSWSTART

#define ADC_CR2_JSWSTART (1 << 21)

Start conversion of injected channels.

Definition at line 137 of file f1/adc.h.

◆ ADC_CR2_RSTCAL

#define ADC_CR2_RSTCAL (1 << 3)

Definition at line 267 of file f1/adc.h.

◆ ADC_CR2_SWSTART

#define ADC_CR2_SWSTART (1 << 22)

Start conversion of regular channels.

Definition at line 134 of file f1/adc.h.

◆ ADC_CR2_TSVREFE

#define ADC_CR2_TSVREFE (1 << 23)

Temperature sensor and V_REFINT enable.

(ADC1 only!)

Definition at line 131 of file f1/adc.h.

◆ ADC_DATA_LSB

#define ADC_DATA_LSB 0

Definition at line 389 of file f1/adc.h.

◆ ADC_DATA_MSK

#define ADC_DATA_MSK (0xffff << ADC_DA)

Definition at line 392 of file f1/adc.h.

◆ ADC_DR

#define ADC_DR ( block ) MMIO32((block) + 0x4c)

Definition at line 76 of file f1/adc.h.

◆ ADC_HT_LSB

#define ADC_HT_LSB 0

Definition at line 320 of file adc_common_v1.h.

◆ ADC_HT_MSK

#define ADC_HT_MSK 0xfff

Definition at line 321 of file adc_common_v1.h.

◆ ADC_HTR

#define ADC_HTR ( block ) MMIO32((block) + 0x24)

Definition at line 52 of file f1/adc.h.

◆ ADC_JDATA_LSB

#define ADC_JDATA_LSB 0

Definition at line 388 of file f1/adc.h.

◆ ADC_JDATA_MSK

#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB)

Definition at line 391 of file f1/adc.h.

◆ ADC_JDR1

#define ADC_JDR1 ( block ) MMIO32((block) + 0x3c)

Definition at line 70 of file f1/adc.h.

◆ ADC_JDR2

#define ADC_JDR2 ( block ) MMIO32((block) + 0x40)

Definition at line 71 of file f1/adc.h.

◆ ADC_JDR3

#define ADC_JDR3 ( block ) MMIO32((block) + 0x44)

Definition at line 72 of file f1/adc.h.

◆ ADC_JDR4

#define ADC_JDR4 ( block ) MMIO32((block) + 0x48)

Definition at line 73 of file f1/adc.h.

◆ ADC_JOFFSET_LSB

#define ADC_JOFFSET_LSB 0

Definition at line 318 of file adc_common_v1.h.

◆ ADC_JOFFSET_MSK

#define ADC_JOFFSET_MSK 0xfff

Definition at line 319 of file adc_common_v1.h.

◆ ADC_JOFR1

#define ADC_JOFR1 ( block ) MMIO32((block) + 0x14)

Definition at line 46 of file f1/adc.h.

◆ ADC_JOFR2

#define ADC_JOFR2 ( block ) MMIO32((block) + 0x18)

Definition at line 47 of file f1/adc.h.

◆ ADC_JOFR3

#define ADC_JOFR3 ( block ) MMIO32((block) + 0x1c)

Definition at line 48 of file f1/adc.h.

◆ ADC_JOFR4

#define ADC_JOFR4 ( block ) MMIO32((block) + 0x20)

Definition at line 49 of file f1/adc.h.

◆ ADC_JSQR

#define ADC_JSQR ( block ) MMIO32((block) + 0x38)

Definition at line 67 of file f1/adc.h.

◆ ADC_JSQR_JL_LSB

#define ADC_JSQR_JL_LSB 20

Definition at line 331 of file adc_common_v1.h.

◆ ADC_JSQR_JL_MSK

#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB)

Definition at line 348 of file adc_common_v1.h.

◆ ADC_JSQR_JL_VAL

#define ADC_JSQR_JL_VAL ( val ) (((val) - 1) << ADC_JSQR_JL_LSB)

Definition at line 355 of file adc_common_v1.h.

◆ ADC_JSQR_JSQ1_LSB

#define ADC_JSQR_JSQ1_LSB 0

Definition at line 335 of file adc_common_v1.h.

◆ ADC_JSQR_JSQ1_MSK

#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)

Definition at line 352 of file adc_common_v1.h.

◆ ADC_JSQR_JSQ2_LSB

#define ADC_JSQR_JSQ2_LSB 5

Definition at line 334 of file adc_common_v1.h.

◆ ADC_JSQR_JSQ2_MSK

#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)

Definition at line 351 of file adc_common_v1.h.

◆ ADC_JSQR_JSQ3_LSB

#define ADC_JSQR_JSQ3_LSB 10

Definition at line 333 of file adc_common_v1.h.

◆ ADC_JSQR_JSQ3_MSK

#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB)

Definition at line 350 of file adc_common_v1.h.

◆ ADC_JSQR_JSQ4_LSB

#define ADC_JSQR_JSQ4_LSB 15

Definition at line 332 of file adc_common_v1.h.

◆ ADC_JSQR_JSQ4_MSK

#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB)

Definition at line 349 of file adc_common_v1.h.

◆ ADC_JSQR_JSQ_VAL

#define ADC_JSQR_JSQ_VAL	(	n,
		val
	)	((val) << (((n) - 1) * 5))

Definition at line 354 of file adc_common_v1.h.

◆ ADC_LT_LSB

#define ADC_LT_LSB 0

Definition at line 322 of file adc_common_v1.h.

◆ ADC_LT_MSK

#define ADC_LT_MSK 0xfff

Definition at line 323 of file adc_common_v1.h.

◆ ADC_LTR

#define ADC_LTR ( block ) MMIO32((block) + 0x28)

Definition at line 55 of file f1/adc.h.

◆ ADC_SMPR1

#define ADC_SMPR1 ( block ) MMIO32((block) + 0x0c)

Definition at line 61 of file adc_common_v1.h.

◆ ADC_SMPR1_SMP10_LSB

#define ADC_SMPR1_SMP10_LSB 0

Definition at line 291 of file f1/adc.h.

◆ ADC_SMPR1_SMP10_MSK

#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMPR1_SMP10_LSB)

Definition at line 299 of file f1/adc.h.

◆ ADC_SMPR1_SMP11_LSB

#define ADC_SMPR1_SMP11_LSB 3

Definition at line 290 of file f1/adc.h.

◆ ADC_SMPR1_SMP11_MSK

#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMPR1_SMP11_LSB)

Definition at line 298 of file f1/adc.h.

◆ ADC_SMPR1_SMP12_LSB

#define ADC_SMPR1_SMP12_LSB 6

Definition at line 289 of file f1/adc.h.

◆ ADC_SMPR1_SMP12_MSK

#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMPR1_SMP12_LSB)

Definition at line 297 of file f1/adc.h.

◆ ADC_SMPR1_SMP13_LSB

#define ADC_SMPR1_SMP13_LSB 9

Definition at line 288 of file f1/adc.h.

◆ ADC_SMPR1_SMP13_MSK

#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMPR1_SMP13_LSB)

Definition at line 296 of file f1/adc.h.

◆ ADC_SMPR1_SMP14_LSB

#define ADC_SMPR1_SMP14_LSB 12

Definition at line 287 of file f1/adc.h.

◆ ADC_SMPR1_SMP14_MSK

#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMPR1_SMP14_LSB)

Definition at line 295 of file f1/adc.h.

◆ ADC_SMPR1_SMP15_LSB

#define ADC_SMPR1_SMP15_LSB 15

Definition at line 286 of file f1/adc.h.

◆ ADC_SMPR1_SMP15_MSK

#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMPR1_SMP15_LSB)

Definition at line 294 of file f1/adc.h.

◆ ADC_SMPR1_SMP16_LSB

#define ADC_SMPR1_SMP16_LSB 18

Definition at line 285 of file f1/adc.h.

◆ ADC_SMPR1_SMP16_MSK

#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMPR1_SMP16_LSB)

Definition at line 293 of file f1/adc.h.

◆ ADC_SMPR1_SMP17_LSB

#define ADC_SMPR1_SMP17_LSB 21

Definition at line 284 of file f1/adc.h.

◆ ADC_SMPR1_SMP17_MSK

#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMPR1_SMP17_LSB)

Definition at line 292 of file f1/adc.h.

◆ ADC_SMPR2

#define ADC_SMPR2 ( block ) MMIO32((block) + 0x10)

Definition at line 64 of file adc_common_v1.h.

◆ ADC_SMPR2_SMP0_LSB

#define ADC_SMPR2_SMP0_LSB 0

Definition at line 312 of file f1/adc.h.

◆ ADC_SMPR2_SMP0_MSK

#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMPR2_SMP0_LSB)

Definition at line 322 of file f1/adc.h.

◆ ADC_SMPR2_SMP1_LSB

#define ADC_SMPR2_SMP1_LSB 3

Definition at line 311 of file f1/adc.h.

◆ ADC_SMPR2_SMP1_MSK

#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMPR2_SMP1_LSB)

Definition at line 321 of file f1/adc.h.

◆ ADC_SMPR2_SMP2_LSB

#define ADC_SMPR2_SMP2_LSB 6

Definition at line 310 of file f1/adc.h.

◆ ADC_SMPR2_SMP2_MSK

#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMPR2_SMP2_LSB)

Definition at line 320 of file f1/adc.h.

◆ ADC_SMPR2_SMP3_LSB

#define ADC_SMPR2_SMP3_LSB 9

Definition at line 309 of file f1/adc.h.

◆ ADC_SMPR2_SMP3_MSK

#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMPR2_SMP3_LSB)

Definition at line 319 of file f1/adc.h.

◆ ADC_SMPR2_SMP4_LSB

#define ADC_SMPR2_SMP4_LSB 12

Definition at line 308 of file f1/adc.h.

◆ ADC_SMPR2_SMP4_MSK

#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMPR2_SMP4_LSB)

Definition at line 318 of file f1/adc.h.

◆ ADC_SMPR2_SMP5_LSB

#define ADC_SMPR2_SMP5_LSB 15

Definition at line 307 of file f1/adc.h.

◆ ADC_SMPR2_SMP5_MSK

#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMPR2_SMP5_LSB)

Definition at line 317 of file f1/adc.h.

◆ ADC_SMPR2_SMP6_LSB

#define ADC_SMPR2_SMP6_LSB 18

Definition at line 306 of file f1/adc.h.

◆ ADC_SMPR2_SMP6_MSK

#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMPR2_SMP6_LSB)

Definition at line 316 of file f1/adc.h.

◆ ADC_SMPR2_SMP7_LSB

#define ADC_SMPR2_SMP7_LSB 21

Definition at line 305 of file f1/adc.h.

◆ ADC_SMPR2_SMP7_MSK

#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMPR2_SMP7_LSB)

Definition at line 315 of file f1/adc.h.

◆ ADC_SMPR2_SMP8_LSB

#define ADC_SMPR2_SMP8_LSB 24

Definition at line 304 of file f1/adc.h.

◆ ADC_SMPR2_SMP8_MSK

#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMPR2_SMP8_LSB)

Definition at line 314 of file f1/adc.h.

◆ ADC_SMPR2_SMP9_LSB

#define ADC_SMPR2_SMP9_LSB 27

Definition at line 303 of file f1/adc.h.

◆ ADC_SMPR2_SMP9_MSK

#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMPR2_SMP9_LSB)

Definition at line 313 of file f1/adc.h.

◆ ADC_SQR1

#define ADC_SQR1 ( block ) MMIO32((block) + 0x2c)

Definition at line 58 of file f1/adc.h.

◆ ADC_SQR1_L_LSB

#define ADC_SQR1_L_LSB 20

Definition at line 328 of file adc_common_v1.h.

◆ ADC_SQR1_L_MSK

#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)

Definition at line 350 of file f1/adc.h.

◆ ADC_SQR1_SQ13_LSB

#define ADC_SQR1_SQ13_LSB 0

Definition at line 349 of file f1/adc.h.

◆ ADC_SQR1_SQ13_MSK

#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB)

Definition at line 354 of file f1/adc.h.

◆ ADC_SQR1_SQ14_LSB

#define ADC_SQR1_SQ14_LSB 5

Definition at line 348 of file f1/adc.h.

◆ ADC_SQR1_SQ14_MSK

#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB)

Definition at line 353 of file f1/adc.h.

◆ ADC_SQR1_SQ15_LSB

#define ADC_SQR1_SQ15_LSB 10

Definition at line 347 of file f1/adc.h.

◆ ADC_SQR1_SQ15_MSK

#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB)

Definition at line 352 of file f1/adc.h.

◆ ADC_SQR1_SQ16_LSB

#define ADC_SQR1_SQ16_LSB 15

Definition at line 346 of file f1/adc.h.

◆ ADC_SQR1_SQ16_MSK

#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB)

Definition at line 351 of file f1/adc.h.

◆ ADC_SQR2

#define ADC_SQR2 ( block ) MMIO32((block) + 0x30)

Definition at line 61 of file f1/adc.h.

◆ ADC_SQR2_SQ10_LSB

#define ADC_SQR2_SQ10_LSB 15

Definition at line 360 of file f1/adc.h.

◆ ADC_SQR2_SQ10_MSK

#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB)

Definition at line 366 of file f1/adc.h.

◆ ADC_SQR2_SQ11_LSB

#define ADC_SQR2_SQ11_LSB 20

Definition at line 359 of file f1/adc.h.

◆ ADC_SQR2_SQ11_MSK

#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB)

Definition at line 365 of file f1/adc.h.

◆ ADC_SQR2_SQ12_LSB

#define ADC_SQR2_SQ12_LSB 25

Definition at line 358 of file f1/adc.h.

◆ ADC_SQR2_SQ12_MSK

#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB)

Definition at line 364 of file f1/adc.h.

◆ ADC_SQR2_SQ7_LSB

#define ADC_SQR2_SQ7_LSB 0

Definition at line 363 of file f1/adc.h.

◆ ADC_SQR2_SQ7_MSK

#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB)

Definition at line 369 of file f1/adc.h.

◆ ADC_SQR2_SQ8_LSB

#define ADC_SQR2_SQ8_LSB 5

Definition at line 362 of file f1/adc.h.

◆ ADC_SQR2_SQ8_MSK

#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB)

Definition at line 368 of file f1/adc.h.

◆ ADC_SQR2_SQ9_LSB

#define ADC_SQR2_SQ9_LSB 10

Definition at line 361 of file f1/adc.h.

◆ ADC_SQR2_SQ9_MSK

#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB)

Definition at line 367 of file f1/adc.h.

◆ ADC_SQR3

#define ADC_SQR3 ( block ) MMIO32((block) + 0x34)

Definition at line 64 of file f1/adc.h.

◆ ADC_SQR3_SQ1_LSB

#define ADC_SQR3_SQ1_LSB 0

Definition at line 378 of file f1/adc.h.

◆ ADC_SQR3_SQ1_MSK

#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB)

Definition at line 384 of file f1/adc.h.

◆ ADC_SQR3_SQ2_LSB

#define ADC_SQR3_SQ2_LSB 5

Definition at line 377 of file f1/adc.h.

◆ ADC_SQR3_SQ2_MSK

#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB)

Definition at line 383 of file f1/adc.h.

◆ ADC_SQR3_SQ3_LSB

#define ADC_SQR3_SQ3_LSB 10

Definition at line 376 of file f1/adc.h.

◆ ADC_SQR3_SQ3_MSK

#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB)

Definition at line 382 of file f1/adc.h.

◆ ADC_SQR3_SQ4_LSB

#define ADC_SQR3_SQ4_LSB 15

Definition at line 375 of file f1/adc.h.

◆ ADC_SQR3_SQ4_MSK

#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB)

Definition at line 381 of file f1/adc.h.

◆ ADC_SQR3_SQ5_LSB

#define ADC_SQR3_SQ5_LSB 20

Definition at line 374 of file f1/adc.h.

◆ ADC_SQR3_SQ5_MSK

#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB)

Definition at line 380 of file f1/adc.h.

◆ ADC_SQR3_SQ6_LSB

#define ADC_SQR3_SQ6_LSB 25

Definition at line 373 of file f1/adc.h.

◆ ADC_SQR3_SQ6_MSK

#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB)

Definition at line 379 of file f1/adc.h.

◆ ADC_SQR_MAX_CHANNELS_REGULAR

#define ADC_SQR_MAX_CHANNELS_REGULAR 16

Definition at line 344 of file f1/adc.h.

◆ ADC_SR

#define ADC_SR ( block ) MMIO32((block) + 0x00)

Definition at line 52 of file adc_common_v1.h.

Function Documentation

◆ adc_calibrate()

void adc_calibrate ( uint32_t adc )

Start ADC calibration and wait for it to finish.

The ADC must have been powered down for at least 2 ADC clock cycles, then powered on before calibration starts

Parameters

adc	ADC Block register address base ADC register base addresses

Definition at line 374 of file adc.c.

References adc_calibrate_async(), and adc_is_calibrating().

Here is the call graph for this function:

◆ adc_calibrate_async()

void adc_calibrate_async ( uint32_t adc )

Start the ADC calibration and immediately return.

See also: adc_calibrate; adc_is_calibrate

Parameters

adc	ADC Block register address base ADC register base addresses

Definition at line 353 of file adc.c.

References ADC_CR2, and ADC_CR2_CAL.

Referenced by adc_calibrate().

Here is the caller graph for this function:

◆ adc_calibration()

void adc_calibration ( uint32_t adc )

ADC Calibration.

Deprecated:: replaced by adc_calibrate/_async/_is_calibrating The calibration data for the ADC is recomputed. The hardware clears the calibration status flag when calibration is complete. This function does not return until this happens and the ADC is ready for use.

The ADC must have been powered down for at least 2 ADC clock cycles, then powered on. before calibration starts

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses.

Definition at line 341 of file adc.c.

References ADC_CR2, and ADC_CR2_CAL.

◆ adc_clear_flag()

void adc_clear_flag	(	uint32_t	adc,
		uint32_t	flag
	)

Clear a Status Flag.

Parameters

[in]	adc	Unsigned int32. ADC register address base ADC register base addresses
[in]	flag	Unsigned int32. Status register flag ADC Status Register Flags.

Definition at line 771 of file adc_common_v1.c.

References ADC_SR.

◆ adc_disable_analog_watchdog_injected()

void adc_disable_analog_watchdog_injected ( uint32_t adc )

ADC Disable Analog Watchdog for Injected Conversions.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 161 of file adc_common_v1.c.

References ADC_CR1.

◆ adc_disable_analog_watchdog_regular()

void adc_disable_analog_watchdog_regular ( uint32_t adc )

ADC Disable Analog Watchdog for Regular Conversions.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses.

Definition at line 135 of file adc_common_v1.c.

References ADC_CR1.

◆ adc_disable_automatic_injected_group_conversion()

void adc_disable_automatic_injected_group_conversion ( uint32_t adc )

ADC Disable Automatic Injected Conversions.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 251 of file adc_common_v1.c.

References ADC_CR1.

◆ adc_disable_awd_interrupt()

void adc_disable_awd_interrupt ( uint32_t adc )

ADC Disable Analog Watchdog Interrupt.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 372 of file adc_common_v1.c.

References ADC_CR1.

◆ adc_disable_discontinuous_mode_injected()

void adc_disable_discontinuous_mode_injected ( uint32_t adc )

ADC Disable Discontinuous Mode for Injected Conversions.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 223 of file adc_common_v1.c.

References ADC_CR1.

◆ adc_disable_discontinuous_mode_regular()

void adc_disable_discontinuous_mode_regular ( uint32_t adc )

ADC Disable Discontinuous Mode for Regular Conversions.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 197 of file adc_common_v1.c.

References ADC_CR1.

◆ adc_disable_dma()

void adc_disable_dma ( uint32_t adc )

ADC Disable DMA Transfers.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 746 of file adc_common_v1.c.

References ADC_CR2.

◆ adc_disable_eoc_interrupt()

void adc_disable_eoc_interrupt ( uint32_t adc )

ADC Disable Regular End-Of-Conversion Interrupt.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 395 of file adc_common_v1.c.

References ADC_CR1.

◆ adc_disable_eoc_interrupt_injected()

void adc_disable_eoc_interrupt_injected ( uint32_t adc )

ADC Disable Injected End-Of-Conversion Interrupt.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 350 of file adc_common_v1.c.

References ADC_CR1.

◆ adc_disable_external_trigger_injected()

void adc_disable_external_trigger_injected ( uint32_t adc )

ADC Disable an External Trigger for Injected Channels.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses.

Definition at line 306 of file adc.c.

References ADC_CR2.

Referenced by adc_enable_automatic_injected_group_conversion().

Here is the caller graph for this function:

◆ adc_disable_external_trigger_regular()

void adc_disable_external_trigger_regular ( uint32_t adc )

ADC Disable an External Trigger for Regular Channels.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses.

Definition at line 252 of file adc.c.

References ADC_CR2.

◆ adc_disable_scan_mode()

void adc_disable_scan_mode ( uint32_t adc )

ADC Disable Scan Mode.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 328 of file adc_common_v1.c.

References ADC_CR1.

◆ adc_disable_temperature_sensor()

void adc_disable_temperature_sensor ( void )

ADC Disable The Temperature Sensor.

Disabling this will reduce power consumption from the sensor and the reference voltage measurements.

Definition at line 198 of file adc.c.

References ADC1, and ADC_CR2.

◆ adc_enable_analog_watchdog_injected()

void adc_enable_analog_watchdog_injected ( uint32_t adc )

ADC Enable Analog Watchdog for Injected Conversions.

The analog watchdog allows the monitoring of an analog signal between two threshold levels. The thresholds must be preset. Comparison is done before data alignment takes place, so the thresholds are left-aligned.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 150 of file adc_common_v1.c.

References ADC_CR1, and ADC_CR1_JAWDEN.

◆ adc_enable_analog_watchdog_on_all_channels()

void adc_enable_analog_watchdog_on_all_channels ( uint32_t adc )

ADC Enable Analog Watchdog for All Regular and/or Injected Channels.

The analog watchdog allows the monitoring of an analog signal between two threshold levels. The thresholds must be preset. Comparison is done before data alignment takes place, so the thresholds are left-aligned.

Note: The analog watchdog must be enabled for either or both of the regular or injected channels. If neither are enabled, the analog watchdog feature will be disabled. adc_enable_analog_watchdog_injected, adc_enable_analog_watchdog_regular.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 272 of file adc_common_v1.c.

References ADC_CR1.

◆ adc_enable_analog_watchdog_on_selected_channel()

void adc_enable_analog_watchdog_on_selected_channel	(	uint32_t	adc,
		uint8_t	channel
	)

ADC Enable Analog Watchdog for a Selected Channel.

The analog watchdog allows the monitoring of an analog signal between two threshold levels. The thresholds must be preset. Comparison is done before data alignment takes place, so the thresholds are left-aligned.

Note: The analog watchdog must be enabled for either or both of the regular or injected channels. If neither are enabled, the analog watchdog feature will be disabled. If both are enabled, the same channel number is monitored. adc_enable_analog_watchdog_injected, adc_enable_analog_watchdog_regular.

Parameters

[in]	adc	Unsigned int32. ADC block register address base ADC register base addresses
[in]	channel	Unsigned int8. ADC channel number ADC watchdog channel

Definition at line 294 of file adc_common_v1.c.

References ADC_CR1, ADC_CR1_AWDCH_MAX, and ADC_CR1_AWDSGL.

◆ adc_enable_analog_watchdog_regular()

void adc_enable_analog_watchdog_regular ( uint32_t adc )

ADC Enable Analog Watchdog for Regular Conversions.

The analog watchdog allows the monitoring of an analog signal between two threshold levels. The thresholds must be preset.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses.

Definition at line 123 of file adc_common_v1.c.

References ADC_CR1, and ADC_CR1_AWDEN.

◆ adc_enable_automatic_injected_group_conversion()

void adc_enable_automatic_injected_group_conversion ( uint32_t adc )

ADC Enable Automatic Injected Conversions.

The ADC converts a defined injected group of channels immediately after the regular channels have been converted. The external trigger on the injected channels is disabled as required.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 239 of file adc_common_v1.c.

References ADC_CR1, ADC_CR1_JAUTO, and adc_disable_external_trigger_injected().

Here is the call graph for this function:

◆ adc_enable_awd_interrupt()

void adc_enable_awd_interrupt ( uint32_t adc )

ADC Enable Analog Watchdog Interrupt.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 361 of file adc_common_v1.c.

References ADC_CR1, and ADC_CR1_AWDIE.

◆ adc_enable_discontinuous_mode_injected()

void adc_enable_discontinuous_mode_injected ( uint32_t adc )

ADC Enable Discontinuous Mode for Injected Conversions.

In this mode the ADC converts sequentially one channel of the defined group of injected channels, cycling back to the first channel in the group once the entire group has been converted.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 212 of file adc_common_v1.c.

References ADC_CR1, and ADC_CR1_JDISCEN.

◆ adc_enable_discontinuous_mode_regular()

void adc_enable_discontinuous_mode_regular	(	uint32_t	adc,
		uint8_t	length
	)

ADC Enable Discontinuous Mode for Regular Conversions.

In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the defined regular channel group. The subgroup is defined by the number of consecutive channels to be converted. After a subgroup has been converted the next trigger will start conversion of the immediately following subgroup of the same length or until the whole group has all been converted. When the the whole group has been converted, the next trigger will restart conversion of the subgroup at the beginning of the whole group.

Parameters

[in]	adc	Unsigned int32. ADC block register address base ADC register base addresses
[in]	length	Unsigned int8. Number of channels in the group ADC Number of channels in discontinuous mode.

Definition at line 182 of file adc_common_v1.c.

References ADC_CR1, ADC_CR1_DISCEN, and ADC_CR1_DISCNUM_SHIFT.

◆ adc_enable_dma()

void adc_enable_dma ( uint32_t adc )

ADC Enable DMA Transfers.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 735 of file adc_common_v1.c.

References ADC_CR2, and ADC_CR2_DMA.

◆ adc_enable_eoc_interrupt()

void adc_enable_eoc_interrupt ( uint32_t adc )

ADC Enable Regular End-Of-Conversion Interrupt.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 384 of file adc_common_v1.c.

References ADC_CR1, and ADC_CR1_EOCIE.

◆ adc_enable_eoc_interrupt_injected()

void adc_enable_eoc_interrupt_injected ( uint32_t adc )

ADC Enable Injected End-Of-Conversion Interrupt.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 339 of file adc_common_v1.c.

References ADC_CR1, and ADC_CR1_JEOCIE.

◆ adc_enable_external_trigger_injected()

void adc_enable_external_trigger_injected	(	uint32_t	adc,
		uint32_t	trigger
	)

ADC Enable an External Trigger for Injected Channels.

This enables an external trigger for set of defined injected channels.

For ADC1 and ADC2

Timer 1 TRGO event
Timer 1 CC4 event
Timer 2 TRGO event
Timer 2 CC1 event
Timer 3 CC4 event
Timer 4 TRGO event
EXTI (TIM8 CC4 is also possible on some devices, see datasheet)
Software Start

For ADC3

Timer 1 TRGO event
Timer 1 CC4 event
Timer 4 CC3 event
Timer 8 CC2 event
Timer 8 CC4 event
Timer 5 TRGO event
Timer 5 CC4 event
Software Start

Parameters

[in]	adc	Unsigned int32. ADC block register address base ADC register base addresses.
[in]	trigger	Unsigned int8. Trigger identifier ADC Injected Trigger Identifier for ADC1 for ADC1 and ADC2, or ADC Injected Trigger Identifier for ADC3 for ADC3.

Definition at line 288 of file adc.c.

References ADC_CR2, ADC_CR2_JEXTSEL_MASK, and ADC_CR2_JEXTTRIG.

◆ adc_enable_external_trigger_regular()

void adc_enable_external_trigger_regular	(	uint32_t	adc,
		uint32_t	trigger
	)

ADC Enable an External Trigger for Regular Channels.

This enables an external trigger for set of defined regular channels.

For ADC1 and ADC2

Timer 1 CC1 event
Timer 1 CC2 event
Timer 1 CC3 event
Timer 2 CC2 event
Timer 3 TRGO event
Timer 4 CC4 event
EXTI (TIM8_TRGO is also possible on some devices, see datasheet)
Software Start

For ADC3

Timer 3 CC1 event
Timer 2 CC3 event
Timer 1 CC3 event
Timer 8 CC1 event
Timer 8 TRGO event
Timer 5 CC1 event
Timer 5 CC3 event
Software Start

Parameters

[in]	adc	Unsigned int32. ADC block register address base ADC register base addresses.
[in]	trigger	Unsigned int8. Trigger identifier ADC Trigger Identifier for ADC1 and ADC2 for ADC1 and ADC2, or ADC Trigger Identifier for ADC3 for ADC3.

Definition at line 235 of file adc.c.

References ADC_CR2, ADC_CR2_EXTSEL_MASK, and ADC_CR2_EXTTRIG.

◆ adc_enable_scan_mode()

void adc_enable_scan_mode ( uint32_t adc )

ADC Set Scan Mode.

In this mode a conversion consists of a scan of the predefined set of channels, regular and injected, each channel conversion immediately following the previous one. It can use single, continuous or discontinuous mode.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 317 of file adc_common_v1.c.

References ADC_CR1, and ADC_CR1_SCAN.

◆ adc_enable_temperature_sensor()

void adc_enable_temperature_sensor ( void )

ADC Enable The Temperature Sensor.

This enables both the sensor and the reference voltage measurements on channels 16 and 17.

Definition at line 186 of file adc.c.

References ADC1, ADC_CR2, and ADC_CR2_TSVREFE.

◆ adc_eoc()

bool adc_eoc ( uint32_t adc )

ADC Read the End-of-Conversion Flag.

This flag is set after all channels of a regular or injected group have been converted.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Returns: bool. End of conversion flag.

Definition at line 435 of file adc_common_v1.c.

References ADC_SR, and ADC_SR_EOC.

◆ adc_eoc_injected()

bool adc_eoc_injected ( uint32_t adc )

ADC Read the End-of-Conversion Flag for Injected Conversion.

This flag is set after all channels of an injected group have been converted.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Returns: bool. End of conversion flag.

Definition at line 449 of file adc_common_v1.c.

References ADC_SR, and ADC_SR_JEOC.

◆ adc_get_flag()

bool adc_get_flag	(	uint32_t	adc,
		uint32_t	flag
	)

Read a Status Flag.

Parameters

[in]	adc	Unsigned int32. ADC register address base ADC register base addresses
[in]	flag	Unsigned int32. Status register flag ADC Status Register Flags.

Returns: boolean: flag set.

Definition at line 759 of file adc_common_v1.c.

References ADC_SR.

◆ adc_is_calibrating()

bool adc_is_calibrating ( uint32_t adc )

Is the ADC Calibrating?

Parameters

adc	ADC Block register address base ADC register base addresses

Returns: true if the adc is currently calibrating

Definition at line 363 of file adc.c.

References ADC_CR2, and ADC_CR2_CAL.

Referenced by adc_calibrate().

Here is the caller graph for this function:

◆ adc_power_off()

void adc_power_off ( uint32_t adc )

ADC Off.

Turn off the ADC to reduce power consumption to a few microamps.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses.

Definition at line 108 of file adc_common_v1.c.

References ADC_CR2.

◆ adc_power_on()

void adc_power_on ( uint32_t adc )

ADC Power On.

If the ADC is in power-down mode then it is powered up. The application needs to wait a time of about 3 microseconds for stabilization before using the ADC. If the ADC is already on this function call has no effect. NOTE Common with F37x

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 107 of file adc.c.

References ADC_CR2, and ADC_CR2_ADON.

◆ adc_read_injected()

uint32_t adc_read_injected	(	uint32_t	adc,
		uint8_t	reg
	)

ADC Read from an Injected Conversion Result Register.

The result read back from the selected injected result register (one of four) is 12 bits, right or left aligned within the first 16 bits. The result can have a negative value if the injected channel offset has been set

See also: adc_set_injected_offset.

Parameters

[in]	adc	Unsigned int32. ADC block register address base ADC register base addresses
[in]	reg	Unsigned int8. Register number (1 ... 4).

Returns: Unsigned int32 conversion result.

Definition at line 483 of file adc_common_v1.c.

References ADC_JDR1, ADC_JDR2, ADC_JDR3, and ADC_JDR4.

◆ adc_read_regular()

uint32_t adc_read_regular ( uint32_t adc )

ADC Read from the Regular Conversion Result Register.

The result read back is 12 bits, right or left aligned within the first 16 bits. For ADC1 only, the higher 16 bits will hold the result from ADC2 if an appropriate dual mode has been set

See also: adc_set_dual_mode.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Returns: Unsigned int32 conversion result.

Definition at line 465 of file adc_common_v1.c.

References ADC_DR.

◆ adc_reset_calibration()

void adc_reset_calibration ( uint32_t adc )

ADC Initialize Calibration Registers.

This resets the calibration registers. It is not clear if this is required to be done before every calibration operation.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses.

Definition at line 321 of file adc.c.

References ADC_CR2, and ADC_CR2_RSTCAL.

◆ adc_set_continuous_conversion_mode()

void adc_set_continuous_conversion_mode ( uint32_t adc )

ADC Enable Continuous Conversion Mode.

In this mode the ADC starts a new conversion of a single channel or a channel group immediately following completion of the previous channel group conversion.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 507 of file adc_common_v1.c.

References ADC_CR2, and ADC_CR2_CONT.

◆ adc_set_dual_mode()

void adc_set_dual_mode ( uint32_t mode )

ADC Set Dual A/D Mode.

The dual mode uses ADC1 as master and ADC2 in a slave arrangement. This setting is applied to ADC1 only. Start of conversion when triggered can cause simultaneous conversion with ADC2, or alternate conversion. Regular and injected conversions can be configured, each one being separately simultaneous or alternate.

Fast interleaved mode starts ADC1 immediately on trigger, and ADC2 seven clock cycles later.

Slow interleaved mode starts ADC1 immediately on trigger, and ADC2 fourteen clock cycles later, followed by ADC1 fourteen cycles later again. This can only be used on a single channel.

Alternate trigger mode must occur on an injected channel group, and alternates between the ADCs on each trigger.

Note that sampling must not overlap between ADCs on the same channel.

Dual A/D converter modes possible:

IND: Independent mode.
CRSISM: Combined regular simultaneous + injected simultaneous mode.
CRSATM: Combined regular simultaneous + alternate trigger mode.
CISFIM: Combined injected simultaneous + fast interleaved mode.
CISSIM: Combined injected simultaneous + slow interleaved mode.
ISM: Injected simultaneous mode only.
RSM: Regular simultaneous mode only.
FIM: Fast interleaved mode only.
SIM: Slow interleaved mode only.
ATM: Alternate trigger mode only.

Parameters

[in] mode Unsigned int32. Dual mode selection from ADC Mode Selection

Definition at line 171 of file adc.c.

References ADC1_CR1.

◆ adc_set_injected_offset()

void adc_set_injected_offset	(	uint32_t	adc,
		uint8_t	reg,
		uint32_t	offset
	)

ADC Set the Injected Channel Data Offset.

This value is subtracted from the injected channel results after conversion is complete, and can result in negative results. A separate value can be specified for each injected data register.

Parameters

[in]	adc	Unsigned int32. ADC block register address base ADC register base addresses
[in]	reg	Unsigned int8. Register number (1 ... 4).
[in]	offset	Unsigned int32.

Definition at line 662 of file adc_common_v1.c.

References ADC_JOFR1, ADC_JOFR2, ADC_JOFR3, and ADC_JOFR4.

◆ adc_set_injected_sequence()

void adc_set_injected_sequence	(	uint32_t	adc,
		uint8_t	length,
		uint8_t	channel[]
	)

ADC Set an Injected Channel Conversion Sequence.

Defines a sequence of channels to be converted as an injected group with a length from 1 to 4 channels. If this is called during conversion, the current conversion is reset and conversion begins again with the newly defined group.

Parameters

[in]	adc	Unsigned int32. ADC block register address base ADC register base addresses
[in]	length	Unsigned int8. Number of channels in the group.
[in]	channel	Unsigned int8[]. Set of channels in sequence, integers 0..18

Definition at line 630 of file adc_common_v1.c.

References ADC_JSQR, ADC_JSQR_JL_VAL, and ADC_JSQR_JSQ_VAL.

◆ adc_set_left_aligned()

void adc_set_left_aligned ( uint32_t adc )

ADC Set the Data as Left Aligned.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses.

Definition at line 408 of file adc_common_v1.c.

References ADC_CR2, and ADC_CR2_ALIGN.

◆ adc_set_regular_sequence()

void adc_set_regular_sequence	(	uint32_t	adc,
		uint8_t	length,
		uint8_t	channel[]
	)

ADC Set a Regular Channel Conversion Sequence.

Define a sequence of channels to be converted as a regular group with a length from 1 to ADC_REGULAR_SEQUENCE_MAX channels. If this is called during conversion, the current conversion is reset and conversion begins again with the newly defined group.

Parameters

[in]	adc	Unsigned int32. ADC block base address ADC register base addresses.
[in]	length	Unsigned int8. Number of channels in the group.
[in]	channel	Unsigned int8[]. Set of channels in sequence, integers 0..31.

Definition at line 574 of file adc_common_v1.c.

References ADC_SQR1, ADC_SQR1_L_LSB, ADC_SQR2, ADC_SQR3, and ADC_SQR_MAX_CHANNELS_REGULAR.

◆ adc_set_right_aligned()

void adc_set_right_aligned ( uint32_t adc )

ADC Set the Data as Right Aligned.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses.

Definition at line 420 of file adc_common_v1.c.

References ADC_CR2.

◆ adc_set_sample_time()

void adc_set_sample_time	(	uint32_t	adc,
		uint8_t	channel,
		uint8_t	time
	)

ADC Set the Sample Time for a Single Channel.

The sampling time can be selected in ADC clock cycles from 1.5 to 239.5.

Parameters

[in]	adc	Unsigned int32. ADC block register address base ADC register base addresses.
[in]	channel	Unsigned int8. ADC Channel integer 0..18 or from ADC Channel Numbers.
[in]	time	Unsigned int8. Sampling time selection from ADC Sample Time Selection for All Channels. NOTE Common with f2 and f37x and f4

Definition at line 394 of file adc.c.

References ADC_SMPR1, and ADC_SMPR2.

◆ adc_set_sample_time_on_all_channels()

void adc_set_sample_time_on_all_channels	(	uint32_t	adc,
		uint8_t	time
	)

ADC Set the Sample Time for All Channels.

The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same for all channels.

Parameters

[in]	adc	Unsigned int32. ADC block register address base ADC register base addresses.
[in]	time	Unsigned int8. Sampling time selection from ADC Sample Time Selection for All Channels. NOTE Common with f2 and f37x and f4

Definition at line 423 of file adc.c.

References ADC_SMPR1, and ADC_SMPR2.

◆ adc_set_single_conversion_mode()

void adc_set_single_conversion_mode ( uint32_t adc )

ADC Enable Single Conversion Mode.

In this mode the ADC performs a conversion of one channel or a channel group and stops.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses.

Definition at line 523 of file adc_common_v1.c.

References ADC_CR2.

◆ adc_set_watchdog_high_threshold()

void adc_set_watchdog_high_threshold	(	uint32_t	adc,
		uint16_t	threshold
	)

ADC Set Analog Watchdog Upper Threshold.

Parameters

[in]	adc	Unsigned int32. ADC block register address base ADC register base addresses
[in]	threshold	Upper threshold value, 12bit right aligned.

Definition at line 535 of file adc_common_v1.c.

References ADC_HT_MSK, and ADC_HTR.

◆ adc_set_watchdog_low_threshold()

void adc_set_watchdog_low_threshold	(	uint32_t	adc,
		uint16_t	threshold
	)

ADC Set Analog Watchdog Lower Threshold.

Parameters

[in]	adc	Unsigned int32. ADC block register address base ADC register base addresses
[in]	threshold	Lower threshold value, 12bit right aligned.

Definition at line 551 of file adc_common_v1.c.

References ADC_LT_MSK, and ADC_LTR.

◆ adc_start_conversion_direct()

void adc_start_conversion_direct ( uint32_t adc )

ADC Start a Conversion Without Trigger.

This initiates a conversion by software without a trigger. The ADC needs to be powered on before this is called, otherwise this function has no effect.

Note that this is not available in other STM32F families. To ensure code compatibility, enable triggering and use a software trigger source

See also: adc_start_conversion_regular.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 127 of file adc.c.

References ADC_CR2, and ADC_CR2_ADON.

◆ adc_start_conversion_injected()

void adc_start_conversion_injected ( uint32_t adc )

ADC Software Triggered Conversion on Injected Channels.

This starts conversion on a set of defined injected channels if the ADC trigger is set to be a software trigger. It is cleared by hardware once conversion starts.

Special F1 Note this is a software trigger and requires triggering to be enabled and the trigger source to be set appropriately otherwise conversion will not start. This is not the same as the ADC start conversion operation.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses.

Definition at line 719 of file adc_common_v1.c.

References ADC_CR2, and ADC_CR2_JSWSTART.

◆ adc_start_conversion_regular()

void adc_start_conversion_regular ( uint32_t adc )

ADC Software Triggered Conversion on Regular Channels.

This starts conversion on a set of defined regular channels if the ADC trigger is set to be a software trigger. It is cleared by hardware once conversion starts.

Special F1 Note this is a software trigger and requires triggering to be enabled and the trigger source to be set appropriately otherwise conversion will not start. This is not the same as the ADC start conversion operation.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses.

Definition at line 695 of file adc_common_v1.c.

References ADC_CR2, and ADC_CR2_SWSTART.

Modules

Macros

Functions

Detailed Description

Macro Definition Documentation

◆ ADC1_CR1

◆ ADC1_CR2

◆ ADC1_DR

◆ ADC1_HTR

◆ ADC1_JDR1

◆ ADC1_JDR2

◆ ADC1_JDR3

◆ ADC1_JDR4

◆ ADC1_JOFR1

◆ ADC1_JOFR2

◆ ADC1_JOFR3

◆ ADC1_JOFR4

◆ ADC1_JSQR

◆ ADC1_LTR

◆ ADC1_SMPR1

◆ ADC1_SMPR2

◆ ADC1_SQR1

◆ ADC1_SQR2

◆ ADC1_SQR3

◆ ADC1_SR

◆ ADC_ADC2DATA_LSB

◆ ADC_ADC2DATA_MSK

◆ ADC_CHANNEL_MASK

◆ ADC_CR1

◆ ADC_CR1_AWDCH_MASK

◆ ADC_CR1_AWDCH_MAX

◆ ADC_CR1_AWDCH_SHIFT

◆ ADC_CR1_AWDEN

◆ ADC_CR1_AWDIE

◆ ADC_CR1_AWDSGL

◆ ADC_CR1_DISCEN

◆ ADC_CR1_DISCNUM_MASK

◆ ADC_CR1_DISCNUM_SHIFT

◆ ADC_CR1_DUALMOD_MASK

◆ ADC_CR1_DUALMOD_SHIFT

◆ ADC_CR1_EOCIE

◆ ADC_CR1_JAUTO

◆ ADC_CR1_JAWDEN

◆ ADC_CR1_JDISCEN

◆ ADC_CR1_JEOCIE

◆ ADC_CR1_SCAN

◆ ADC_CR2

◆ ADC_CR2_ADON [1/2]

◆ ADC_CR2_ADON [2/2]

◆ ADC_CR2_ALIGN [1/2]

◆ ADC_CR2_ALIGN [2/2]

◆ ADC_CR2_ALIGN_LEFT [1/2]

◆ ADC_CR2_ALIGN_LEFT [2/2]

◆ ADC_CR2_ALIGN_RIGHT [1/2]

◆ ADC_CR2_ALIGN_RIGHT [2/2]

◆ ADC_CR2_CAL

◆ ADC_CR2_CONT [1/2]

◆ ADC_CR2_CONT [2/2]

◆ ADC_CR2_DMA [1/2]

◆ ADC_CR2_DMA [2/2]

◆ ADC_CR2_EXTSEL_MASK

◆ ADC_CR2_EXTSEL_SHIFT

◆ ADC_CR2_EXTTRIG

◆ ADC_CR2_JEXTSEL_MASK

◆ ADC_CR2_JEXTSEL_SHIFT

◆ ADC_CR2_JEXTTRIG

◆ ADC_CR2_JSWSTART

◆ ADC_CR2_RSTCAL

◆ ADC_CR2_SWSTART

◆ ADC_CR2_TSVREFE

◆ ADC_DATA_LSB

◆ ADC_DATA_MSK

◆ ADC_DR

◆ ADC_HT_LSB

◆ ADC_HT_MSK

◆ ADC_HTR

◆ ADC_JDATA_LSB

◆ ADC_JDATA_MSK

◆ ADC_JDR1

◆ ADC_JDR2