NVIC Registers

Collaboration diagram for NVIC Registers:

Macros
#define	NVIC_ISER(iser_id)
	ISER: Interrupt Set Enable Registers. More...
#define	NVIC_ICER(icer_id)
	ICER: Interrupt Clear Enable Registers. More...
#define	NVIC_ISPR(ispr_id)
	ISPR: Interrupt Set Pending Registers. More...
#define	NVIC_ICPR(icpr_id)
	ICPR: Interrupt Clear Pending Registers. More...
#define	NVIC_IABR(iabr_id)
	IABR: Interrupt Active Bit Register. More...
#define	NVIC_IPR(ipr_id)
	IPR: Interrupt Priority Registers. More...
#define	NVIC_STIR   MMIO32(STIR_BASE)
	STIR: Software Trigger Interrupt Register. More...

Detailed Description

Macro Definition Documentation

NVIC_IABR

#define NVIC_IABR

(

iabr_id

)

Value:

                                                MMIO32(NVIC_BASE + 0x200 + \
                                                ((iabr_id) * 4))

IABR: Interrupt Active Bit Register.

Note

8 32bit Registers

Definition at line 87 of file cm3/nvic.h.

NVIC_ICER

#define NVIC_ICER

(

icer_id

)

Value:

                                                MMIO32(NVIC_BASE + 0x80 + \
                                                ((icer_id) * 4))

ICER: Interrupt Clear Enable Registers.

Note

8 32bit Registers

Single register on CM0

Definition at line 60 of file cm3/nvic.h.

NVIC_ICPR

#define NVIC_ICPR

(

icpr_id

)

Value:

                                                MMIO32(NVIC_BASE + 0x180 + \
                                                ((icpr_id) * 4))

ICPR: Interrupt Clear Pending Registers.

Note

8 32bit Registers

Single register on CM0

Definition at line 78 of file cm3/nvic.h.

NVIC_IPR

#define NVIC_IPR

(

ipr_id

)

Value:

                                                MMIO8(NVIC_BASE + 0x300 + \
                                                (ipr_id))

IPR: Interrupt Priority Registers.

Note

240 8bit Registers

32 8bit Registers on CM0, requires word access

Definition at line 101 of file cm3/nvic.h.

NVIC_ISER

#define NVIC_ISER

(

iser_id

)

Value:

                                                MMIO32(NVIC_BASE + 0x00 + \
                                                ((iser_id) * 4))

ISER: Interrupt Set Enable Registers.

Note

8 32bit Registers

Single register on CM0

Definition at line 51 of file cm3/nvic.h.

NVIC_ISPR

#define NVIC_ISPR

(

ispr_id

)

Value:

                                                MMIO32(NVIC_BASE + 0x100 + \
                                                ((ispr_id) * 4))

ISPR: Interrupt Set Pending Registers.

Note

8 32bit Registers

Single register on CM0

Definition at line 69 of file cm3/nvic.h.

NVIC_STIR

#define NVIC_STIR   MMIO32(STIR_BASE)

STIR: Software Trigger Interrupt Register.

Definition at line 107 of file cm3/nvic.h.