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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */ |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */ |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2 |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3 |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4 |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5 |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6 |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7 |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8 /* (XX) */ |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9 /* (XX) */ |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa /* (XX) */ |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */ |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */ |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */ |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */ |
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