libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.

Defined Constants and Types for the STM32F2xx Reset and Clock Control More...

Collaboration diagram for RCC Defines:

Data Structures

struct  rcc_clock_scale
 

Modules

 RCC_CFGR APBx prescale factors
 These can be used for both APB1 and APB2 prescaling.
 
 RCC_CFGR AHB prescale factors
 
 RCC_CFGR Deprecated dividers
 Older compatible definitions to ease migration.
 
 RCC_AHBxRSTR reset values (full set)
 
 RCC_APB1RSTR reset values
 
 RCC_APB2RSTR reset values
 
 RCC_AHBxENR enable values (full set)
 
 RCC_APB1ENR enable values
 
 RCC_APB2ENR enable values
 

Macros

#define RCC_CR   MMIO32(RCC_BASE + 0x00)
 
#define RCC_PLLCFGR   MMIO32(RCC_BASE + 0x04)
 
#define RCC_CFGR   MMIO32(RCC_BASE + 0x08)
 
#define RCC_CIR   MMIO32(RCC_BASE + 0x0c)
 
#define RCC_AHB1RSTR   MMIO32(RCC_BASE + 0x10)
 
#define RCC_AHB2RSTR   MMIO32(RCC_BASE + 0x14)
 
#define RCC_AHB3RSTR   MMIO32(RCC_BASE + 0x18)
 
#define RCC_APB1RSTR   MMIO32(RCC_BASE + 0x20)
 
#define RCC_APB2RSTR   MMIO32(RCC_BASE + 0x24)
 
#define RCC_AHB1ENR   MMIO32(RCC_BASE + 0x30)
 
#define RCC_AHB2ENR   MMIO32(RCC_BASE + 0x34)
 
#define RCC_AHB3ENR   MMIO32(RCC_BASE + 0x38)
 
#define RCC_APB1ENR   MMIO32(RCC_BASE + 0x40)
 
#define RCC_APB2ENR   MMIO32(RCC_BASE + 0x44)
 
#define RCC_AHB1LPENR   MMIO32(RCC_BASE + 0x50)
 
#define RCC_AHB2LPENR   MMIO32(RCC_BASE + 0x54)
 
#define RCC_AHB3LPENR   MMIO32(RCC_BASE + 0x58)
 
#define RCC_APB1LPENR   MMIO32(RCC_BASE + 0x60)
 
#define RCC_APB2LPENR   MMIO32(RCC_BASE + 0x64)
 
#define RCC_BDCR   MMIO32(RCC_BASE + 0x70)
 
#define RCC_CSR   MMIO32(RCC_BASE + 0x74)
 
#define RCC_SSCGR   MMIO32(RCC_BASE + 0x80)
 
#define RCC_PLLI2SCFGR   MMIO32(RCC_BASE + 0x84)
 
#define RCC_CR_PLLI2SRDY   (1 << 27)
 
#define RCC_CR_PLLI2SON   (1 << 26)
 
#define RCC_CR_PLLRDY   (1 << 25)
 
#define RCC_CR_PLLON   (1 << 24)
 
#define RCC_CR_CSSON   (1 << 19)
 
#define RCC_CR_HSEBYP   (1 << 18)
 
#define RCC_CR_HSERDY   (1 << 17)
 
#define RCC_CR_HSEON   (1 << 16)
 
#define RCC_CR_HSIRDY   (1 << 1)
 
#define RCC_CR_HSION   (1 << 0)
 
#define RCC_PLLCFGR_PLLQ_SHIFT   24
 
#define RCC_PLLCFGR_PLLSRC   (1 << 22)
 
#define RCC_PLLCFGR_PLLP_SHIFT   16
 
#define RCC_PLLCFGR_PLLN_SHIFT   6
 
#define RCC_PLLCFGR_PLLM_SHIFT   0
 
#define RCC_CFGR_MCO2_SHIFT   30
 
#define RCC_CFGR_MCO2_SYSCLK   0x0
 
#define RCC_CFGR_MCO2_PLLI2S   0x1
 
#define RCC_CFGR_MCO2_HSE   0x2
 
#define RCC_CFGR_MCO2_PLL   0x3
 
#define RCC_CFGR_MCO2PRE_SHIFT   27
 
#define RCC_CFGR_MCO1PRE_SHIFT   24
 
#define RCC_CFGR_MCOPRE_DIV_NONE   0x0
 
#define RCC_CFGR_MCOPRE_DIV_2   0x4
 
#define RCC_CFGR_MCOPRE_DIV_3   0x5
 
#define RCC_CFGR_MCOPRE_DIV_4   0x6
 
#define RCC_CFGR_MCOPRE_DIV_5   0x7
 
#define RCC_CFGR_I2SSRC   (1 << 23)
 
#define RCC_CFGR_MCO1_SHIFT   21
 
#define RCC_CFGR_MCO1_MASK   0x3
 
#define RCC_CFGR_MCO1_HSI   0x0
 
#define RCC_CFGR_MCO1_LSE   0x1
 
#define RCC_CFGR_MCO1_HSE   0x2
 
#define RCC_CFGR_MCO1_PLL   0x3
 
#define RCC_CFGR_MCO_SHIFT   RCC_CFGR_MCO1_SHIFT
 
#define RCC_CFGR_MCO_MASK   RCC_CFGR_MCO1_MASK
 
#define RCC_CFGR_RTCPRE_SHIFT   16
 
#define RCC_CFGR_RTCPRE_MASK   0x1f
 
#define RCC_CFGR_PPRE2_SHIFT   13
 
#define RCC_CFGR_PPRE2_MASK   0x7
 
#define RCC_CFGR_PPRE1_SHIFT   10
 
#define RCC_CFGR_PPRE1_MASK   0x7
 
#define RCC_CFGR_HPRE_SHIFT   4
 
#define RCC_CFGR_HPRE_MASK   0xf
 
#define RCC_CFGR_SWS_SHIFT   2
 
#define RCC_CFGR_SWS_MASK   0x3
 
#define RCC_CFGR_SWS_HSI   0x0
 
#define RCC_CFGR_SWS_HSE   0x1
 
#define RCC_CFGR_SWS_PLL   0x2
 
#define RCC_CFGR_SW_SHIFT   0
 
#define RCC_CFGR_SW_HSI   0x0
 
#define RCC_CFGR_SW_HSE   0x1
 
#define RCC_CFGR_SW_PLL   0x2
 
#define RCC_CIR_CSSC   (1 << 23)
 
#define RCC_CIR_PLLI2SRDYC   (1 << 21)
 
#define RCC_CIR_PLLRDYC   (1 << 20)
 
#define RCC_CIR_HSERDYC   (1 << 19)
 
#define RCC_CIR_HSIRDYC   (1 << 18)
 
#define RCC_CIR_LSERDYC   (1 << 17)
 
#define RCC_CIR_LSIRDYC   (1 << 16)
 
#define RCC_CIR_PLLI2SRDYIE   (1 << 13)
 
#define RCC_CIR_PLLRDYIE   (1 << 12)
 
#define RCC_CIR_HSERDYIE   (1 << 11)
 
#define RCC_CIR_HSIRDYIE   (1 << 10)
 
#define RCC_CIR_LSERDYIE   (1 << 9)
 
#define RCC_CIR_LSIRDYIE   (1 << 8)
 
#define RCC_CIR_CSSF   (1 << 7)
 
#define RCC_CIR_PLLI2SRDYF   (1 << 5)
 
#define RCC_CIR_PLLRDYF   (1 << 4)
 
#define RCC_CIR_HSERDYF   (1 << 3)
 
#define RCC_CIR_HSIRDYF   (1 << 2)
 
#define RCC_CIR_LSERDYF   (1 << 1)
 
#define RCC_CIR_LSIRDYF   (1 << 0)
 
#define RCC_AHB1LPENR_OTGHSULPILPEN   (1 << 30)
 
#define RCC_AHB1LPENR_OTGHSLPEN   (1 << 29)
 
#define RCC_AHB1LPENR_ETHMACPTPLPEN   (1 << 28)
 
#define RCC_AHB1LPENR_ETHMACRXLPEN   (1 << 27)
 
#define RCC_AHB1LPENR_ETHMACTXLPEN   (1 << 26)
 
#define RCC_AHB1LPENR_ETHMACLPEN   (1 << 25)
 
#define RCC_AHB1LPENR_DMA2LPEN   (1 << 22)
 
#define RCC_AHB1LPENR_DMA1LPEN   (1 << 21)
 
#define RCC_AHB1LPENR_BKPSRAMLPEN   (1 << 18)
 
#define RCC_AHB1LPENR_SRAM2LPEN   (1 << 17)
 
#define RCC_AHB1LPENR_SRAM1LPEN   (1 << 16)
 
#define RCC_AHB1LPENR_FLITFLPEN   (1 << 15)
 
#define RCC_AHB1LPENR_CRCLPEN   (1 << 12)
 
#define RCC_AHB1LPENR_GPIOILPEN   (1 << 8)
 
#define RCC_AHB1LPENR_GPIOHLPEN   (1 << 7)
 
#define RCC_AHB1LPENR_GPIOGLPEN   (1 << 6)
 
#define RCC_AHB1LPENR_GPIOFLPEN   (1 << 5)
 
#define RCC_AHB1LPENR_GPIOELPEN   (1 << 4)
 
#define RCC_AHB1LPENR_GPIODLPEN   (1 << 3)
 
#define RCC_AHB1LPENR_GPIOCLPEN   (1 << 2)
 
#define RCC_AHB1LPENR_GPIOBLPEN   (1 << 1)
 
#define RCC_AHB1LPENR_GPIOALPEN   (1 << 0)
 
#define RCC_AHB2LPENR_OTGFSLPEN   (1 << 7)
 
#define RCC_AHB2LPENR_RNGLPEN   (1 << 6)
 
#define RCC_AHB2LPENR_HASHLPEN   (1 << 5)
 
#define RCC_AHB2LPENR_CRYPLPEN   (1 << 4)
 
#define RCC_AHB2LPENR_DCMILPEN   (1 << 0)
 
#define RCC_AHB3LPENR_FSMCLPEN   (1 << 0)
 
#define RCC_APB1LPENR_DACLPEN   (1 << 29)
 
#define RCC_APB1LPENR_PWRLPEN   (1 << 28)
 
#define RCC_APB1LPENR_CAN2LPEN   (1 << 26)
 
#define RCC_APB1LPENR_CAN1LPEN   (1 << 25)
 
#define RCC_APB1LPENR_I2C3LPEN   (1 << 23)
 
#define RCC_APB1LPENR_I2C2LPEN   (1 << 22)
 
#define RCC_APB1LPENR_I2C1LPEN   (1 << 21)
 
#define RCC_APB1LPENR_UART5LPEN   (1 << 20)
 
#define RCC_APB1LPENR_UART4LPEN   (1 << 19)
 
#define RCC_APB1LPENR_USART3LPEN   (1 << 18)
 
#define RCC_APB1LPENR_USART2LPEN   (1 << 17)
 
#define RCC_APB1LPENR_SPI3LPEN   (1 << 15)
 
#define RCC_APB1LPENR_SPI2LPEN   (1 << 14)
 
#define RCC_APB1LPENR_WWDGLPEN   (1 << 11)
 
#define RCC_APB1LPENR_TIM14LPEN   (1 << 8)
 
#define RCC_APB1LPENR_TIM13LPEN   (1 << 7)
 
#define RCC_APB1LPENR_TIM12LPEN   (1 << 6)
 
#define RCC_APB1LPENR_TIM7LPEN   (1 << 5)
 
#define RCC_APB1LPENR_TIM6LPEN   (1 << 4)
 
#define RCC_APB1LPENR_TIM5LPEN   (1 << 3)
 
#define RCC_APB1LPENR_TIM4LPEN   (1 << 2)
 
#define RCC_APB1LPENR_TIM3LPEN   (1 << 1)
 
#define RCC_APB1LPENR_TIM2LPEN   (1 << 0)
 
#define RCC_APB2LPENR_TIM11LPEN   (1 << 18)
 
#define RCC_APB2LPENR_TIM10LPEN   (1 << 17)
 
#define RCC_APB2LPENR_TIM9LPEN   (1 << 16)
 
#define RCC_APB2LPENR_SYSCFGLPEN   (1 << 14)
 
#define RCC_APB2LPENR_SPI1LPEN   (1 << 12)
 
#define RCC_APB2LPENR_SDIOLPEN   (1 << 11)
 
#define RCC_APB2LPENR_ADC3LPEN   (1 << 10)
 
#define RCC_APB2LPENR_ADC2LPEN   (1 << 9)
 
#define RCC_APB2LPENR_ADC1LPEN   (1 << 8)
 
#define RCC_APB2LPENR_USART6LPEN   (1 << 5)
 
#define RCC_APB2LPENR_USART1LPEN   (1 << 4)
 
#define RCC_APB2LPENR_TIM8LPEN   (1 << 1)
 
#define RCC_APB2LPENR_TIM1LPEN   (1 << 0)
 
#define RCC_BDCR_BDRST   (1 << 16)
 
#define RCC_BDCR_RTCEN   (1 << 15)
 
#define RCC_BDCR_LSEBYP   (1 << 2)
 
#define RCC_BDCR_LSERDY   (1 << 1)
 
#define RCC_BDCR_LSEON   (1 << 0)
 
#define RCC_CSR_LPWRRSTF   (1 << 31)
 
#define RCC_CSR_WWDGRSTF   (1 << 30)
 
#define RCC_CSR_IWDGRSTF   (1 << 29)
 
#define RCC_CSR_SFTRSTF   (1 << 28)
 
#define RCC_CSR_PORRSTF   (1 << 27)
 
#define RCC_CSR_PINRSTF   (1 << 26)
 
#define RCC_CSR_BORRSTF   (1 << 25)
 
#define RCC_CSR_RMVF   (1 << 24)
 
#define RCC_CSR_RESET_FLAGS
 
#define RCC_CSR_LSIRDY   (1 << 1)
 
#define RCC_CSR_LSION   (1 << 0)
 
#define RCC_SSCGR_SSCGEN   (1 << 31)
 
#define RCC_SSCGR_SPREADSEL   (1 << 30)
 
#define RCC_SSCGR_INCSTEP_SHIFT   16
 
#define RCC_SSCGR_MODPER_SHIFT   15
 
#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT   28
 
#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT   6
 
#define _REG_BIT(base, bit)   (((base) << 5) + (bit))
 

Enumerations

enum  rcc_clock_3v3 { RCC_CLOCK_3V3_120MHZ , RCC_CLOCK_3V3_END }
 
enum  rcc_osc {
  RCC_PLL , RCC_HSE , RCC_HSI , RCC_LSE ,
  RCC_LSI
}
 
enum  rcc_periph_clken {
  RCC_GPIOA = _REG_BIT(0x30, 0) , RCC_GPIOB = _REG_BIT(0x30, 1) , RCC_GPIOC = _REG_BIT(0x30, 2) , RCC_GPIOD = _REG_BIT(0x30, 3) ,
  RCC_GPIOE = _REG_BIT(0x30, 4) , RCC_GPIOF = _REG_BIT(0x30, 5) , RCC_GPIOG = _REG_BIT(0x30, 6) , RCC_GPIOH = _REG_BIT(0x30, 7) ,
  RCC_GPIOI = _REG_BIT(0x30, 8) , RCC_CRC = _REG_BIT(0x30, 12) , RCC_BKPSRAM = _REG_BIT(0x30, 18) , RCC_DMA1 = _REG_BIT(0x30, 21) ,
  RCC_DMA2 = _REG_BIT(0x30, 22) , RCC_ETHMAC = _REG_BIT(0x30, 25) , RCC_ETHMACTX = _REG_BIT(0x30, 26) , RCC_ETHMACRX = _REG_BIT(0x30, 27) ,
  RCC_ETHMACPTP = _REG_BIT(0x30, 28) , RCC_OTGHS = _REG_BIT(0x30, 29) , RCC_OTGHSULPI = _REG_BIT(0x30, 30) , RCC_DCMI = _REG_BIT(0x34, 0) ,
  RCC_CRYP = _REG_BIT(0x34, 4) , RCC_HASH = _REG_BIT(0x34, 5) , RCC_RNG = _REG_BIT(0x34, 6) , RCC_OTGFS = _REG_BIT(0x34, 7) ,
  RCC_FSMC = _REG_BIT(0x38, 0) , RCC_TIM2 = _REG_BIT(0x40, 0) , RCC_TIM3 = _REG_BIT(0x40, 1) , RCC_TIM4 = _REG_BIT(0x40, 2) ,
  RCC_TIM5 = _REG_BIT(0x40, 3) , RCC_TIM6 = _REG_BIT(0x40, 4) , RCC_TIM7 = _REG_BIT(0x40, 5) , RCC_TIM12 = _REG_BIT(0x40, 6) ,
  RCC_TIM13 = _REG_BIT(0x40, 7) , RCC_TIM14 = _REG_BIT(0x40, 8) , RCC_WWDG = _REG_BIT(0x40, 11) , RCC_SPI2 = _REG_BIT(0x40, 14) ,
  RCC_SPI3 = _REG_BIT(0x40, 15) , RCC_USART2 = _REG_BIT(0x40, 17) , RCC_USART3 = _REG_BIT(0x40, 18) , RCC_UART4 = _REG_BIT(0x40, 19) ,
  RCC_UART5 = _REG_BIT(0x40, 20) , RCC_I2C1 = _REG_BIT(0x40, 21) , RCC_I2C2 = _REG_BIT(0x40, 22) , RCC_I2C3 = _REG_BIT(0x40, 23) ,
  RCC_CAN1 = _REG_BIT(0x40, 25) , RCC_CAN2 = _REG_BIT(0x40, 26) , RCC_PWR = _REG_BIT(0x40, 28) , RCC_DAC = _REG_BIT(0x40, 29) ,
  RCC_TIM1 = _REG_BIT(0x44, 0) , RCC_TIM8 = _REG_BIT(0x44, 1) , RCC_USART1 = _REG_BIT(0x44, 4) , RCC_USART6 = _REG_BIT(0x44, 5) ,
  RCC_ADC1 = _REG_BIT(0x44, 8) , RCC_ADC2 = _REG_BIT(0x44, 9) , RCC_ADC3 = _REG_BIT(0x44, 10) , RCC_SDIO = _REG_BIT(0x44, 11) ,
  RCC_SPI1 = _REG_BIT(0x44, 12) , RCC_SYSCFG = _REG_BIT(0x44, 14) , RCC_TIM9 = _REG_BIT(0x44, 16) , RCC_TIM10 = _REG_BIT(0x44, 17) ,
  RCC_TIM11 = _REG_BIT(0x44, 18) , RCC_RTC = _REG_BIT(0x70, 15) , SCC_GPIOA = _REG_BIT(0x50, 0) , SCC_GPIOB = _REG_BIT(0x50, 1) ,
  SCC_GPIOC = _REG_BIT(0x50, 2) , SCC_GPIOD = _REG_BIT(0x50, 3) , SCC_GPIOE = _REG_BIT(0x50, 4) , SCC_GPIOF = _REG_BIT(0x50, 5) ,
  SCC_GPIOG = _REG_BIT(0x50, 6) , SCC_GPIOH = _REG_BIT(0x50, 7) , SCC_GPIOI = _REG_BIT(0x50, 8) , SCC_CRC = _REG_BIT(0x50, 12) ,
  SCC_FLTIF = _REG_BIT(0x50, 15) , SCC_SRAM1 = _REG_BIT(0x50, 16) , SCC_SRAM2 = _REG_BIT(0x50, 17) , SCC_BKPSRAM = _REG_BIT(0x50, 18) ,
  SCC_DMA1 = _REG_BIT(0x50, 21) , SCC_DMA2 = _REG_BIT(0x50, 22) , SCC_ETHMAC = _REG_BIT(0x50, 25) , SCC_ETHMACTX = _REG_BIT(0x50, 26) ,
  SCC_ETHMACRX = _REG_BIT(0x50, 27) , SCC_ETHMACPTP = _REG_BIT(0x50, 28) , SCC_OTGHS = _REG_BIT(0x50, 29) , SCC_OTGHSULPI = _REG_BIT(0x50, 30) ,
  SCC_DCMI = _REG_BIT(0x54, 0) , SCC_CRYP = _REG_BIT(0x54, 4) , SCC_HASH = _REG_BIT(0x54, 5) , SCC_RNG = _REG_BIT(0x54, 6) ,
  SCC_OTGFS = _REG_BIT(0x54, 7) , SCC_FSMC = _REG_BIT(0x58, 0) , SCC_TIM2 = _REG_BIT(0x60, 0) , SCC_TIM3 = _REG_BIT(0x60, 1) ,
  SCC_TIM4 = _REG_BIT(0x60, 2) , SCC_TIM5 = _REG_BIT(0x60, 3) , SCC_TIM6 = _REG_BIT(0x60, 4) , SCC_TIM7 = _REG_BIT(0x60, 5) ,
  SCC_TIM12 = _REG_BIT(0x60, 6) , SCC_TIM13 = _REG_BIT(0x60, 7) , SCC_TIM14 = _REG_BIT(0x60, 8) , SCC_WWDG = _REG_BIT(0x60, 11) ,
  SCC_SPI2 = _REG_BIT(0x60, 14) , SCC_SPI3 = _REG_BIT(0x60, 15) , SCC_USART2 = _REG_BIT(0x60, 17) , SCC_USART3 = _REG_BIT(0x60, 18) ,
  SCC_UART4 = _REG_BIT(0x60, 19) , SCC_UART5 = _REG_BIT(0x60, 20) , SCC_I2C1 = _REG_BIT(0x60, 21) , SCC_I2C2 = _REG_BIT(0x60, 22) ,
  SCC_I2C3 = _REG_BIT(0x60, 23) , SCC_CAN1 = _REG_BIT(0x60, 25) , SCC_CAN2 = _REG_BIT(0x60, 26) , SCC_PWR = _REG_BIT(0x60, 28) ,
  SCC_DAC = _REG_BIT(0x60, 29) , SCC_TIM1 = _REG_BIT(0x64, 0) , SCC_TIM8 = _REG_BIT(0x64, 1) , SCC_USART1 = _REG_BIT(0x64, 4) ,
  SCC_USART6 = _REG_BIT(0x64, 5) , SCC_ADC1 = _REG_BIT(0x64, 8) , SCC_ADC2 = _REG_BIT(0x64, 9) , SCC_ADC3 = _REG_BIT(0x64, 10) ,
  SCC_SDIO = _REG_BIT(0x64, 11) , SCC_SPI1 = _REG_BIT(0x64, 12) , SCC_SYSCFG = _REG_BIT(0x64, 14) , SCC_TIM9 = _REG_BIT(0x64, 16) ,
  SCC_TIM10 = _REG_BIT(0x64, 17) , SCC_TIM11 = _REG_BIT(0x64, 18)
}
 
enum  rcc_periph_rst {
  RST_GPIOA = _REG_BIT(0x10, 0) , RST_GPIOB = _REG_BIT(0x10, 1) , RST_GPIOC = _REG_BIT(0x10, 2) , RST_GPIOD = _REG_BIT(0x10, 3) ,
  RST_GPIOE = _REG_BIT(0x10, 4) , RST_GPIOF = _REG_BIT(0x10, 5) , RST_GPIOG = _REG_BIT(0x10, 6) , RST_GPIOH = _REG_BIT(0x10, 7) ,
  RST_GPIOI = _REG_BIT(0x10, 8) , RST_CRC = _REG_BIT(0x10, 12) , RST_DMA1 = _REG_BIT(0x10, 21) , RST_DMA2 = _REG_BIT(0x10, 22) ,
  RST_ETHMAC = _REG_BIT(0x10, 25) , RST_OTGHS = _REG_BIT(0x10, 29) , RST_DCMI = _REG_BIT(0x14, 0) , RST_CRYP = _REG_BIT(0x14, 4) ,
  RST_HASH = _REG_BIT(0x14, 5) , RST_RNG = _REG_BIT(0x14, 6) , RST_OTGFS = _REG_BIT(0x14, 7) , RST_FSMC = _REG_BIT(0x18, 0) ,
  RST_TIM2 = _REG_BIT(0x20, 0) , RST_TIM3 = _REG_BIT(0x20, 1) , RST_TIM4 = _REG_BIT(0x20, 2) , RST_TIM5 = _REG_BIT(0x20, 3) ,
  RST_TIM6 = _REG_BIT(0x20, 4) , RST_TIM7 = _REG_BIT(0x20, 5) , RST_TIM12 = _REG_BIT(0x20, 6) , RST_TIM13 = _REG_BIT(0x20, 7) ,
  RST_TIM14 = _REG_BIT(0x20, 8) , RST_WWDG = _REG_BIT(0x20, 11) , RST_SPI2 = _REG_BIT(0x20, 14) , RST_SPI3 = _REG_BIT(0x20, 15) ,
  RST_USART2 = _REG_BIT(0x20, 17) , RST_USART3 = _REG_BIT(0x20, 18) , RST_UART4 = _REG_BIT(0x20, 19) , RST_UART5 = _REG_BIT(0x20, 20) ,
  RST_I2C1 = _REG_BIT(0x20, 21) , RST_I2C2 = _REG_BIT(0x20, 22) , RST_I2C3 = _REG_BIT(0x20, 23) , RST_CAN1 = _REG_BIT(0x20, 25) ,
  RST_CAN2 = _REG_BIT(0x20, 26) , RST_PWR = _REG_BIT(0x20, 28) , RST_DAC = _REG_BIT(0x20, 29) , RST_TIM1 = _REG_BIT(0x24, 0) ,
  RST_TIM8 = _REG_BIT(0x24, 1) , RST_USART1 = _REG_BIT(0x24, 4) , RST_USART6 = _REG_BIT(0x24, 5) , RST_ADC = _REG_BIT(0x24, 8) ,
  RST_SDIO = _REG_BIT(0x24, 11) , RST_SPI1 = _REG_BIT(0x24, 12) , RST_SYSCFG = _REG_BIT(0x24, 14) , RST_TIM9 = _REG_BIT(0x24, 16) ,
  RST_TIM10 = _REG_BIT(0x24, 17) , RST_TIM11 = _REG_BIT(0x24, 18)
}
 

Functions

void rcc_osc_ready_int_clear (enum rcc_osc osc)
 
void rcc_osc_ready_int_enable (enum rcc_osc osc)
 
void rcc_osc_ready_int_disable (enum rcc_osc osc)
 
int rcc_osc_ready_int_flag (enum rcc_osc osc)
 
void rcc_css_int_clear (void)
 
int rcc_css_int_flag (void)
 
void rcc_wait_for_sysclk_status (enum rcc_osc osc)
 
void rcc_osc_on (enum rcc_osc osc)
 
void rcc_osc_off (enum rcc_osc osc)
 
void rcc_css_enable (void)
 
void rcc_css_disable (void)
 
void rcc_set_sysclk_source (uint32_t clk)
 
void rcc_set_pll_source (uint32_t pllsrc)
 
void rcc_set_ppre2 (uint32_t ppre2)
 
void rcc_set_ppre1 (uint32_t ppre1)
 
void rcc_set_hpre (uint32_t hpre)
 
void rcc_set_rtcpre (uint32_t rtcpre)
 
void rcc_set_main_pll_hsi (uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq)
 
void rcc_set_main_pll_hse (uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq)
 
uint32_t rcc_system_clock_source (void)
 
void rcc_clock_setup_hse_3v3 (const struct rcc_clock_scale *clock)
 
void rcc_backupdomain_reset (void)
 
uint32_t rcc_get_usart_clk_freq (uint32_t usart)
 Get the peripheral clock speed for the USART at base specified. More...
 
uint32_t rcc_get_timer_clk_freq (uint32_t timer)
 Get the peripheral clock speed for the Timer at base specified. More...
 
uint32_t rcc_get_i2c_clk_freq (uint32_t i2c)
 Get the peripheral clock speed for the I2C device at base specified. More...
 
uint32_t rcc_get_spi_clk_freq (uint32_t spi)
 Get the peripheral clock speed for the SPI device at base specified. More...
 
void rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en)
 RCC Enable Peripheral Clocks. More...
 
void rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en)
 RCC Disable Peripheral Clocks. More...
 
void rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset)
 RCC Reset Peripherals. More...
 
void rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset)
 RCC Remove Reset on Peripherals. More...
 
void rcc_periph_clock_enable (enum rcc_periph_clken clken)
 Enable Peripheral Clock in running mode. More...
 
void rcc_periph_clock_disable (enum rcc_periph_clken clken)
 Disable Peripheral Clock in running mode. More...
 
void rcc_periph_reset_pulse (enum rcc_periph_rst rst)
 Reset Peripheral, pulsed. More...
 
void rcc_periph_reset_hold (enum rcc_periph_rst rst)
 Reset Peripheral, hold. More...
 
void rcc_periph_reset_release (enum rcc_periph_rst rst)
 Reset Peripheral, release. More...
 
void rcc_set_mco (uint32_t mcosrc)
 Select the source of Microcontroller Clock Output. More...
 
void rcc_osc_bypass_enable (enum rcc_osc osc)
 RCC Enable Bypass. More...
 
void rcc_osc_bypass_disable (enum rcc_osc osc)
 RCC Disable Bypass. More...
 
bool rcc_is_osc_ready (enum rcc_osc osc)
 Is the given oscillator ready? More...
 
void rcc_wait_for_osc_ready (enum rcc_osc osc)
 Wait for Oscillator Ready. More...
 
uint16_t rcc_get_div_from_hpre (uint8_t div_val)
 This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More...
 

Variables

uint32_t rcc_ahb_frequency
 
uint32_t rcc_apb1_frequency
 
uint32_t rcc_apb2_frequency
 
const struct rcc_clock_scale rcc_hse_8mhz_3v3 [RCC_CLOCK_3V3_END]
 

Detailed Description

Defined Constants and Types for the STM32F2xx Reset and Clock Control

Version
1.0.0
Author
© 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
© 2009 Uwe Hermann uwe@h.nosp@m.erma.nosp@m.nn-uw.nosp@m.e.de
© 2011 Fergus Noble fergu.nosp@m.snob.nosp@m.le@gm.nosp@m.ail..nosp@m.com
Date
18 August 2012

LGPL License Terms libopencm3 License

Author
© 2013 Frantisek Burian BuFra.nosp@m.n@se.nosp@m.znam..nosp@m.cz

Macro Definition Documentation

◆ _REG_BIT

#define _REG_BIT (   base,
  bit 
)    (((base) << 5) + (bit))

Definition at line 605 of file f2/rcc.h.

◆ RCC_AHB1ENR

#define RCC_AHB1ENR   MMIO32(RCC_BASE + 0x30)

Definition at line 60 of file f2/rcc.h.

◆ RCC_AHB1LPENR

#define RCC_AHB1LPENR   MMIO32(RCC_BASE + 0x50)

Definition at line 68 of file f2/rcc.h.

◆ RCC_AHB1LPENR_BKPSRAMLPEN

#define RCC_AHB1LPENR_BKPSRAMLPEN   (1 << 18)

Definition at line 443 of file f2/rcc.h.

◆ RCC_AHB1LPENR_CRCLPEN

#define RCC_AHB1LPENR_CRCLPEN   (1 << 12)

Definition at line 447 of file f2/rcc.h.

◆ RCC_AHB1LPENR_DMA1LPEN

#define RCC_AHB1LPENR_DMA1LPEN   (1 << 21)

Definition at line 442 of file f2/rcc.h.

◆ RCC_AHB1LPENR_DMA2LPEN

#define RCC_AHB1LPENR_DMA2LPEN   (1 << 22)

Definition at line 441 of file f2/rcc.h.

◆ RCC_AHB1LPENR_ETHMACLPEN

#define RCC_AHB1LPENR_ETHMACLPEN   (1 << 25)

Definition at line 440 of file f2/rcc.h.

◆ RCC_AHB1LPENR_ETHMACPTPLPEN

#define RCC_AHB1LPENR_ETHMACPTPLPEN   (1 << 28)

Definition at line 437 of file f2/rcc.h.

◆ RCC_AHB1LPENR_ETHMACRXLPEN

#define RCC_AHB1LPENR_ETHMACRXLPEN   (1 << 27)

Definition at line 438 of file f2/rcc.h.

◆ RCC_AHB1LPENR_ETHMACTXLPEN

#define RCC_AHB1LPENR_ETHMACTXLPEN   (1 << 26)

Definition at line 439 of file f2/rcc.h.

◆ RCC_AHB1LPENR_FLITFLPEN

#define RCC_AHB1LPENR_FLITFLPEN   (1 << 15)

Definition at line 446 of file f2/rcc.h.

◆ RCC_AHB1LPENR_GPIOALPEN

#define RCC_AHB1LPENR_GPIOALPEN   (1 << 0)

Definition at line 456 of file f2/rcc.h.

◆ RCC_AHB1LPENR_GPIOBLPEN

#define RCC_AHB1LPENR_GPIOBLPEN   (1 << 1)

Definition at line 455 of file f2/rcc.h.

◆ RCC_AHB1LPENR_GPIOCLPEN

#define RCC_AHB1LPENR_GPIOCLPEN   (1 << 2)

Definition at line 454 of file f2/rcc.h.

◆ RCC_AHB1LPENR_GPIODLPEN

#define RCC_AHB1LPENR_GPIODLPEN   (1 << 3)

Definition at line 453 of file f2/rcc.h.

◆ RCC_AHB1LPENR_GPIOELPEN

#define RCC_AHB1LPENR_GPIOELPEN   (1 << 4)

Definition at line 452 of file f2/rcc.h.

◆ RCC_AHB1LPENR_GPIOFLPEN

#define RCC_AHB1LPENR_GPIOFLPEN   (1 << 5)

Definition at line 451 of file f2/rcc.h.

◆ RCC_AHB1LPENR_GPIOGLPEN

#define RCC_AHB1LPENR_GPIOGLPEN   (1 << 6)

Definition at line 450 of file f2/rcc.h.

◆ RCC_AHB1LPENR_GPIOHLPEN

#define RCC_AHB1LPENR_GPIOHLPEN   (1 << 7)

Definition at line 449 of file f2/rcc.h.

◆ RCC_AHB1LPENR_GPIOILPEN

#define RCC_AHB1LPENR_GPIOILPEN   (1 << 8)

Definition at line 448 of file f2/rcc.h.

◆ RCC_AHB1LPENR_OTGHSLPEN

#define RCC_AHB1LPENR_OTGHSLPEN   (1 << 29)

Definition at line 436 of file f2/rcc.h.

◆ RCC_AHB1LPENR_OTGHSULPILPEN

#define RCC_AHB1LPENR_OTGHSULPILPEN   (1 << 30)

Definition at line 435 of file f2/rcc.h.

◆ RCC_AHB1LPENR_SRAM1LPEN

#define RCC_AHB1LPENR_SRAM1LPEN   (1 << 16)

Definition at line 445 of file f2/rcc.h.

◆ RCC_AHB1LPENR_SRAM2LPEN

#define RCC_AHB1LPENR_SRAM2LPEN   (1 << 17)

Definition at line 444 of file f2/rcc.h.

◆ RCC_AHB1RSTR

#define RCC_AHB1RSTR   MMIO32(RCC_BASE + 0x10)

Definition at line 52 of file f2/rcc.h.

◆ RCC_AHB2ENR

#define RCC_AHB2ENR   MMIO32(RCC_BASE + 0x34)

Definition at line 61 of file f2/rcc.h.

◆ RCC_AHB2LPENR

#define RCC_AHB2LPENR   MMIO32(RCC_BASE + 0x54)

Definition at line 69 of file f2/rcc.h.

◆ RCC_AHB2LPENR_CRYPLPEN

#define RCC_AHB2LPENR_CRYPLPEN   (1 << 4)

Definition at line 478 of file f2/rcc.h.

◆ RCC_AHB2LPENR_DCMILPEN

#define RCC_AHB2LPENR_DCMILPEN   (1 << 0)

Definition at line 479 of file f2/rcc.h.

◆ RCC_AHB2LPENR_HASHLPEN

#define RCC_AHB2LPENR_HASHLPEN   (1 << 5)

Definition at line 477 of file f2/rcc.h.

◆ RCC_AHB2LPENR_OTGFSLPEN

#define RCC_AHB2LPENR_OTGFSLPEN   (1 << 7)

Definition at line 475 of file f2/rcc.h.

◆ RCC_AHB2LPENR_RNGLPEN

#define RCC_AHB2LPENR_RNGLPEN   (1 << 6)

Definition at line 476 of file f2/rcc.h.

◆ RCC_AHB2RSTR

#define RCC_AHB2RSTR   MMIO32(RCC_BASE + 0x14)

Definition at line 53 of file f2/rcc.h.

◆ RCC_AHB3ENR

#define RCC_AHB3ENR   MMIO32(RCC_BASE + 0x38)

Definition at line 62 of file f2/rcc.h.

◆ RCC_AHB3LPENR

#define RCC_AHB3LPENR   MMIO32(RCC_BASE + 0x58)

Definition at line 70 of file f2/rcc.h.

◆ RCC_AHB3LPENR_FSMCLPEN

#define RCC_AHB3LPENR_FSMCLPEN   (1 << 0)

Definition at line 483 of file f2/rcc.h.

◆ RCC_AHB3RSTR

#define RCC_AHB3RSTR   MMIO32(RCC_BASE + 0x18)

Definition at line 54 of file f2/rcc.h.

◆ RCC_APB1ENR

#define RCC_APB1ENR   MMIO32(RCC_BASE + 0x40)

Definition at line 64 of file f2/rcc.h.

◆ RCC_APB1LPENR

#define RCC_APB1LPENR   MMIO32(RCC_BASE + 0x60)

Definition at line 72 of file f2/rcc.h.

◆ RCC_APB1LPENR_CAN1LPEN

#define RCC_APB1LPENR_CAN1LPEN   (1 << 25)

Definition at line 490 of file f2/rcc.h.

◆ RCC_APB1LPENR_CAN2LPEN

#define RCC_APB1LPENR_CAN2LPEN   (1 << 26)

Definition at line 489 of file f2/rcc.h.

◆ RCC_APB1LPENR_DACLPEN

#define RCC_APB1LPENR_DACLPEN   (1 << 29)

Definition at line 487 of file f2/rcc.h.

◆ RCC_APB1LPENR_I2C1LPEN

#define RCC_APB1LPENR_I2C1LPEN   (1 << 21)

Definition at line 493 of file f2/rcc.h.

◆ RCC_APB1LPENR_I2C2LPEN

#define RCC_APB1LPENR_I2C2LPEN   (1 << 22)

Definition at line 492 of file f2/rcc.h.

◆ RCC_APB1LPENR_I2C3LPEN

#define RCC_APB1LPENR_I2C3LPEN   (1 << 23)

Definition at line 491 of file f2/rcc.h.

◆ RCC_APB1LPENR_PWRLPEN

#define RCC_APB1LPENR_PWRLPEN   (1 << 28)

Definition at line 488 of file f2/rcc.h.

◆ RCC_APB1LPENR_SPI2LPEN

#define RCC_APB1LPENR_SPI2LPEN   (1 << 14)

Definition at line 499 of file f2/rcc.h.

◆ RCC_APB1LPENR_SPI3LPEN

#define RCC_APB1LPENR_SPI3LPEN   (1 << 15)

Definition at line 498 of file f2/rcc.h.

◆ RCC_APB1LPENR_TIM12LPEN

#define RCC_APB1LPENR_TIM12LPEN   (1 << 6)

Definition at line 503 of file f2/rcc.h.

◆ RCC_APB1LPENR_TIM13LPEN

#define RCC_APB1LPENR_TIM13LPEN   (1 << 7)

Definition at line 502 of file f2/rcc.h.

◆ RCC_APB1LPENR_TIM14LPEN

#define RCC_APB1LPENR_TIM14LPEN   (1 << 8)

Definition at line 501 of file f2/rcc.h.

◆ RCC_APB1LPENR_TIM2LPEN

#define RCC_APB1LPENR_TIM2LPEN   (1 << 0)

Definition at line 509 of file f2/rcc.h.

◆ RCC_APB1LPENR_TIM3LPEN

#define RCC_APB1LPENR_TIM3LPEN   (1 << 1)

Definition at line 508 of file f2/rcc.h.

◆ RCC_APB1LPENR_TIM4LPEN

#define RCC_APB1LPENR_TIM4LPEN   (1 << 2)

Definition at line 507 of file f2/rcc.h.

◆ RCC_APB1LPENR_TIM5LPEN

#define RCC_APB1LPENR_TIM5LPEN   (1 << 3)

Definition at line 506 of file f2/rcc.h.

◆ RCC_APB1LPENR_TIM6LPEN

#define RCC_APB1LPENR_TIM6LPEN   (1 << 4)

Definition at line 505 of file f2/rcc.h.

◆ RCC_APB1LPENR_TIM7LPEN

#define RCC_APB1LPENR_TIM7LPEN   (1 << 5)

Definition at line 504 of file f2/rcc.h.

◆ RCC_APB1LPENR_UART4LPEN

#define RCC_APB1LPENR_UART4LPEN   (1 << 19)

Definition at line 495 of file f2/rcc.h.

◆ RCC_APB1LPENR_UART5LPEN

#define RCC_APB1LPENR_UART5LPEN   (1 << 20)

Definition at line 494 of file f2/rcc.h.

◆ RCC_APB1LPENR_USART2LPEN

#define RCC_APB1LPENR_USART2LPEN   (1 << 17)

Definition at line 497 of file f2/rcc.h.

◆ RCC_APB1LPENR_USART3LPEN

#define RCC_APB1LPENR_USART3LPEN   (1 << 18)

Definition at line 496 of file f2/rcc.h.

◆ RCC_APB1LPENR_WWDGLPEN

#define RCC_APB1LPENR_WWDGLPEN   (1 << 11)

Definition at line 500 of file f2/rcc.h.

◆ RCC_APB1RSTR

#define RCC_APB1RSTR   MMIO32(RCC_BASE + 0x20)

Definition at line 56 of file f2/rcc.h.

◆ RCC_APB2ENR

#define RCC_APB2ENR   MMIO32(RCC_BASE + 0x44)

Definition at line 65 of file f2/rcc.h.

◆ RCC_APB2LPENR

#define RCC_APB2LPENR   MMIO32(RCC_BASE + 0x64)

Definition at line 73 of file f2/rcc.h.

◆ RCC_APB2LPENR_ADC1LPEN

#define RCC_APB2LPENR_ADC1LPEN   (1 << 8)

Definition at line 521 of file f2/rcc.h.

◆ RCC_APB2LPENR_ADC2LPEN

#define RCC_APB2LPENR_ADC2LPEN   (1 << 9)

Definition at line 520 of file f2/rcc.h.

◆ RCC_APB2LPENR_ADC3LPEN

#define RCC_APB2LPENR_ADC3LPEN   (1 << 10)

Definition at line 519 of file f2/rcc.h.

◆ RCC_APB2LPENR_SDIOLPEN

#define RCC_APB2LPENR_SDIOLPEN   (1 << 11)

Definition at line 518 of file f2/rcc.h.

◆ RCC_APB2LPENR_SPI1LPEN

#define RCC_APB2LPENR_SPI1LPEN   (1 << 12)

Definition at line 517 of file f2/rcc.h.

◆ RCC_APB2LPENR_SYSCFGLPEN

#define RCC_APB2LPENR_SYSCFGLPEN   (1 << 14)

Definition at line 516 of file f2/rcc.h.

◆ RCC_APB2LPENR_TIM10LPEN

#define RCC_APB2LPENR_TIM10LPEN   (1 << 17)

Definition at line 514 of file f2/rcc.h.

◆ RCC_APB2LPENR_TIM11LPEN

#define RCC_APB2LPENR_TIM11LPEN   (1 << 18)

Definition at line 513 of file f2/rcc.h.

◆ RCC_APB2LPENR_TIM1LPEN

#define RCC_APB2LPENR_TIM1LPEN   (1 << 0)

Definition at line 525 of file f2/rcc.h.

◆ RCC_APB2LPENR_TIM8LPEN

#define RCC_APB2LPENR_TIM8LPEN   (1 << 1)

Definition at line 524 of file f2/rcc.h.

◆ RCC_APB2LPENR_TIM9LPEN

#define RCC_APB2LPENR_TIM9LPEN   (1 << 16)

Definition at line 515 of file f2/rcc.h.

◆ RCC_APB2LPENR_USART1LPEN

#define RCC_APB2LPENR_USART1LPEN   (1 << 4)

Definition at line 523 of file f2/rcc.h.

◆ RCC_APB2LPENR_USART6LPEN

#define RCC_APB2LPENR_USART6LPEN   (1 << 5)

Definition at line 522 of file f2/rcc.h.

◆ RCC_APB2RSTR

#define RCC_APB2RSTR   MMIO32(RCC_BASE + 0x24)

Definition at line 57 of file f2/rcc.h.

◆ RCC_BDCR

#define RCC_BDCR   MMIO32(RCC_BASE + 0x70)

Definition at line 76 of file f2/rcc.h.

◆ RCC_BDCR_BDRST

#define RCC_BDCR_BDRST   (1 << 16)

Definition at line 529 of file f2/rcc.h.

◆ RCC_BDCR_LSEBYP

#define RCC_BDCR_LSEBYP   (1 << 2)

Definition at line 532 of file f2/rcc.h.

◆ RCC_BDCR_LSEON

#define RCC_BDCR_LSEON   (1 << 0)

Definition at line 534 of file f2/rcc.h.

◆ RCC_BDCR_LSERDY

#define RCC_BDCR_LSERDY   (1 << 1)

Definition at line 533 of file f2/rcc.h.

◆ RCC_BDCR_RTCEN

#define RCC_BDCR_RTCEN   (1 << 15)

Definition at line 530 of file f2/rcc.h.

◆ RCC_CFGR

#define RCC_CFGR   MMIO32(RCC_BASE + 0x08)

Definition at line 50 of file f2/rcc.h.

◆ RCC_CFGR_HPRE_MASK

#define RCC_CFGR_HPRE_MASK   0xf

Definition at line 161 of file f2/rcc.h.

◆ RCC_CFGR_HPRE_SHIFT

#define RCC_CFGR_HPRE_SHIFT   4

Definition at line 160 of file f2/rcc.h.

◆ RCC_CFGR_I2SSRC

#define RCC_CFGR_I2SSRC   (1 << 23)

Definition at line 129 of file f2/rcc.h.

◆ RCC_CFGR_MCO1_HSE

#define RCC_CFGR_MCO1_HSE   0x2

Definition at line 136 of file f2/rcc.h.

◆ RCC_CFGR_MCO1_HSI

#define RCC_CFGR_MCO1_HSI   0x0

Definition at line 134 of file f2/rcc.h.

◆ RCC_CFGR_MCO1_LSE

#define RCC_CFGR_MCO1_LSE   0x1

Definition at line 135 of file f2/rcc.h.

◆ RCC_CFGR_MCO1_MASK

#define RCC_CFGR_MCO1_MASK   0x3

Definition at line 133 of file f2/rcc.h.

◆ RCC_CFGR_MCO1_PLL

#define RCC_CFGR_MCO1_PLL   0x3

Definition at line 137 of file f2/rcc.h.

◆ RCC_CFGR_MCO1_SHIFT

#define RCC_CFGR_MCO1_SHIFT   21

Definition at line 132 of file f2/rcc.h.

◆ RCC_CFGR_MCO1PRE_SHIFT

#define RCC_CFGR_MCO1PRE_SHIFT   24

Definition at line 121 of file f2/rcc.h.

◆ RCC_CFGR_MCO2_HSE

#define RCC_CFGR_MCO2_HSE   0x2

Definition at line 116 of file f2/rcc.h.

◆ RCC_CFGR_MCO2_PLL

#define RCC_CFGR_MCO2_PLL   0x3

Definition at line 117 of file f2/rcc.h.

◆ RCC_CFGR_MCO2_PLLI2S

#define RCC_CFGR_MCO2_PLLI2S   0x1

Definition at line 115 of file f2/rcc.h.

◆ RCC_CFGR_MCO2_SHIFT

#define RCC_CFGR_MCO2_SHIFT   30

Definition at line 113 of file f2/rcc.h.

◆ RCC_CFGR_MCO2_SYSCLK

#define RCC_CFGR_MCO2_SYSCLK   0x0

Definition at line 114 of file f2/rcc.h.

◆ RCC_CFGR_MCO2PRE_SHIFT

#define RCC_CFGR_MCO2PRE_SHIFT   27

Definition at line 120 of file f2/rcc.h.

◆ RCC_CFGR_MCO_MASK

#define RCC_CFGR_MCO_MASK   RCC_CFGR_MCO1_MASK

Definition at line 139 of file f2/rcc.h.

◆ RCC_CFGR_MCO_SHIFT

#define RCC_CFGR_MCO_SHIFT   RCC_CFGR_MCO1_SHIFT

Definition at line 138 of file f2/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV_2

#define RCC_CFGR_MCOPRE_DIV_2   0x4

Definition at line 123 of file f2/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV_3

#define RCC_CFGR_MCOPRE_DIV_3   0x5

Definition at line 124 of file f2/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV_4

#define RCC_CFGR_MCOPRE_DIV_4   0x6

Definition at line 125 of file f2/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV_5

#define RCC_CFGR_MCOPRE_DIV_5   0x7

Definition at line 126 of file f2/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV_NONE

#define RCC_CFGR_MCOPRE_DIV_NONE   0x0

Definition at line 122 of file f2/rcc.h.

◆ RCC_CFGR_PPRE1_MASK

#define RCC_CFGR_PPRE1_MASK   0x7

Definition at line 148 of file f2/rcc.h.

◆ RCC_CFGR_PPRE1_SHIFT

#define RCC_CFGR_PPRE1_SHIFT   10

Definition at line 147 of file f2/rcc.h.

◆ RCC_CFGR_PPRE2_MASK

#define RCC_CFGR_PPRE2_MASK   0x7

Definition at line 146 of file f2/rcc.h.

◆ RCC_CFGR_PPRE2_SHIFT

#define RCC_CFGR_PPRE2_SHIFT   13

Definition at line 145 of file f2/rcc.h.

◆ RCC_CFGR_RTCPRE_MASK

#define RCC_CFGR_RTCPRE_MASK   0x1f

Definition at line 143 of file f2/rcc.h.

◆ RCC_CFGR_RTCPRE_SHIFT

#define RCC_CFGR_RTCPRE_SHIFT   16

Definition at line 142 of file f2/rcc.h.

◆ RCC_CFGR_SW_HSE

#define RCC_CFGR_SW_HSE   0x1

Definition at line 185 of file f2/rcc.h.

◆ RCC_CFGR_SW_HSI

#define RCC_CFGR_SW_HSI   0x0

Definition at line 184 of file f2/rcc.h.

◆ RCC_CFGR_SW_PLL

#define RCC_CFGR_SW_PLL   0x2

Definition at line 186 of file f2/rcc.h.

◆ RCC_CFGR_SW_SHIFT

#define RCC_CFGR_SW_SHIFT   0

Definition at line 183 of file f2/rcc.h.

◆ RCC_CFGR_SWS_HSE

#define RCC_CFGR_SWS_HSE   0x1

Definition at line 179 of file f2/rcc.h.

◆ RCC_CFGR_SWS_HSI

#define RCC_CFGR_SWS_HSI   0x0

Definition at line 178 of file f2/rcc.h.

◆ RCC_CFGR_SWS_MASK

#define RCC_CFGR_SWS_MASK   0x3

Definition at line 177 of file f2/rcc.h.

◆ RCC_CFGR_SWS_PLL

#define RCC_CFGR_SWS_PLL   0x2

Definition at line 180 of file f2/rcc.h.

◆ RCC_CFGR_SWS_SHIFT

#define RCC_CFGR_SWS_SHIFT   2

Definition at line 176 of file f2/rcc.h.

◆ RCC_CIR

#define RCC_CIR   MMIO32(RCC_BASE + 0x0c)

Definition at line 51 of file f2/rcc.h.

◆ RCC_CIR_CSSC

#define RCC_CIR_CSSC   (1 << 23)

Definition at line 213 of file f2/rcc.h.

◆ RCC_CIR_CSSF

#define RCC_CIR_CSSF   (1 << 7)

Definition at line 232 of file f2/rcc.h.

◆ RCC_CIR_HSERDYC

#define RCC_CIR_HSERDYC   (1 << 19)

Definition at line 218 of file f2/rcc.h.

◆ RCC_CIR_HSERDYF

#define RCC_CIR_HSERDYF   (1 << 3)

Definition at line 237 of file f2/rcc.h.

◆ RCC_CIR_HSERDYIE

#define RCC_CIR_HSERDYIE   (1 << 11)

Definition at line 226 of file f2/rcc.h.

◆ RCC_CIR_HSIRDYC

#define RCC_CIR_HSIRDYC   (1 << 18)

Definition at line 219 of file f2/rcc.h.

◆ RCC_CIR_HSIRDYF

#define RCC_CIR_HSIRDYF   (1 << 2)

Definition at line 238 of file f2/rcc.h.

◆ RCC_CIR_HSIRDYIE

#define RCC_CIR_HSIRDYIE   (1 << 10)

Definition at line 227 of file f2/rcc.h.

◆ RCC_CIR_LSERDYC

#define RCC_CIR_LSERDYC   (1 << 17)

Definition at line 220 of file f2/rcc.h.

◆ RCC_CIR_LSERDYF

#define RCC_CIR_LSERDYF   (1 << 1)

Definition at line 239 of file f2/rcc.h.

◆ RCC_CIR_LSERDYIE

#define RCC_CIR_LSERDYIE   (1 << 9)

Definition at line 228 of file f2/rcc.h.

◆ RCC_CIR_LSIRDYC

#define RCC_CIR_LSIRDYC   (1 << 16)

Definition at line 221 of file f2/rcc.h.

◆ RCC_CIR_LSIRDYF

#define RCC_CIR_LSIRDYF   (1 << 0)

Definition at line 240 of file f2/rcc.h.

◆ RCC_CIR_LSIRDYIE

#define RCC_CIR_LSIRDYIE   (1 << 8)

Definition at line 229 of file f2/rcc.h.

◆ RCC_CIR_PLLI2SRDYC

#define RCC_CIR_PLLI2SRDYC   (1 << 21)

Definition at line 216 of file f2/rcc.h.

◆ RCC_CIR_PLLI2SRDYF

#define RCC_CIR_PLLI2SRDYF   (1 << 5)

Definition at line 235 of file f2/rcc.h.

◆ RCC_CIR_PLLI2SRDYIE

#define RCC_CIR_PLLI2SRDYIE   (1 << 13)

Definition at line 224 of file f2/rcc.h.

◆ RCC_CIR_PLLRDYC

#define RCC_CIR_PLLRDYC   (1 << 20)

Definition at line 217 of file f2/rcc.h.

◆ RCC_CIR_PLLRDYF

#define RCC_CIR_PLLRDYF   (1 << 4)

Definition at line 236 of file f2/rcc.h.

◆ RCC_CIR_PLLRDYIE

#define RCC_CIR_PLLRDYIE   (1 << 12)

Definition at line 225 of file f2/rcc.h.

◆ RCC_CR

#define RCC_CR   MMIO32(RCC_BASE + 0x00)

Definition at line 48 of file f2/rcc.h.

◆ RCC_CR_CSSON

#define RCC_CR_CSSON   (1 << 19)

Definition at line 89 of file f2/rcc.h.

◆ RCC_CR_HSEBYP

#define RCC_CR_HSEBYP   (1 << 18)

Definition at line 90 of file f2/rcc.h.

◆ RCC_CR_HSEON

#define RCC_CR_HSEON   (1 << 16)

Definition at line 92 of file f2/rcc.h.

◆ RCC_CR_HSERDY

#define RCC_CR_HSERDY   (1 << 17)

Definition at line 91 of file f2/rcc.h.

◆ RCC_CR_HSION

#define RCC_CR_HSION   (1 << 0)

Definition at line 96 of file f2/rcc.h.

◆ RCC_CR_HSIRDY

#define RCC_CR_HSIRDY   (1 << 1)

Definition at line 95 of file f2/rcc.h.

◆ RCC_CR_PLLI2SON

#define RCC_CR_PLLI2SON   (1 << 26)

Definition at line 86 of file f2/rcc.h.

◆ RCC_CR_PLLI2SRDY

#define RCC_CR_PLLI2SRDY   (1 << 27)

Definition at line 85 of file f2/rcc.h.

◆ RCC_CR_PLLON

#define RCC_CR_PLLON   (1 << 24)

Definition at line 88 of file f2/rcc.h.

◆ RCC_CR_PLLRDY

#define RCC_CR_PLLRDY   (1 << 25)

Definition at line 87 of file f2/rcc.h.

◆ RCC_CSR

#define RCC_CSR   MMIO32(RCC_BASE + 0x74)

Definition at line 77 of file f2/rcc.h.

◆ RCC_CSR_BORRSTF

#define RCC_CSR_BORRSTF   (1 << 25)

Definition at line 544 of file f2/rcc.h.

◆ RCC_CSR_IWDGRSTF

#define RCC_CSR_IWDGRSTF   (1 << 29)

Definition at line 540 of file f2/rcc.h.

◆ RCC_CSR_LPWRRSTF

#define RCC_CSR_LPWRRSTF   (1 << 31)

Definition at line 538 of file f2/rcc.h.

◆ RCC_CSR_LSION

#define RCC_CSR_LSION   (1 << 0)

Definition at line 550 of file f2/rcc.h.

◆ RCC_CSR_LSIRDY

#define RCC_CSR_LSIRDY   (1 << 1)

Definition at line 549 of file f2/rcc.h.

◆ RCC_CSR_PINRSTF

#define RCC_CSR_PINRSTF   (1 << 26)

Definition at line 543 of file f2/rcc.h.

◆ RCC_CSR_PORRSTF

#define RCC_CSR_PORRSTF   (1 << 27)

Definition at line 542 of file f2/rcc.h.

◆ RCC_CSR_RESET_FLAGS

#define RCC_CSR_RESET_FLAGS
Value:
RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF |\
RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)
#define RCC_CSR_SFTRSTF
Definition: f2/rcc.h:541
#define RCC_CSR_BORRSTF
Definition: f2/rcc.h:544
#define RCC_CSR_LPWRRSTF
Definition: f2/rcc.h:538
#define RCC_CSR_PORRSTF
Definition: f2/rcc.h:542
#define RCC_CSR_WWDGRSTF
Definition: f2/rcc.h:539

Definition at line 546 of file f2/rcc.h.

◆ RCC_CSR_RMVF

#define RCC_CSR_RMVF   (1 << 24)

Definition at line 545 of file f2/rcc.h.

◆ RCC_CSR_SFTRSTF

#define RCC_CSR_SFTRSTF   (1 << 28)

Definition at line 541 of file f2/rcc.h.

◆ RCC_CSR_WWDGRSTF

#define RCC_CSR_WWDGRSTF   (1 << 30)

Definition at line 539 of file f2/rcc.h.

◆ RCC_PLLCFGR

#define RCC_PLLCFGR   MMIO32(RCC_BASE + 0x04)

Definition at line 49 of file f2/rcc.h.

◆ RCC_PLLCFGR_PLLM_SHIFT

#define RCC_PLLCFGR_PLLM_SHIFT   0

Definition at line 108 of file f2/rcc.h.

◆ RCC_PLLCFGR_PLLN_SHIFT

#define RCC_PLLCFGR_PLLN_SHIFT   6

Definition at line 106 of file f2/rcc.h.

◆ RCC_PLLCFGR_PLLP_SHIFT

#define RCC_PLLCFGR_PLLP_SHIFT   16

Definition at line 104 of file f2/rcc.h.

◆ RCC_PLLCFGR_PLLQ_SHIFT

#define RCC_PLLCFGR_PLLQ_SHIFT   24

Definition at line 101 of file f2/rcc.h.

◆ RCC_PLLCFGR_PLLSRC

#define RCC_PLLCFGR_PLLSRC   (1 << 22)

Definition at line 102 of file f2/rcc.h.

◆ RCC_PLLI2SCFGR

#define RCC_PLLI2SCFGR   MMIO32(RCC_BASE + 0x84)

Definition at line 81 of file f2/rcc.h.

◆ RCC_PLLI2SCFGR_PLLI2SN_SHIFT

#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT   6

Definition at line 568 of file f2/rcc.h.

◆ RCC_PLLI2SCFGR_PLLI2SR_SHIFT

#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT   28

Definition at line 566 of file f2/rcc.h.

◆ RCC_SSCGR

#define RCC_SSCGR   MMIO32(RCC_BASE + 0x80)

Definition at line 80 of file f2/rcc.h.

◆ RCC_SSCGR_INCSTEP_SHIFT

#define RCC_SSCGR_INCSTEP_SHIFT   16

Definition at line 559 of file f2/rcc.h.

◆ RCC_SSCGR_MODPER_SHIFT

#define RCC_SSCGR_MODPER_SHIFT   15

Definition at line 561 of file f2/rcc.h.

◆ RCC_SSCGR_SPREADSEL

#define RCC_SSCGR_SPREADSEL   (1 << 30)

Definition at line 557 of file f2/rcc.h.

◆ RCC_SSCGR_SSCGEN

#define RCC_SSCGR_SSCGEN   (1 << 31)

Definition at line 556 of file f2/rcc.h.

Enumeration Type Documentation

◆ rcc_clock_3v3

Enumerator
RCC_CLOCK_3V3_120MHZ 
RCC_CLOCK_3V3_END 

Definition at line 577 of file f2/rcc.h.

◆ rcc_osc

enum rcc_osc
Enumerator
RCC_PLL 
RCC_HSE 
RCC_HSI 
RCC_LSE 
RCC_LSI 

Definition at line 597 of file f2/rcc.h.

◆ rcc_periph_clken

Enumerator
RCC_GPIOA 
RCC_GPIOB 
RCC_GPIOC 
RCC_GPIOD 
RCC_GPIOE 
RCC_GPIOF 
RCC_GPIOG 
RCC_GPIOH 
RCC_GPIOI 
RCC_CRC 
RCC_BKPSRAM 
RCC_DMA1 
RCC_DMA2 
RCC_ETHMAC 
RCC_ETHMACTX 
RCC_ETHMACRX 
RCC_ETHMACPTP 
RCC_OTGHS 
RCC_OTGHSULPI 
RCC_DCMI 
RCC_CRYP 
RCC_HASH 
RCC_RNG 
RCC_OTGFS 
RCC_FSMC 
RCC_TIM2 
RCC_TIM3 
RCC_TIM4 
RCC_TIM5 
RCC_TIM6 
RCC_TIM7 
RCC_TIM12 
RCC_TIM13 
RCC_TIM14 
RCC_WWDG 
RCC_SPI2 
RCC_SPI3 
RCC_USART2 
RCC_USART3 
RCC_UART4 
RCC_UART5 
RCC_I2C1 
RCC_I2C2 
RCC_I2C3 
RCC_CAN1 
RCC_CAN2 
RCC_PWR 
RCC_DAC 
RCC_TIM1 
RCC_TIM8 
RCC_USART1 
RCC_USART6 
RCC_ADC1 
RCC_ADC2 
RCC_ADC3 
RCC_SDIO 
RCC_SPI1 
RCC_SYSCFG 
RCC_TIM9 
RCC_TIM10 
RCC_TIM11 
RCC_RTC 
SCC_GPIOA 
SCC_GPIOB 
SCC_GPIOC 
SCC_GPIOD 
SCC_GPIOE 
SCC_GPIOF 
SCC_GPIOG 
SCC_GPIOH 
SCC_GPIOI 
SCC_CRC 
SCC_FLTIF 
SCC_SRAM1 
SCC_SRAM2 
SCC_BKPSRAM 
SCC_DMA1 
SCC_DMA2 
SCC_ETHMAC 
SCC_ETHMACTX 
SCC_ETHMACRX 
SCC_ETHMACPTP 
SCC_OTGHS 
SCC_OTGHSULPI 
SCC_DCMI 
SCC_CRYP 
SCC_HASH 
SCC_RNG 
SCC_OTGFS 
SCC_FSMC 
SCC_TIM2 
SCC_TIM3 
SCC_TIM4 
SCC_TIM5 
SCC_TIM6 
SCC_TIM7 
SCC_TIM12 
SCC_TIM13 
SCC_TIM14 
SCC_WWDG 
SCC_SPI2 
SCC_SPI3 
SCC_USART2 
SCC_USART3 
SCC_UART4 
SCC_UART5 
SCC_I2C1 
SCC_I2C2 
SCC_I2C3 
SCC_CAN1 
SCC_CAN2 
SCC_PWR 
SCC_DAC 
SCC_TIM1 
SCC_TIM8 
SCC_USART1 
SCC_USART6 
SCC_ADC1 
SCC_ADC2 
SCC_ADC3 
SCC_SDIO 
SCC_SPI1 
SCC_SYSCFG 
SCC_TIM9 
SCC_TIM10 
SCC_TIM11 

Definition at line 607 of file f2/rcc.h.

◆ rcc_periph_rst

Enumerator
RST_GPIOA 
RST_GPIOB 
RST_GPIOC 
RST_GPIOD 
RST_GPIOE 
RST_GPIOF 
RST_GPIOG 
RST_GPIOH 
RST_GPIOI 
RST_CRC 
RST_DMA1 
RST_DMA2 
RST_ETHMAC 
RST_OTGHS 
RST_DCMI 
RST_CRYP 
RST_HASH 
RST_RNG 
RST_OTGFS 
RST_FSMC 
RST_TIM2 
RST_TIM3 
RST_TIM4 
RST_TIM5 
RST_TIM6 
RST_TIM7 
RST_TIM12 
RST_TIM13 
RST_TIM14 
RST_WWDG 
RST_SPI2 
RST_SPI3 
RST_USART2 
RST_USART3 
RST_UART4 
RST_UART5 
RST_I2C1 
RST_I2C2 
RST_I2C3 
RST_CAN1 
RST_CAN2 
RST_PWR 
RST_DAC 
RST_TIM1 
RST_TIM8 
RST_USART1 
RST_USART6 
RST_ADC 
RST_SDIO 
RST_SPI1 
RST_SYSCFG 
RST_TIM9 
RST_TIM10 
RST_TIM11 

Definition at line 757 of file f2/rcc.h.

Function Documentation

◆ rcc_backupdomain_reset()

void rcc_backupdomain_reset ( void  )

Definition at line 383 of file rcc.c.

References RCC_BDCR, and RCC_BDCR_BDRST.

◆ rcc_clock_setup_hse_3v3()

◆ rcc_css_disable()

void rcc_css_disable ( void  )

Definition at line 253 of file rcc.c.

References RCC_CR.

◆ rcc_css_enable()

void rcc_css_enable ( void  )

Definition at line 248 of file rcc.c.

References RCC_CR, and RCC_CR_CSSON.

◆ rcc_css_int_clear()

void rcc_css_int_clear ( void  )

Definition at line 153 of file rcc.c.

References RCC_CIR, and RCC_CIR_CSSC.

◆ rcc_css_int_flag()

int rcc_css_int_flag ( void  )

Definition at line 158 of file rcc.c.

References RCC_CIR, and RCC_CIR_CSSF.

◆ rcc_get_div_from_hpre()

uint16_t rcc_get_div_from_hpre ( uint8_t  div_val)

This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.

Parameters
div_valMasked and shifted divider value from register (e.g. RCC_CFGR)

Definition at line 276 of file rcc_common_all.c.

◆ rcc_get_i2c_clk_freq()

uint32_t rcc_get_i2c_clk_freq ( uint32_t  i2c)

Get the peripheral clock speed for the I2C device at base specified.

Parameters
i2cBase address of I2C to get clock frequency for.

Definition at line 428 of file rcc.c.

References rcc_apb1_frequency.

◆ rcc_get_spi_clk_freq()

uint32_t rcc_get_spi_clk_freq ( uint32_t  spi)

Get the peripheral clock speed for the SPI device at base specified.

Parameters
spiBase address of SPI device to get clock frequency for (e.g. SPI1_BASE).

Definition at line 437 of file rcc.c.

References rcc_apb1_frequency, rcc_apb2_frequency, and SPI1_BASE.

◆ rcc_get_timer_clk_freq()

uint32_t rcc_get_timer_clk_freq ( uint32_t  timer)

Get the peripheral clock speed for the Timer at base specified.

Parameters
timerBase address of TIM to get clock frequency for.

Definition at line 410 of file rcc.c.

References rcc_clock_scale::ppre1, rcc_clock_scale::ppre2, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CFGR, RCC_CFGR_PPRE1_MASK, RCC_CFGR_PPRE1_SHIFT, RCC_CFGR_PPRE2_MASK, RCC_CFGR_PPRE2_SHIFT, RCC_CFGR_PPRE_DIV_NONE, TIM14_BASE, and TIM2_BASE.

◆ rcc_get_usart_clk_freq()

uint32_t rcc_get_usart_clk_freq ( uint32_t  usart)

Get the peripheral clock speed for the USART at base specified.

Parameters
usartBase address of USART to get clock frequency for.

Definition at line 397 of file rcc.c.

References rcc_apb1_frequency, rcc_apb2_frequency, USART1_BASE, and USART6_BASE.

◆ rcc_is_osc_ready()

bool rcc_is_osc_ready ( enum rcc_osc  osc)

Is the given oscillator ready?

Parameters
oscOscillator ID
Returns
true if the hardware indicates the oscillator is ready.

Definition at line 163 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSERDY, RCC_CR, RCC_CR_HSERDY, RCC_CR_HSIRDY, RCC_CR_PLLRDY, RCC_CSR, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_wait_for_osc_ready().

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◆ rcc_osc_bypass_disable()

void rcc_osc_bypass_disable ( enum rcc_osc  osc)

RCC Disable Bypass.

Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note
The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see rcc_backupdomain_reset).
Parameters
[in]oscOscillator ID. Only HSE and LSE have effect.

Definition at line 254 of file rcc_common_all.c.

References RCC_BDCR, RCC_CR, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_bypass_enable()

void rcc_osc_bypass_enable ( enum rcc_osc  osc)

RCC Enable Bypass.

Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note
The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).
Parameters
[in]oscOscillator ID. Only HSE and LSE have effect.

Definition at line 224 of file rcc_common_all.c.

References RCC_BDCR, RCC_BDCR_LSEBYP, RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_off()

void rcc_osc_off ( enum rcc_osc  osc)

Definition at line 227 of file rcc.c.

References RCC_BDCR, RCC_CR, RCC_CSR, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_clock_setup_hse_3v3().

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◆ rcc_osc_on()

void rcc_osc_on ( enum rcc_osc  osc)

Definition at line 206 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSEON, RCC_CR, RCC_CR_HSEON, RCC_CR_HSION, RCC_CR_PLLON, RCC_CSR, RCC_CSR_LSION, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_clock_setup_hse_3v3().

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◆ rcc_osc_ready_int_clear()

void rcc_osc_ready_int_clear ( enum rcc_osc  osc)

◆ rcc_osc_ready_int_disable()

void rcc_osc_ready_int_disable ( enum rcc_osc  osc)

Definition at line 109 of file rcc.c.

References RCC_CIR, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_osc_ready_int_enable()

void rcc_osc_ready_int_enable ( enum rcc_osc  osc)

◆ rcc_osc_ready_int_flag()

int rcc_osc_ready_int_flag ( enum rcc_osc  osc)

◆ rcc_periph_clock_disable()

void rcc_periph_clock_disable ( enum rcc_periph_clken  clken)

Disable Peripheral Clock in running mode.

Disable the clock on particular peripheral.

Parameters
[in]clkenrcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 148 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_periph_clock_enable()

void rcc_periph_clock_enable ( enum rcc_periph_clken  clken)

Enable Peripheral Clock in running mode.

Enable the clock on particular peripheral.

Parameters
[in]clkenrcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 134 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by stm32f107_usbd_init(), and stm32f207_usbd_init().

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◆ rcc_periph_reset_hold()

void rcc_periph_reset_hold ( enum rcc_periph_rst  rst)

Reset Peripheral, hold.

Reset particular peripheral, and hold in reset state.

Parameters
[in]rstrcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 179 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_pulse()

void rcc_periph_reset_pulse ( enum rcc_periph_rst  rst)

Reset Peripheral, pulsed.

Reset particular peripheral, and restore to working state.

Parameters
[in]rstrcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 163 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by i2c_reset(), and spi_reset().

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◆ rcc_periph_reset_release()

void rcc_periph_reset_release ( enum rcc_periph_rst  rst)

Reset Peripheral, release.

Restore peripheral from reset state to working state.

Parameters
[in]rstrcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 194 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_peripheral_clear_reset()

void rcc_peripheral_clear_reset ( volatile uint32_t *  reg,
uint32_t  clear_reset 
)

RCC Remove Reset on Peripherals.

Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.

See also
rcc_periph_reset_release for a less error prone version, if you only need to unreset a single peripheral.
rcc_periph_reset_pulse if you are only going to toggle reset anyway.
Parameters
[in]*regUnsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]clear_resetUnsigned int32. Logical OR of all resets to be removed:

Definition at line 116 of file rcc_common_all.c.

◆ rcc_peripheral_disable_clock()

void rcc_peripheral_disable_clock ( volatile uint32_t *  reg,
uint32_t  en 
)

RCC Disable Peripheral Clocks.

Disable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.

See also
rcc_periph_clock_disable for a less error prone version, if you only need to disable a single peripheral.
Parameters
[in]*regUnsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]enUnsigned int32. Logical OR of all enables to be used for disabling.

Definition at line 69 of file rcc_common_all.c.

◆ rcc_peripheral_enable_clock()

void rcc_peripheral_enable_clock ( volatile uint32_t *  reg,
uint32_t  en 
)

RCC Enable Peripheral Clocks.

Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.

See also
rcc_periph_clock_enable for a less error prone version, if you only need to enable a single peripheral.
Parameters
[in]*regUnsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]enUnsigned int32. Logical OR of all enables to be set

Definition at line 46 of file rcc_common_all.c.

◆ rcc_peripheral_reset()

void rcc_peripheral_reset ( volatile uint32_t *  reg,
uint32_t  reset 
)

RCC Reset Peripherals.

Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.

See also
rcc_periph_reset_hold for a less error prone version, if you only need to reset a single peripheral.
rcc_periph_reset_pulse if you are only going to toggle reset anyway.
Parameters
[in]*regUnsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]resetUnsigned int32. Logical OR of all resets.

Definition at line 92 of file rcc_common_all.c.

◆ rcc_set_hpre()

void rcc_set_hpre ( uint32_t  hpre)

Definition at line 294 of file rcc.c.

References rcc_clock_scale::hpre, and RCC_CFGR.

Referenced by rcc_clock_setup_hse_3v3().

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◆ rcc_set_main_pll_hse()

void rcc_set_main_pll_hse ( uint32_t  pllm,
uint32_t  plln,
uint32_t  pllp,
uint32_t  pllq 
)

◆ rcc_set_main_pll_hsi()

void rcc_set_main_pll_hsi ( uint32_t  pllm,
uint32_t  plln,
uint32_t  pllp,
uint32_t  pllq 
)

◆ rcc_set_mco()

void rcc_set_mco ( uint32_t  mcosrc)

Select the source of Microcontroller Clock Output.

Exact sources available depend on your target. On devices with multiple MCO pins, this function controls MCO1

Parameters
[in]mcosrcthe unshifted source bits

Definition at line 207 of file rcc_common_all.c.

References RCC_CFGR, RCC_CFGR_MCO_MASK, and RCC_CFGR_MCO_SHIFT.

◆ rcc_set_pll_source()

void rcc_set_pll_source ( uint32_t  pllsrc)

Definition at line 267 of file rcc.c.

References RCC_PLLCFGR.

◆ rcc_set_ppre1()

void rcc_set_ppre1 ( uint32_t  ppre1)

Definition at line 285 of file rcc.c.

References rcc_clock_scale::ppre1, and RCC_CFGR.

Referenced by rcc_clock_setup_hse_3v3().

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◆ rcc_set_ppre2()

void rcc_set_ppre2 ( uint32_t  ppre2)

Definition at line 276 of file rcc.c.

References rcc_clock_scale::ppre2, and RCC_CFGR.

Referenced by rcc_clock_setup_hse_3v3().

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◆ rcc_set_rtcpre()

void rcc_set_rtcpre ( uint32_t  rtcpre)

Definition at line 303 of file rcc.c.

References RCC_CFGR.

◆ rcc_set_sysclk_source()

void rcc_set_sysclk_source ( uint32_t  clk)

Definition at line 258 of file rcc.c.

References RCC_CFGR.

Referenced by rcc_clock_setup_hse_3v3().

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◆ rcc_system_clock_source()

uint32_t rcc_system_clock_source ( void  )

Definition at line 331 of file rcc.c.

References RCC_CFGR.

◆ rcc_wait_for_osc_ready()

void rcc_wait_for_osc_ready ( enum rcc_osc  osc)

Wait for Oscillator Ready.

Block until the hardware indicates that the Oscillator is ready.

Parameters
oscOscillator ID

Definition at line 180 of file rcc.c.

References rcc_is_osc_ready().

Referenced by rcc_clock_setup_hse_3v3().

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◆ rcc_wait_for_sysclk_status()

void rcc_wait_for_sysclk_status ( enum rcc_osc  osc)

Definition at line 185 of file rcc.c.

References RCC_CFGR, RCC_CFGR_SWS_HSE, RCC_CFGR_SWS_HSI, RCC_CFGR_SWS_MASK, RCC_CFGR_SWS_PLL, RCC_CFGR_SWS_SHIFT, RCC_HSE, RCC_HSI, and RCC_PLL.

Referenced by rcc_clock_setup_hse_3v3().

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Variable Documentation

◆ rcc_ahb_frequency

uint32_t rcc_ahb_frequency
extern

Definition at line 47 of file rcc.c.

◆ rcc_apb1_frequency

uint32_t rcc_apb1_frequency
extern

◆ rcc_apb2_frequency

uint32_t rcc_apb2_frequency
extern

◆ rcc_hse_8mhz_3v3

const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END]
extern

Definition at line 51 of file rcc.c.