libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.

Defined Constants and Types for the STM32F3xx Reset and Clock Control More...

Collaboration diagram for RCC Defines:

Modules

 PLL source predividers
 

Functions

void rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en)
 RCC Enable Peripheral Clocks. More...
 
void rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en)
 RCC Disable Peripheral Clocks. More...
 
void rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset)
 RCC Reset Peripherals. More...
 
void rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset)
 RCC Remove Reset on Peripherals. More...
 
void rcc_periph_clock_enable (enum rcc_periph_clken clken)
 Enable Peripheral Clock in running mode. More...
 
void rcc_periph_clock_disable (enum rcc_periph_clken clken)
 Disable Peripheral Clock in running mode. More...
 
void rcc_periph_reset_pulse (enum rcc_periph_rst rst)
 Reset Peripheral, pulsed. More...
 
void rcc_periph_reset_hold (enum rcc_periph_rst rst)
 Reset Peripheral, hold. More...
 
void rcc_periph_reset_release (enum rcc_periph_rst rst)
 Reset Peripheral, release. More...
 
void rcc_set_mco (uint32_t mcosrc)
 Select the source of Microcontroller Clock Output. More...
 
void rcc_osc_bypass_enable (enum rcc_osc osc)
 RCC Enable Bypass. More...
 
void rcc_osc_bypass_disable (enum rcc_osc osc)
 RCC Disable Bypass. More...
 
bool rcc_is_osc_ready (enum rcc_osc osc)
 Is the given oscillator ready? More...
 
void rcc_wait_for_osc_ready (enum rcc_osc osc)
 Wait for Oscillator Ready. More...
 
uint16_t rcc_get_div_from_hpre (uint8_t div_val)
 This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More...
 

Detailed Description

Defined Constants and Types for the STM32F3xx Reset and Clock Control

Author
© 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
© 2009 Uwe Hermann uwe@h.nosp@m.erma.nosp@m.nn-uw.nosp@m.e.de
© 2011 Fergus Noble fergu.nosp@m.snob.nosp@m.le@gm.nosp@m.ail..nosp@m.com
© 2011 Stephen Caudle scaud.nosp@m.le@d.nosp@m.oceme.nosp@m..com
© 2013 Fernando Cortes ferna.nosp@m.ndo..nosp@m.corca.nosp@m.m@gm.nosp@m.ail.c.nosp@m.om
© 2013 Guillermo Rivera memog.nosp@m.rg@g.nosp@m.mail..nosp@m.com
Version
1.0.0
Date
11 July 2013

LGPL License Terms libopencm3 License

Author
© 2013 Frantisek Burian BuFra.nosp@m.n@se.nosp@m.znam..nosp@m.cz

Function Documentation

◆ rcc_get_div_from_hpre()

uint16_t rcc_get_div_from_hpre ( uint8_t  div_val)

This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.

Parameters
div_valMasked and shifted divider value from register (e.g. RCC_CFGR)

Definition at line 260 of file rcc_common_all.c.

Referenced by rcc_get_i2c_clk_freq(), and rcc_get_usart_clksel_freq().

Here is the caller graph for this function:

◆ rcc_is_osc_ready()

bool rcc_is_osc_ready ( enum rcc_osc  osc)

Is the given oscillator ready?

Parameters
oscOscillator ID
Returns
true if the hardware indicates the oscillator is ready.

Definition at line 184 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSERDY, RCC_CR, RCC_CR_HSERDY, RCC_CR_HSIRDY, RCC_CR_PLLRDY, RCC_CSR, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_wait_for_osc_not_ready(), and rcc_wait_for_osc_ready().

Here is the caller graph for this function:

◆ rcc_osc_bypass_disable()

void rcc_osc_bypass_disable ( enum rcc_osc  osc)

RCC Disable Bypass.

Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note
The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see rcc_backupdomain_reset).
Parameters
[in]oscOscillator ID. Only HSE and LSE have effect.

Definition at line 238 of file rcc_common_all.c.

References RCC_BDCR, RCC_CR, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_bypass_enable()

void rcc_osc_bypass_enable ( enum rcc_osc  osc)

RCC Enable Bypass.

Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note
The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).
Parameters
[in]oscOscillator ID. Only HSE and LSE have effect.

Definition at line 208 of file rcc_common_all.c.

References RCC_BDCR, RCC_BDCR_LSEBYP, RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_periph_clock_disable()

void rcc_periph_clock_disable ( enum rcc_periph_clken  clken)

Disable Peripheral Clock in running mode.

Disable the clock on particular peripheral.

Parameters
[in]clkenrcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 139 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_periph_clock_enable()

void rcc_periph_clock_enable ( enum rcc_periph_clken  clken)

Enable Peripheral Clock in running mode.

Enable the clock on particular peripheral.

Parameters
[in]clkenrcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 127 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by st_usbfs_v1_usbd_init().

Here is the caller graph for this function:

◆ rcc_periph_reset_hold()

void rcc_periph_reset_hold ( enum rcc_periph_rst  rst)

Reset Peripheral, hold.

Reset particular peripheral, and hold in reset state.

Parameters
[in]rstrcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 166 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_pulse()

void rcc_periph_reset_pulse ( enum rcc_periph_rst  rst)

Reset Peripheral, pulsed.

Reset particular peripheral, and restore to working state.

Parameters
[in]rstrcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 152 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by can_reset().

Here is the caller graph for this function:

◆ rcc_periph_reset_release()

void rcc_periph_reset_release ( enum rcc_periph_rst  rst)

Reset Peripheral, release.

Restore peripheral from reset state to working state.

Parameters
[in]rstrcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 179 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_peripheral_clear_reset()

void rcc_peripheral_clear_reset ( volatile uint32_t *  reg,
uint32_t  clear_reset 
)

RCC Remove Reset on Peripherals.

Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.

See also
rcc_periph_reset_release for a less error prone version, if you only need to unreset a single peripheral.
rcc_periph_reset_pulse if you are only going to toggle reset anyway.
Parameters
[in]*regUnsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]clear_resetUnsigned int32. Logical OR of all resets to be removed:

Definition at line 111 of file rcc_common_all.c.

◆ rcc_peripheral_disable_clock()

void rcc_peripheral_disable_clock ( volatile uint32_t *  reg,
uint32_t  en 
)

RCC Disable Peripheral Clocks.

Disable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.

See also
rcc_periph_clock_disable for a less error prone version, if you only need to disable a single peripheral.
Parameters
[in]*regUnsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]enUnsigned int32. Logical OR of all enables to be used for disabling.

Definition at line 66 of file rcc_common_all.c.

◆ rcc_peripheral_enable_clock()

void rcc_peripheral_enable_clock ( volatile uint32_t *  reg,
uint32_t  en 
)

RCC Enable Peripheral Clocks.

Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.

See also
rcc_periph_clock_enable for a less error prone version, if you only need to enable a single peripheral.
Parameters
[in]*regUnsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]enUnsigned int32. Logical OR of all enables to be set

Definition at line 44 of file rcc_common_all.c.

◆ rcc_peripheral_reset()

void rcc_peripheral_reset ( volatile uint32_t *  reg,
uint32_t  reset 
)

RCC Reset Peripherals.

Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.

See also
rcc_periph_reset_hold for a less error prone version, if you only need to reset a single peripheral.
rcc_periph_reset_pulse if you are only going to toggle reset anyway.
Parameters
[in]*regUnsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]resetUnsigned int32. Logical OR of all resets.

Definition at line 88 of file rcc_common_all.c.

◆ rcc_set_mco()

void rcc_set_mco ( uint32_t  mcosrc)

Select the source of Microcontroller Clock Output.

Exact sources available depend on your target. On devices with multiple MCO pins, this function controls MCO1

Parameters
[in]mcosrcthe unshifted source bits

Definition at line 191 of file rcc_common_all.c.

References RCC_CFGR, RCC_CFGR_MCO_MASK, and RCC_CFGR_MCO_SHIFT.

◆ rcc_wait_for_osc_ready()

void rcc_wait_for_osc_ready ( enum rcc_osc  osc)

Wait for Oscillator Ready.

Block until the hardware indicates that the Oscillator is ready.

Parameters
oscOscillator ID

Definition at line 201 of file rcc.c.

References rcc_is_osc_ready().

Referenced by rcc_clock_setup_hsi(), and rcc_clock_setup_pll().

Here is the call graph for this function:
Here is the caller graph for this function: