libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
dma_common_f24.c
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1/** @defgroup dma_file DMA peripheral API
2@ingroup peripheral_apis
3@brief DMA library for the multi stream controller found in f2/f4/f7 parts.
4
5@author @htmlonly © @endhtmlonly 2012
6Ken Sarkies <ksarkies@internode.on.net>
7
8This library supports the DMA Control System in the STM32F2 and STM32F4
9series of ARM Cortex Microcontrollers by ST Microelectronics.
10
11Up to two DMA controllers are supported each with 8 streams, and each stream
12having up to 8 channels hardware dedicated to various peripheral DMA signals.
13
14DMA transfers can be configured to occur between peripheral and memory in
15either direction, and memory to memory. Peripheral to peripheral transfer
16is not supported. Circular mode transfers are also supported in transfers
17involving a peripheral. An arbiter is provided to resolve priority DMA
18requests. Transfers can be made with 8, 16 or 32 bit words.
19
20Each stream has access to a 4 word deep FIFO and can use double buffering
21by means of two memory pointers. When using the FIFO it is possible to
22configure transfers to occur in indivisible bursts.
23
24It is also possible to select a peripheral instead of the DMA controller to
25control the flow of data. This limits the functionality but is useful when the
26number of transfers is unknown.
27
28LGPL License Terms @ref lgpl_license
29 */
30/*
31 * This file is part of the libopencm3 project.
32 *
33 * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
34 *
35 * This library is free software: you can redistribute it and/or modify
36 * it under the terms of the GNU Lesser General Public License as published by
37 * the Free Software Foundation, either version 3 of the License, or
38 * (at your option) any later version.
39 *
40 * This library is distributed in the hope that it will be useful,
41 * but WITHOUT ANY WARRANTY; without even the implied warranty of
42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
43 * GNU Lesser General Public License for more details.
44 *
45 * You should have received a copy of the GNU Lesser General Public License
46 * along with this library. If not, see <http://www.gnu.org/licenses/>.
47 */
48
49/**@{*/
50
52
53/*---------------------------------------------------------------------------*/
54/** @brief DMA Stream Reset
55
56The specified stream is disabled and configuration registers are cleared.
57
58@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
59@param[in] stream unsigned int8. Stream number: @ref dma_st_number
60*/
61
62void dma_stream_reset(uint32_t dma, uint8_t stream)
63{
64/* Disable stream (must be done before register is otherwise changed). */
65 DMA_SCR(dma, stream) &= ~DMA_SxCR_EN;
66/* Reset all config bits. */
67 DMA_SCR(dma, stream) = 0;
68/* Reset data transfer number. */
69 DMA_SNDTR(dma, stream) = 0;
70/* Reset peripheral and memory addresses. */
71 DMA_SPAR(dma, stream) = 0;
72 DMA_SM0AR(dma, stream) = 0;
73 DMA_SM1AR(dma, stream) = 0;
74/* This is the default setting */
75 DMA_SFCR(dma, stream) = 0x21;
76/* Reset all stream interrupt flags using the interrupt flag clear register. */
77 uint32_t mask = DMA_ISR_MASK(stream);
78 if (stream < 4) {
79 DMA_LIFCR(dma) |= mask;
80 } else {
81 DMA_HIFCR(dma) |= mask;
82 }
83}
84
85/*---------------------------------------------------------------------------*/
86/** @brief DMA Stream Clear Interrupt Flag
87
88The interrupt flag for the stream is cleared. More than one interrupt for the
89same stream may be cleared by using the bitwise OR of the interrupt flags.
90
91@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
92@param[in] stream unsigned int8. Stream number: @ref dma_st_number
93@param[in] interrupts unsigned int32. Bitwise OR of interrupt numbers: @ref
94dma_if_offset
95*/
96
97void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream,
98 uint32_t interrupts)
99{
100 /* Get offset to interrupt flag location in stream field */
101 uint32_t flags = (interrupts << DMA_ISR_OFFSET(stream));
102 /* First four streams are in low register. Flag clear must be set then
103 * reset.
104 */
105 if (stream < 4) {
106 DMA_LIFCR(dma) = flags;
107 } else {
108 DMA_HIFCR(dma) = flags;
109 }
110}
111
112/*---------------------------------------------------------------------------*/
113/** @brief DMA Stream Read Interrupt Flag
114
115The interrupt flag for the stream is returned.
116
117@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
118@param[in] stream unsigned int8. Stream number: @ref dma_st_number
119@param[in] interrupt unsigned int32. Interrupt number: @ref dma_if_offset
120@returns bool interrupt flag is set.
121*/
122
123bool dma_get_interrupt_flag(uint32_t dma, uint8_t stream, uint32_t interrupt)
124{
125 /* get offset to interrupt flag location in stream field. Assumes
126 * stream and interrupt parameters are integers.
127 */
128 uint32_t flag = (interrupt << DMA_ISR_OFFSET(stream));
129 /* First four streams are in low register */
130 if (stream < 4) {
131 return ((DMA_LISR(dma) & flag) > 0);
132 } else {
133 return ((DMA_HISR(dma) & flag) > 0);
134 }
135}
136
137/*---------------------------------------------------------------------------*/
138/** @brief DMA Stream Enable Transfer Direction
139
140Set peripheral to memory, memory to peripheral or memory to memory. If memory
141to memory mode is selected, circular mode and double buffer modes are disabled.
142Ensure that these modes are not enabled at a later time.
143
144Ensure that the stream is disabled otherwise the setting will not be changed.
145
146@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
147@param[in] stream unsigned int8. Stream number: @ref dma_st_number
148@param[in] direction unsigned int32. Data transfer direction @ref dma_st_dir
149*/
150
151void dma_set_transfer_mode(uint32_t dma, uint8_t stream, uint32_t direction)
152{
153 uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_DIR_MASK);
154 /* Disable circular and double buffer modes if memory to memory
155 * transfers are in effect. (Direct Mode is automatically disabled by
156 * hardware)
157 */
158 if (direction == DMA_SxCR_DIR_MEM_TO_MEM) {
159 reg32 &= ~(DMA_SxCR_CIRC | DMA_SxCR_DBM);
160 }
161
162 DMA_SCR(dma, stream) = (reg32 | direction);
163}
164
165/*---------------------------------------------------------------------------*/
166/** @brief DMA Stream Set Priority
167
168Stream Priority has four levels: low to very high. This has precedence over the
169hardware priority. In the event of equal software priority the lower numbered
170stream has priority.
171
172Ensure that the stream is disabled otherwise the setting will not be changed.
173
174@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
175@param[in] stream unsigned int8. Stream number: @ref dma_st_number
176@param[in] prio unsigned int32. Priority level @ref dma_st_pri.
177*/
178
179void dma_set_priority(uint32_t dma, uint8_t stream, uint32_t prio)
180{
181 DMA_SCR(dma, stream) &= ~(DMA_SxCR_PL_MASK);
182 DMA_SCR(dma, stream) |= prio;
183}
184
185/*---------------------------------------------------------------------------*/
186/** @brief DMA Stream Set Memory Word Width
187
188Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
189alignment information if the source and destination widths do not match.
190
191Ensure that the stream is disabled otherwise the setting will not be changed.
192
193@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
194@param[in] stream unsigned int8. Stream number: @ref dma_st_number
195@param[in] mem_size unsigned int32. Memory word width @ref dma_st_memwidth.
196*/
197
198void dma_set_memory_size(uint32_t dma, uint8_t stream, uint32_t mem_size)
199{
200 DMA_SCR(dma, stream) &= ~(DMA_SxCR_MSIZE_MASK);
201 DMA_SCR(dma, stream) |= mem_size;
202}
203
204/*---------------------------------------------------------------------------*/
205/** @brief DMA Stream Set Peripheral Word Width
206
207Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet
208for alignment information if the source and destination widths do not match, or
209if the peripheral does not support byte or half-word writes.
210
211Ensure that the stream is disabled otherwise the setting will not be changed.
212
213@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
214@param[in] stream unsigned int8. Stream number: @ref dma_st_number
215@param[in] peripheral_size unsigned int32. Peripheral word width @ref
216dma_st_perwidth.
217*/
218
219void dma_set_peripheral_size(uint32_t dma, uint8_t stream,
220 uint32_t peripheral_size)
221{
222 DMA_SCR(dma, stream) &= ~(DMA_SxCR_PSIZE_MASK);
223 DMA_SCR(dma, stream) |= peripheral_size;
224}
225
226/*---------------------------------------------------------------------------*/
227/** @brief DMA Stream Enable Memory Increment after Transfer
228
229Following each transfer the current memory address is incremented by
2301, 2 or 4 depending on the data size set in @ref dma_set_memory_size. The
231value held by the base memory address register is unchanged.
232
233Ensure that the stream is disabled otherwise the setting will not be changed.
234
235@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
236@param[in] stream unsigned int8. Stream number: @ref dma_st_number
237*/
238
239void dma_enable_memory_increment_mode(uint32_t dma, uint8_t stream)
240{
241 DMA_SCR(dma, stream) |= DMA_SxCR_MINC;
242}
243
244/*---------------------------------------------------------------------------*/
245/** @brief DMA Channel Disable Memory Increment after Transfer
246
247Ensure that the stream is disabled otherwise the setting will not be changed.
248
249@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
250@param[in] stream unsigned int8. Stream number: @ref dma_st_number
251*/
252
253void dma_disable_memory_increment_mode(uint32_t dma, uint8_t stream)
254{
255 DMA_SCR(dma, stream) &= ~DMA_SxCR_MINC;
256}
257
258/*---------------------------------------------------------------------------*/
259/** @brief DMA Channel Enable Variable Sized Peripheral Increment after Transfer
260
261Following each transfer the current peripheral address is incremented by
2621, 2 or 4 depending on the data size set in @ref dma_set_peripheral_size. The
263value held by the base peripheral address register is unchanged.
264
265Ensure that the stream is disabled otherwise the setting will not be changed.
266
267@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
268@param[in] stream unsigned int8. Stream number: @ref dma_st_number
269*/
270
271void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t stream)
272{
273 uint32_t reg32 = (DMA_SCR(dma, stream) | DMA_SxCR_PINC);
274 DMA_SCR(dma, stream) = (reg32 & ~DMA_SxCR_PINCOS);
275}
276
277/*---------------------------------------------------------------------------*/
278/** @brief DMA Channel Disable Peripheral Increment after Transfer
279
280Ensure that the stream is disabled otherwise the setting will not be changed.
281
282@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
283@param[in] stream unsigned int8. Stream number: @ref dma_st_number
284*/
285
286void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t stream)
287{
288 DMA_SCR(dma, stream) &= ~DMA_SxCR_PINC;
289}
290
291/*---------------------------------------------------------------------------*/
292/** @brief DMA Channel Enable Fixed Sized Peripheral Increment after Transfer
293
294Following each transfer the current peripheral address is incremented by
2954 regardless of the data size. The value held by the base peripheral address
296register is unchanged.
297
298Ensure that the stream is disabled otherwise the setting will not be changed.
299
300@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
301@param[in] stream unsigned int8. Stream number: @ref dma_st_number
302*/
303
304void dma_enable_fixed_peripheral_increment_mode(uint32_t dma, uint8_t stream)
305{
306 DMA_SCR(dma, stream) |= (DMA_SxCR_PINC | DMA_SxCR_PINCOS);
307}
308
309/*---------------------------------------------------------------------------*/
310/** @brief DMA Stream Enable Memory Circular Mode
311
312After the number of bytes/words to be transferred has been completed, the
313original transfer block size, memory and peripheral base addresses are
314reloaded and the process repeats.
315
316Ensure that the stream is disabled otherwise the setting will not be changed.
317
318@note This cannot be used with memory to memory mode. It is disabled
319automatically if the peripheral is selected as the flow controller.
320It is enabled automatically if double buffered mode is selected.
321
322@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
323@param[in] stream unsigned int8. Stream number: @ref dma_st_number
324*/
325
326void dma_enable_circular_mode(uint32_t dma, uint8_t stream)
327{
328 DMA_SCR(dma, stream) |= DMA_SxCR_CIRC;
329}
330
331/*---------------------------------------------------------------------------*/
332/** @brief DMA Stream Channel Select
333
334Associate an input channel to the stream. Not every channel is allocated to a
335hardware DMA request signal. The allocations for each stream are given in the
336STM32F4 Reference Manual.
337
338Ensure that the stream is disabled otherwise the setting will not be changed.
339
340@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
341@param[in] stream unsigned int8. Stream number: @ref dma_st_number
342@param[in] channel unsigned int8. Channel selection @ref dma_ch_sel
343*/
344
345void dma_channel_select(uint32_t dma, uint8_t stream, uint32_t channel)
346{
347 DMA_SCR(dma, stream) |= channel;
348}
349
350/*---------------------------------------------------------------------------*/
351/** @brief DMA Stream Set Memory Burst Configuration
352
353Set the memory burst type to none, 4 8 or 16 word length. This is forced to none
354if direct mode is used.
355
356Ensure that the stream is disabled otherwise the setting will not be changed.
357
358@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
359@param[in] stream unsigned int8. Stream number: @ref dma_st_number
360@param[in] burst unsigned int8. Memory Burst selection @ref dma_mburst
361*/
362
363void dma_set_memory_burst(uint32_t dma, uint8_t stream, uint32_t burst)
364{
365 uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_MBURST_MASK);
366 DMA_SCR(dma, stream) = (reg32 | burst);
367}
368
369/*---------------------------------------------------------------------------*/
370/** @brief DMA Stream Set Peripheral Burst Configuration
371
372Set the memory burst type to none, 4 8 or 16 word length. This is forced to none
373if direct mode is used.
374
375Ensure that the stream is disabled otherwise the setting will not be changed.
376
377@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
378@param[in] stream unsigned int8. Stream number: @ref dma_st_number
379@param[in] burst unsigned int8. Peripheral Burst selection @ref dma_pburst
380*/
381
382void dma_set_peripheral_burst(uint32_t dma, uint8_t stream, uint32_t burst)
383{
384 uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_PBURST_MASK);
385 DMA_SCR(dma, stream) = (reg32 | burst);
386}
387
388/*---------------------------------------------------------------------------*/
389/** @brief DMA Stream Set Initial Target Memory
390
391In double buffered mode, set the target memory (M0 or M1) to be used for the
392first transfer.
393
394Ensure that the stream is disabled otherwise the setting will not be changed.
395
396@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
397@param[in] stream unsigned int8. Stream number: @ref dma_st_number
398@param[in] memory unsigned int8. Initial memory pointer to use: 0 or 1
399*/
400
401void dma_set_initial_target(uint32_t dma, uint8_t stream, uint8_t memory)
402{
403 uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_CT);
404 if (memory == 1) {
405 reg32 |= DMA_SxCR_CT;
406 }
407
408 DMA_SCR(dma, stream) = reg32;
409}
410
411/*---------------------------------------------------------------------------*/
412/** @brief DMA Stream Read Current Memory Target
413
414In double buffer mode, return the current memory target (M0 or M1). It is
415possible to update the memory pointer in the register that is <b> not </b>
416currently in use. An attempt to change the register currently in use will cause
417the stream to be disabled and the transfer error flag to be set.
418
419@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
420@param[in] stream unsigned int8. Stream number: @ref dma_st_number
421@returns unsigned int8. Memory buffer in use: 0 or 1
422*/
423
424uint8_t dma_get_target(uint32_t dma, uint8_t stream)
425{
426 if (DMA_SCR(dma, stream) & DMA_SxCR_CT) {
427 return 1;
428 }
429
430 return 0;
431}
432
433/*---------------------------------------------------------------------------*/
434/** @brief DMA Stream Enable Double Buffer Mode
435
436Double buffer mode is used for memory to/from peripheral transfers only, and in
437circular mode which is automatically enabled. Two memory buffers must be
438established with pointers stored in the memory pointer registers.
439
440Ensure that the stream is disabled otherwise the setting will not be changed.
441
442@note This cannot be used with memory to memory mode.
443
444@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
445@param[in] stream unsigned int8. Stream number: @ref dma_st_number
446*/
447
448void dma_enable_double_buffer_mode(uint32_t dma, uint8_t stream)
449{
450 DMA_SCR(dma, stream) |= DMA_SxCR_DBM;
451}
452
453/*---------------------------------------------------------------------------*/
454/** @brief DMA Stream Disable Double Buffer Mode
455
456@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
457@param[in] stream unsigned int8. Stream number: @ref dma_st_number
458*/
459
460void dma_disable_double_buffer_mode(uint32_t dma, uint8_t stream)
461{
462 DMA_SCR(dma, stream) &= ~DMA_SxCR_DBM;
463}
464
465/*---------------------------------------------------------------------------*/
466/** @brief DMA Stream Set Peripheral Flow Control
467
468Set the peripheral to control DMA flow. Useful when the number of transfers is
469unknown. This is forced off when memory to memory mode is selected.
470
471Ensure that the stream is disabled otherwise the setting will not be changed.
472
473@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
474@param[in] stream unsigned int8. Stream number: @ref dma_st_number
475*/
476
477void dma_set_peripheral_flow_control(uint32_t dma, uint8_t stream)
478{
479 DMA_SCR(dma, stream) |= DMA_SxCR_PFCTRL;
480}
481
482/*---------------------------------------------------------------------------*/
483/** @brief DMA Stream Set DMA Flow Control
484
485Set the DMA controller to control DMA flow. This is the default.
486
487Ensure that the stream is disabled otherwise the setting will not be changed.
488
489@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
490@param[in] stream unsigned int8. Stream number: @ref dma_st_number
491*/
492
493void dma_set_dma_flow_control(uint32_t dma, uint8_t stream)
494{
495 DMA_SCR(dma, stream) &= ~DMA_SxCR_PFCTRL;
496}
497
498/*---------------------------------------------------------------------------*/
499/** @brief DMA Stream Enable Interrupt on Transfer Error
500
501@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
502@param[in] stream unsigned int8. Stream number: @ref dma_st_number
503*/
504
505void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t stream)
506{
508 DMA_SCR(dma, stream) |= DMA_SxCR_TEIE;
509}
510
511/*---------------------------------------------------------------------------*/
512/** @brief DMA Stream Disable Interrupt on Transfer Error
513
514@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
515@param[in] stream unsigned int8. Stream number: @ref dma_st_number
516*/
517
518void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t stream)
519{
520 DMA_SCR(dma, stream) &= ~DMA_SxCR_TEIE;
521}
522
523/*---------------------------------------------------------------------------*/
524/** @brief DMA Stream Enable Interrupt on Transfer Half Complete
525
526@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
527@param[in] stream unsigned int8. Stream number: @ref dma_st_number
528*/
529
530void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t stream)
531{
533 DMA_SCR(dma, stream) |= DMA_SxCR_HTIE;
534}
535
536/*---------------------------------------------------------------------------*/
537/** @brief DMA Stream Disable Interrupt on Transfer Half Complete
538
539@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
540@param[in] stream unsigned int8. Stream number: @ref dma_st_number
541*/
542
543void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t stream)
544{
545 DMA_SCR(dma, stream) &= ~DMA_SxCR_HTIE;
546}
547
548/*---------------------------------------------------------------------------*/
549/** @brief DMA Stream Enable Interrupt on Transfer Complete
550
551@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
552@param[in] stream unsigned int8. Stream number: @ref dma_st_number
553*/
554
555void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream)
556{
558 DMA_SCR(dma, stream) |= DMA_SxCR_TCIE;
559}
560
561/*---------------------------------------------------------------------------*/
562/** @brief DMA Stream Disable Interrupt on Transfer Complete
563
564@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
565@param[in] stream unsigned int8. Stream number: @ref dma_st_number
566*/
567
568void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream)
569{
570 DMA_SCR(dma, stream) &= ~DMA_SxCR_TCIE;
571}
572
573/*---------------------------------------------------------------------------*/
574/** @brief DMA Stream Enable Interrupt on Direct Mode Error
575
576@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
577@param[in] stream unsigned int8. Stream number: @ref dma_st_number
578*/
579
580void dma_enable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream)
581{
583 DMA_SCR(dma, stream) |= DMA_SxCR_DMEIE;
584}
585
586/*---------------------------------------------------------------------------*/
587/** @brief DMA Stream Disable Interrupt on Direct Mode Error
588
589@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
590@param[in] stream unsigned int8. Stream number: @ref dma_st_number
591*/
592
593void dma_disable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream)
594{
595 DMA_SCR(dma, stream) &= ~DMA_SxCR_DMEIE;
596}
597
598/*---------------------------------------------------------------------------*/
599/** @brief DMA Enable Interrupt on FIFO Error
600
601@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
602@param[in] stream unsigned int8. Stream number: @ref dma_st_number
603*/
604
605void dma_enable_fifo_error_interrupt(uint32_t dma, uint8_t stream)
606{
608 DMA_SFCR(dma, stream) |= DMA_SxFCR_FEIE;
609}
610
611/*---------------------------------------------------------------------------*/
612/** @brief DMA Disable Interrupt on FIFO Error
613
614@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
615@param[in] stream unsigned int8. Stream number: @ref dma_st_number
616*/
617
618void dma_disable_fifo_error_interrupt(uint32_t dma, uint8_t stream)
619{
620 DMA_SFCR(dma, stream) &= ~DMA_SxFCR_FEIE;
621}
622
623/*---------------------------------------------------------------------------*/
624/** @brief DMA Get FIFO Status
625
626Status of FIFO (empty. full or partial filled states) is returned. This has no
627meaning if direct mode is enabled (as the FIFO is not used).
628
629@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
630@param[in] stream unsigned int8. Stream number: @ref dma_st_number
631@returns uint32_t FIFO Status @ref dma_fifo_status
632*/
633
634uint32_t dma_fifo_status(uint32_t dma, uint8_t stream)
635{
636 return DMA_SFCR(dma, stream) & DMA_SxFCR_FS_MASK;
637}
638
639/*---------------------------------------------------------------------------*/
640/** @brief DMA Enable Direct Mode
641
642Direct mode is the default. Data is transferred as soon as a DMA request is
643received. The FIFO is not used. This must not be set when memory to memory
644mode is selected.
645
646@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
647@param[in] stream unsigned int8. Stream number: @ref dma_st_number
648*/
649
650void dma_enable_direct_mode(uint32_t dma, uint8_t stream)
651{
652 DMA_SFCR(dma, stream) &= ~DMA_SxFCR_DMDIS;
653}
654
655/*---------------------------------------------------------------------------*/
656/** @brief DMA Enable FIFO Mode
657
658Data is transferred via a FIFO.
659
660@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
661@param[in] stream unsigned int8. Stream number: @ref dma_st_number
662*/
663
664void dma_enable_fifo_mode(uint32_t dma, uint8_t stream)
665{
666 DMA_SFCR(dma, stream) |= DMA_SxFCR_DMDIS;
667}
668
669/*---------------------------------------------------------------------------*/
670/** @brief DMA Set FIFO Threshold
671
672This is the filled level at which data is transferred out of the FIFO to the
673destination.
674
675@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
676@param[in] stream unsigned int8. Stream number: @ref dma_st_number
677@param[in] threshold unsigned int8. Threshold setting @ref dma_fifo_thresh
678*/
679
680void dma_set_fifo_threshold(uint32_t dma, uint8_t stream, uint32_t threshold)
681{
682 uint32_t reg32 = (DMA_SFCR(dma, stream) & ~DMA_SxFCR_FTH_MASK);
683 DMA_SFCR(dma, stream) = (reg32 | threshold);
684}
685
686/*---------------------------------------------------------------------------*/
687/** @brief DMA Stream Enable
688
689@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
690@param[in] stream unsigned int8. Stream number: @ref dma_st_number
691*/
692
693void dma_enable_stream(uint32_t dma, uint8_t stream)
694{
695 DMA_SCR(dma, stream) |= DMA_SxCR_EN;
696}
697
698/*---------------------------------------------------------------------------*/
699/** @brief DMA Stream Disable
700
701@note The DMA stream registers retain their values when the stream is disabled.
702
703@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
704@param[in] stream unsigned int8. Stream number: @ref dma_st_number
705*/
706
707void dma_disable_stream(uint32_t dma, uint8_t stream)
708{
709 DMA_SCR(dma, stream) &= ~DMA_SxCR_EN;
710}
711
712/*---------------------------------------------------------------------------*/
713/** @brief DMA Stream Set the Peripheral Address
714
715Set the address of the peripheral register to or from which data is to be
716transferred. Refer to the documentation for the specific peripheral.
717
718@note The DMA stream must be disabled before setting this address. This function
719has no effect if the stream is enabled.
720
721@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
722@param[in] stream unsigned int8. Stream number: @ref dma_st_number
723@param[in] address unsigned int32. Peripheral Address.
724*/
725
726void dma_set_peripheral_address(uint32_t dma, uint8_t stream, uint32_t address)
727{
728 if (!(DMA_SCR(dma, stream) & DMA_SxCR_EN)) {
729 DMA_SPAR(dma, stream) = (uint32_t *) address;
730 }
731}
732
733/*---------------------------------------------------------------------------*/
734/** @brief DMA Stream Set the Base Memory Address 0
735
736Set the address pointer to the memory location for DMA transfers. The DMA stream
737must normally be disabled before setting this address, however it is possible
738to change this in double buffer mode when the current target is memory area 1
739(see @ref dma_get_target).
740
741This is the default base memory address used in direct mode.
742
743@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
744@param[in] stream unsigned int8. Stream number: @ref dma_st_number
745@param[in] address unsigned int32. Memory Initial Address.
746*/
747
748void dma_set_memory_address(uint32_t dma, uint8_t stream, uint32_t address)
749{
750 uint32_t reg32 = DMA_SCR(dma, stream);
751 if (!(reg32 & DMA_SxCR_EN) ||
752 ((reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) {
753 DMA_SM0AR(dma, stream) = (uint32_t *) address;
754 }
755}
756
757/*---------------------------------------------------------------------------*/
758/** @brief DMA Stream Set the Base Memory Address 1
759
760Set the address pointer to the memory location for DMA transfers. The DMA stream
761must normally be disabled before setting this address, however it is possible
762to change this in double buffer mode when the current target is memory area 0
763(see @ref dma_get_target).
764
765@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
766@param[in] stream unsigned int8. Stream number: @ref dma_st_number
767@param[in] address unsigned int32. Memory Initial Address.
768*/
769
770void dma_set_memory_address_1(uint32_t dma, uint8_t stream, uint32_t address)
771{
772 uint32_t reg32 = DMA_SCR(dma, stream);
773 if (!(reg32 & DMA_SxCR_EN) ||
774 (!(reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) {
775 DMA_SM1AR(dma, stream) = (uint32_t *) address;
776 }
777}
778
779/*---------------------------------------------------------------------------*/
780/** @brief DMA Stream Get the Transfer Block Size
781
782@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
783@param[in] stream unsigned int8. Stream number: @ref dma_st_number
784@returns unsigned int16. Number of remaining data words to transfer (65535
785maximum).
786*/
787
788uint16_t dma_get_number_of_data(uint32_t dma, uint8_t stream)
789{
790 return DMA_SNDTR(dma, stream);
791}
792
793/*---------------------------------------------------------------------------*/
794/** @brief DMA Stream Set the Transfer Block Size
795
796@note The DMA stream must be disabled before setting this count value. The count
797is not changed if the stream is enabled.
798
799@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
800@param[in] stream unsigned int8. Stream number: @ref dma_st_number
801@param[in] number unsigned int16. Number of data words to transfer (65535
802maximum).
803*/
804
805void dma_set_number_of_data(uint32_t dma, uint8_t stream, uint16_t number)
806{
807 DMA_SNDTR(dma, stream) = number;
808}
809/**@}*/
810
#define DMA_SFCR(port, n)
#define DMA_SxCR_PFCTRL
#define DMA_SxCR_HTIE
#define DMA_LISR(port)
#define DMA_SM1AR(port, n)
#define DMA_SxCR_PINC
#define DMA_SM0AR(port, n)
#define DMA_HIFCR(port)
#define DMA_ISR_MASK(stream)
#define DMA_SxCR_MSIZE_MASK
#define DMA_SxCR_DBM
#define DMA_LIFCR(port)
#define DMA_SxCR_TCIE
#define DMA_HISR(port)
#define DMA_SxCR_MINC
#define DMA_SCR(port, n)
#define DMA_SxFCR_DMDIS
#define DMA_SxCR_PL_MASK
#define DMA_SxCR_EN
#define DMA_SxFCR_FEIE
#define DMA_ISR_OFFSET(stream)
#define DMA_SxCR_PSIZE_MASK
#define DMA_SxCR_DMEIE
#define DMA_SxFCR_FS_MASK
#define DMA_SxCR_CIRC
#define DMA_SxCR_CT
#define DMA_SxCR_PINCOS
#define DMA_SxCR_TEIE
#define DMA_SNDTR(port, n)
#define DMA_SPAR(port, n)
void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t stream)
DMA Stream Enable Interrupt on Transfer Half Complete.
uint16_t dma_get_number_of_data(uint32_t dma, uint8_t stream)
DMA Stream Get the Transfer Block Size.
void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream)
DMA Stream Enable Interrupt on Transfer Complete.
void dma_enable_fixed_peripheral_increment_mode(uint32_t dma, uint8_t stream)
DMA Channel Enable Fixed Sized Peripheral Increment after Transfer.
void dma_set_memory_burst(uint32_t dma, uint8_t stream, uint32_t burst)
DMA Stream Set Memory Burst Configuration.
void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t stream)
DMA Stream Disable Interrupt on Transfer Error.
void dma_set_transfer_mode(uint32_t dma, uint8_t stream, uint32_t direction)
DMA Stream Enable Transfer Direction.
void dma_channel_select(uint32_t dma, uint8_t stream, uint32_t channel)
DMA Stream Channel Select.
void dma_set_fifo_threshold(uint32_t dma, uint8_t stream, uint32_t threshold)
DMA Set FIFO Threshold.
void dma_enable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream)
DMA Stream Enable Interrupt on Direct Mode Error.
void dma_disable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream)
DMA Stream Disable Interrupt on Direct Mode Error.
void dma_set_peripheral_size(uint32_t dma, uint8_t stream, uint32_t peripheral_size)
DMA Stream Set Peripheral Word Width.
void dma_set_priority(uint32_t dma, uint8_t stream, uint32_t prio)
DMA Stream Set Priority.
void dma_set_memory_address_1(uint32_t dma, uint8_t stream, uint32_t address)
DMA Stream Set the Base Memory Address 1.
void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t stream)
DMA Channel Enable Variable Sized Peripheral Increment after Transfer.
void dma_disable_stream(uint32_t dma, uint8_t stream)
DMA Stream Disable.
void dma_enable_fifo_mode(uint32_t dma, uint8_t stream)
DMA Enable FIFO Mode.
void dma_enable_double_buffer_mode(uint32_t dma, uint8_t stream)
DMA Stream Enable Double Buffer Mode.
void dma_enable_direct_mode(uint32_t dma, uint8_t stream)
DMA Enable Direct Mode.
void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t stream)
DMA Stream Enable Interrupt on Transfer Error.
void dma_set_memory_size(uint32_t dma, uint8_t stream, uint32_t mem_size)
DMA Stream Set Memory Word Width.
void dma_set_peripheral_burst(uint32_t dma, uint8_t stream, uint32_t burst)
DMA Stream Set Peripheral Burst Configuration.
void dma_set_peripheral_address(uint32_t dma, uint8_t stream, uint32_t address)
DMA Stream Set the Peripheral Address.
void dma_set_initial_target(uint32_t dma, uint8_t stream, uint8_t memory)
DMA Stream Set Initial Target Memory.
void dma_enable_fifo_error_interrupt(uint32_t dma, uint8_t stream)
DMA Enable Interrupt on FIFO Error.
void dma_stream_reset(uint32_t dma, uint8_t stream)
DMA Stream Reset.
bool dma_get_interrupt_flag(uint32_t dma, uint8_t stream, uint32_t interrupt)
DMA Stream Read Interrupt Flag.
uint8_t dma_get_target(uint32_t dma, uint8_t stream)
DMA Stream Read Current Memory Target.
void dma_enable_circular_mode(uint32_t dma, uint8_t stream)
DMA Stream Enable Memory Circular Mode.
void dma_disable_fifo_error_interrupt(uint32_t dma, uint8_t stream)
DMA Disable Interrupt on FIFO Error.
void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t stream)
DMA Stream Disable Interrupt on Transfer Half Complete.
void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream)
DMA Stream Disable Interrupt on Transfer Complete.
void dma_disable_memory_increment_mode(uint32_t dma, uint8_t stream)
DMA Channel Disable Memory Increment after Transfer.
uint32_t dma_fifo_status(uint32_t dma, uint8_t stream)
DMA Get FIFO Status.
void dma_set_number_of_data(uint32_t dma, uint8_t stream, uint16_t number)
DMA Stream Set the Transfer Block Size.
void dma_set_dma_flow_control(uint32_t dma, uint8_t stream)
DMA Stream Set DMA Flow Control.
void dma_enable_memory_increment_mode(uint32_t dma, uint8_t stream)
DMA Stream Enable Memory Increment after Transfer.
void dma_disable_double_buffer_mode(uint32_t dma, uint8_t stream)
DMA Stream Disable Double Buffer Mode.
void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t stream)
DMA Channel Disable Peripheral Increment after Transfer.
void dma_set_memory_address(uint32_t dma, uint8_t stream, uint32_t address)
DMA Stream Set the Base Memory Address 0.
void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream, uint32_t interrupts)
DMA Stream Clear Interrupt Flag.
void dma_enable_stream(uint32_t dma, uint8_t stream)
DMA Stream Enable.
void dma_set_peripheral_flow_control(uint32_t dma, uint8_t stream)
DMA Stream Set Peripheral Flow Control.
#define DMA_TCIF
Transfer Complete Interrupt Flag.
#define DMA_TEIF
Transfer Error Interrupt Flag.
#define DMA_DMEIF
Direct Mode Error Interrupt Flag.
#define DMA_FEIF
FIFO Error Interrupt Flag.
#define DMA_HTIF
Half Transfer Interrupt Flag.
#define DMA_SxCR_DIR_MEM_TO_MEM