#include <libopencm3/cm3/memorymap.h>

Include dependency graph for stm32/f7/memorymap.h:

Macros
#define	FLASH_BASE (0x08000000U)

#define	PERIPH_BASE (0x40000000U)

#define	PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)

#define	PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)

#define	PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)

#define	PERIPH_BASE_AHB2 0x50000000U

#define	PERIPH_BASE_AHB3 0x60000000U

#define	TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)

#define	TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)

#define	TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)

#define	TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)

#define	TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)

#define	TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)

#define	TIM12_BASE (PERIPH_BASE_APB1 + 0x1800)

#define	TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00)

#define	TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)

#define	LPTIM1_BASE (PERIPH_BASE_APB1 + 0x2400)

#define	RTC_BASE (PERIPH_BASE_APB1 + 0x2800)

#define	WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)

#define	IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)

#define	SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)

#define	SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)

#define	SPDIF_BASE (PERIPH_BASE_APB1 + 0x4000)

#define	USART2_BASE (PERIPH_BASE_APB1 + 0x4400)

#define	USART3_BASE (PERIPH_BASE_APB1 + 0x4800)

#define	UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)

#define	UART5_BASE (PERIPH_BASE_APB1 + 0x5000)

#define	I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)

#define	I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)

#define	I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00)

#define	I2C4_BASE (PERIPH_BASE_APB1 + 0x6000)

#define	BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)

#define	BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)

#define	CEC_BASE (PERIPH_BASE_APB1 + 0x6C00)

#define	POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)

#define	DAC_BASE (PERIPH_BASE_APB1 + 0x7400)

#define	UART7_BASE (PERIPH_BASE_APB1 + 0x7800)

#define	UART8_BASE (PERIPH_BASE_APB1 + 0x7c00)

#define	TIM1_BASE (PERIPH_BASE_APB2 + 0x0000)

#define	TIM8_BASE (PERIPH_BASE_APB2 + 0x0400)

#define	USART1_BASE (PERIPH_BASE_APB2 + 0x1000)

#define	USART6_BASE (PERIPH_BASE_APB2 + 0x1400)

#define	ADC1_BASE (PERIPH_BASE_APB2 + 0x2000) /* TODO */

#define	ADC2_BASE (PERIPH_BASE_APB2 + 0x2100) /* TODO */

#define	ADC3_BASE (PERIPH_BASE_APB2 + 0x2200) /* TODO */

#define	ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300) /* TODO */

#define	SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00) /* SDMMC */

#define	SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)

#define	SPI4_BASE (PERIPH_BASE_APB2 + 0x3400)

#define	SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800)

#define	EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00)

#define	TIM9_BASE (PERIPH_BASE_APB2 + 0x4000)

#define	TIM10_BASE (PERIPH_BASE_APB2 + 0x4400)

#define	TIM11_BASE (PERIPH_BASE_APB2 + 0x4800)

#define	SPI5_BASE (PERIPH_BASE_APB2 + 0x5000)

#define	SPI6_BASE (PERIPH_BASE_APB2 + 0x5400)

#define	SAI1_BASE (PERIPH_BASE_APB2 + 0x5800)

#define	SAI2_BASE (PERIPH_BASE_APB2 + 0x5C00)

#define	LCD_TFT_BASE (PERIPH_BASE_APB2 + 0x6800)

#define	LTDC_BASE (PERIPH_BASE_APB2 + 0x6800) /* compat. with f4 */

#define	DSI_BASE (PERIPH_BASE_APB2 + 0x6C00)

#define	DFSDM1_BASE (PERIPH_BASE_APB2 + 0x7400)

#define	MDIOS_BASE (PERIPH_BASE_APB2 + 0x7800)

#define	GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000)

#define	GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400)

#define	GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800)

#define	GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00)

#define	GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000)

#define	GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400)

#define	GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800)

#define	GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00)

#define	GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000)

#define	GPIO_PORT_J_BASE (PERIPH_BASE_AHB1 + 0x2400)

#define	GPIO_PORT_K_BASE (PERIPH_BASE_AHB1 + 0x2800)

#define	CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)

#define	RCC_BASE (PERIPH_BASE_AHB1 + 0x3800)

#define	FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00)

#define	BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000)

#define	DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000)

#define	DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400)

#define	ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000)

#define	DMA2D_BASE (PERIPH_BASE_AHB1 + 0xB000)

#define	USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000)

#define	USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x00000)

#define	DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000)

#define	CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000)

#define	HASH_BASE (PERIPH_BASE_AHB2 + 0x60400)

#define	RNG_BASE (PERIPH_BASE_AHB2 + 0x60800)

#define	FMC1_BASE (PERIPH_BASE_AHB3 + 0x00000000U)

#define	FMC2_BASE (PERIPH_BASE_AHB3 + 0x10000000U)

#define	FMC3_BASE (PERIPH_BASE_AHB3 + 0x20000000U)

#define	QSPI_BASE (PERIPH_BASE_AHB3 + 0x30000000U)

#define	FMCC_BASE (PERIPH_BASE_AHB3 + 0x40000000U)

#define	QUADSPI_BASE (PERIPH_BASE_AHB3 + 0x40001000U)

#define	QSPIC_BASE QUADSPI_BASE /* Deprecated compat */

#define	FMC5_BASE (PERIPH_BASE_AHB3 + 0x60000000U)

#define	FMC6_BASE (PERIPH_BASE_AHB3 + 0x70000000U)

#define	DBGMCU_BASE (PPBI_BASE + 0x00042000)

#define	DESIG_FLASH_SIZE_BASE_449 (0x1FF0F422U)

#define	DESIG_FLASH_SIZE_BASE_451 (0x1FF0F422U)

#define	DESIG_FLASH_SIZE_BASE_452 (0x1FF07A22U)

#define	DESIG_UNIQUE_ID_BASE_449 (0x1FF0F420U)

#define	DESIG_UNIQUE_ID_BASE_451 (0x1FF0F420U)

#define	DESIG_UNIQUE_ID_BASE_452 (0x1FF07A10U)

#define	ST_VREFINT_CAL MMIO16(0x1FF07A4A)

#define	ST_TSENSE_CAL1_30C MMIO16(0x1FF07A4C)

#define	ST_TSENSE_CAL2_110C MMIO16(0x1FF07A4E)

Macro Definition Documentation

◆ ADC1_BASE

#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000) /* TODO */

Definition at line 78 of file stm32/f7/memorymap.h.

◆ ADC2_BASE

#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2100) /* TODO */

Definition at line 79 of file stm32/f7/memorymap.h.

◆ ADC3_BASE

#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2200) /* TODO */

Definition at line 80 of file stm32/f7/memorymap.h.

◆ ADC_COMMON_BASE

#define ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300) /* TODO */

Definition at line 81 of file stm32/f7/memorymap.h.

◆ BKPSRAM_BASE

#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000)

Definition at line 121 of file stm32/f7/memorymap.h.

◆ BX_CAN1_BASE

#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)

Definition at line 62 of file stm32/f7/memorymap.h.

◆ BX_CAN2_BASE

#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)

Definition at line 63 of file stm32/f7/memorymap.h.

◆ CEC_BASE

#define CEC_BASE (PERIPH_BASE_APB1 + 0x6C00)

Definition at line 64 of file stm32/f7/memorymap.h.

◆ CRC_BASE

#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)

Definition at line 117 of file stm32/f7/memorymap.h.

◆ CRYP_BASE

#define CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000)

Definition at line 138 of file stm32/f7/memorymap.h.

◆ DAC_BASE

#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)

Definition at line 66 of file stm32/f7/memorymap.h.

◆ DBGMCU_BASE

#define DBGMCU_BASE (PPBI_BASE + 0x00042000)

Definition at line 156 of file stm32/f7/memorymap.h.

◆ DCMI_BASE

#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000)

Definition at line 136 of file stm32/f7/memorymap.h.

◆ DESIG_FLASH_SIZE_BASE_449

#define DESIG_FLASH_SIZE_BASE_449 (0x1FF0F422U)

Definition at line 160 of file stm32/f7/memorymap.h.

◆ DESIG_FLASH_SIZE_BASE_451

#define DESIG_FLASH_SIZE_BASE_451 (0x1FF0F422U)

Definition at line 161 of file stm32/f7/memorymap.h.

◆ DESIG_FLASH_SIZE_BASE_452

#define DESIG_FLASH_SIZE_BASE_452 (0x1FF07A22U)

Definition at line 162 of file stm32/f7/memorymap.h.

◆ DESIG_UNIQUE_ID_BASE_449

#define DESIG_UNIQUE_ID_BASE_449 (0x1FF0F420U)

Definition at line 164 of file stm32/f7/memorymap.h.

◆ DESIG_UNIQUE_ID_BASE_451

#define DESIG_UNIQUE_ID_BASE_451 (0x1FF0F420U)

Definition at line 165 of file stm32/f7/memorymap.h.

◆ DESIG_UNIQUE_ID_BASE_452

#define DESIG_UNIQUE_ID_BASE_452 (0x1FF07A10U)

Definition at line 166 of file stm32/f7/memorymap.h.

◆ DFSDM1_BASE

#define DFSDM1_BASE (PERIPH_BASE_APB2 + 0x7400)

Definition at line 100 of file stm32/f7/memorymap.h.

◆ DMA1_BASE

#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000)

Definition at line 123 of file stm32/f7/memorymap.h.

◆ DMA2_BASE

#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400)

Definition at line 124 of file stm32/f7/memorymap.h.

◆ DMA2D_BASE

#define DMA2D_BASE (PERIPH_BASE_AHB1 + 0xB000)

Definition at line 128 of file stm32/f7/memorymap.h.

◆ DSI_BASE

#define DSI_BASE (PERIPH_BASE_APB2 + 0x6C00)

Definition at line 99 of file stm32/f7/memorymap.h.

◆ ETHERNET_BASE

#define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000)

Definition at line 126 of file stm32/f7/memorymap.h.

◆ EXTI_BASE

#define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00)

Definition at line 88 of file stm32/f7/memorymap.h.

◆ FLASH_BASE

#define FLASH_BASE (0x08000000U)

Definition at line 26 of file stm32/f7/memorymap.h.

◆ FLASH_MEM_INTERFACE_BASE

#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00)

Definition at line 120 of file stm32/f7/memorymap.h.

◆ FMC1_BASE

#define FMC1_BASE (PERIPH_BASE_AHB3 + 0x00000000U)

Definition at line 145 of file stm32/f7/memorymap.h.

◆ FMC2_BASE

#define FMC2_BASE (PERIPH_BASE_AHB3 + 0x10000000U)

Definition at line 146 of file stm32/f7/memorymap.h.

◆ FMC3_BASE

#define FMC3_BASE (PERIPH_BASE_AHB3 + 0x20000000U)

Definition at line 147 of file stm32/f7/memorymap.h.

◆ FMC5_BASE

#define FMC5_BASE (PERIPH_BASE_AHB3 + 0x60000000U)

Definition at line 152 of file stm32/f7/memorymap.h.

◆ FMC6_BASE

#define FMC6_BASE (PERIPH_BASE_AHB3 + 0x70000000U)

Definition at line 153 of file stm32/f7/memorymap.h.

◆ FMCC_BASE

#define FMCC_BASE (PERIPH_BASE_AHB3 + 0x40000000U)

Definition at line 149 of file stm32/f7/memorymap.h.

◆ GPIO_PORT_A_BASE

#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000)

Definition at line 105 of file stm32/f7/memorymap.h.

◆ GPIO_PORT_B_BASE

#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400)

Definition at line 106 of file stm32/f7/memorymap.h.

◆ GPIO_PORT_C_BASE

#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800)

Definition at line 107 of file stm32/f7/memorymap.h.

◆ GPIO_PORT_D_BASE

#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00)

Definition at line 108 of file stm32/f7/memorymap.h.

◆ GPIO_PORT_E_BASE

#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000)

Definition at line 109 of file stm32/f7/memorymap.h.

◆ GPIO_PORT_F_BASE

#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400)

Definition at line 110 of file stm32/f7/memorymap.h.

◆ GPIO_PORT_G_BASE

#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800)

Definition at line 111 of file stm32/f7/memorymap.h.

◆ GPIO_PORT_H_BASE

#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00)

Definition at line 112 of file stm32/f7/memorymap.h.

◆ GPIO_PORT_I_BASE

#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000)

Definition at line 113 of file stm32/f7/memorymap.h.

◆ GPIO_PORT_J_BASE

#define GPIO_PORT_J_BASE (PERIPH_BASE_AHB1 + 0x2400)

Definition at line 114 of file stm32/f7/memorymap.h.

◆ GPIO_PORT_K_BASE

#define GPIO_PORT_K_BASE (PERIPH_BASE_AHB1 + 0x2800)

Definition at line 115 of file stm32/f7/memorymap.h.

◆ HASH_BASE

#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400)

Definition at line 139 of file stm32/f7/memorymap.h.

◆ I2C1_BASE

#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)

Definition at line 58 of file stm32/f7/memorymap.h.

◆ I2C2_BASE

#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)

Definition at line 59 of file stm32/f7/memorymap.h.

◆ I2C3_BASE

#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00)

Definition at line 60 of file stm32/f7/memorymap.h.

◆ I2C4_BASE

#define I2C4_BASE (PERIPH_BASE_APB1 + 0x6000)

Definition at line 61 of file stm32/f7/memorymap.h.

◆ IWDG_BASE

#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)

Definition at line 49 of file stm32/f7/memorymap.h.

◆ LCD_TFT_BASE

#define LCD_TFT_BASE (PERIPH_BASE_APB2 + 0x6800)

Definition at line 97 of file stm32/f7/memorymap.h.

◆ LPTIM1_BASE

#define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x2400)

Definition at line 46 of file stm32/f7/memorymap.h.

◆ LTDC_BASE

#define LTDC_BASE (PERIPH_BASE_APB2 + 0x6800) /* compat. with f4 */

Definition at line 98 of file stm32/f7/memorymap.h.

◆ MDIOS_BASE

#define MDIOS_BASE (PERIPH_BASE_APB2 + 0x7800)

Definition at line 101 of file stm32/f7/memorymap.h.

◆ PERIPH_BASE

#define PERIPH_BASE (0x40000000U)

Definition at line 27 of file stm32/f7/memorymap.h.

◆ PERIPH_BASE_AHB1

#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)

Definition at line 30 of file stm32/f7/memorymap.h.

◆ PERIPH_BASE_AHB2

#define PERIPH_BASE_AHB2 0x50000000U

Definition at line 31 of file stm32/f7/memorymap.h.

◆ PERIPH_BASE_AHB3

#define PERIPH_BASE_AHB3 0x60000000U

Definition at line 32 of file stm32/f7/memorymap.h.

◆ PERIPH_BASE_APB1

#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)

Definition at line 28 of file stm32/f7/memorymap.h.

◆ PERIPH_BASE_APB2

#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)

Definition at line 29 of file stm32/f7/memorymap.h.

◆ POWER_CONTROL_BASE

#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)

Definition at line 65 of file stm32/f7/memorymap.h.

◆ QSPI_BASE

#define QSPI_BASE (PERIPH_BASE_AHB3 + 0x30000000U)

Definition at line 148 of file stm32/f7/memorymap.h.

◆ QSPIC_BASE

#define QSPIC_BASE QUADSPI_BASE /* Deprecated compat */

Definition at line 151 of file stm32/f7/memorymap.h.

◆ QUADSPI_BASE

#define QUADSPI_BASE (PERIPH_BASE_AHB3 + 0x40001000U)

Definition at line 150 of file stm32/f7/memorymap.h.

◆ RCC_BASE

#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800)

Definition at line 119 of file stm32/f7/memorymap.h.

◆ RNG_BASE

#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800)

Definition at line 141 of file stm32/f7/memorymap.h.

◆ RTC_BASE

#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)

Definition at line 47 of file stm32/f7/memorymap.h.

◆ SAI1_BASE

#define SAI1_BASE (PERIPH_BASE_APB2 + 0x5800)

Definition at line 95 of file stm32/f7/memorymap.h.

◆ SAI2_BASE

#define SAI2_BASE (PERIPH_BASE_APB2 + 0x5C00)

Definition at line 96 of file stm32/f7/memorymap.h.

◆ SDIO_BASE

#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00) /* SDMMC */

Definition at line 83 of file stm32/f7/memorymap.h.

◆ SPDIF_BASE

#define SPDIF_BASE (PERIPH_BASE_APB1 + 0x4000)

Definition at line 53 of file stm32/f7/memorymap.h.

◆ SPI1_BASE

#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)

Definition at line 85 of file stm32/f7/memorymap.h.

◆ SPI2_BASE

#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)

Definition at line 51 of file stm32/f7/memorymap.h.

◆ SPI3_BASE

#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)

Definition at line 52 of file stm32/f7/memorymap.h.

◆ SPI4_BASE

#define SPI4_BASE (PERIPH_BASE_APB2 + 0x3400)

Definition at line 86 of file stm32/f7/memorymap.h.

◆ SPI5_BASE

#define SPI5_BASE (PERIPH_BASE_APB2 + 0x5000)

Definition at line 93 of file stm32/f7/memorymap.h.

◆ SPI6_BASE

#define SPI6_BASE (PERIPH_BASE_APB2 + 0x5400)

Definition at line 94 of file stm32/f7/memorymap.h.

◆ ST_TSENSE_CAL1_30C

#define ST_TSENSE_CAL1_30C MMIO16(0x1FF07A4C)

Definition at line 170 of file stm32/f7/memorymap.h.

◆ ST_TSENSE_CAL2_110C

#define ST_TSENSE_CAL2_110C MMIO16(0x1FF07A4E)

Definition at line 171 of file stm32/f7/memorymap.h.

◆ ST_VREFINT_CAL

#define ST_VREFINT_CAL MMIO16(0x1FF07A4A)

Definition at line 169 of file stm32/f7/memorymap.h.

◆ SYSCFG_BASE

#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800)

Definition at line 87 of file stm32/f7/memorymap.h.

◆ TIM10_BASE

#define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400)

Definition at line 90 of file stm32/f7/memorymap.h.

◆ TIM11_BASE

#define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800)

Definition at line 91 of file stm32/f7/memorymap.h.

◆ TIM12_BASE

#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800)

Definition at line 43 of file stm32/f7/memorymap.h.

◆ TIM13_BASE

#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00)

Definition at line 44 of file stm32/f7/memorymap.h.

◆ TIM14_BASE

#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)

Definition at line 45 of file stm32/f7/memorymap.h.

◆ TIM1_BASE

#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000)

Definition at line 72 of file stm32/f7/memorymap.h.

◆ TIM2_BASE

#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)

Definition at line 37 of file stm32/f7/memorymap.h.

◆ TIM3_BASE

#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)

Definition at line 38 of file stm32/f7/memorymap.h.

◆ TIM4_BASE

#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)

Definition at line 39 of file stm32/f7/memorymap.h.

◆ TIM5_BASE

#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)

Definition at line 40 of file stm32/f7/memorymap.h.

◆ TIM6_BASE

#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)

Definition at line 41 of file stm32/f7/memorymap.h.

◆ TIM7_BASE

#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)

Definition at line 42 of file stm32/f7/memorymap.h.

◆ TIM8_BASE

#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400)

Definition at line 73 of file stm32/f7/memorymap.h.

◆ TIM9_BASE

#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000)

Definition at line 89 of file stm32/f7/memorymap.h.

◆ UART4_BASE

#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)

Definition at line 56 of file stm32/f7/memorymap.h.

◆ UART5_BASE

#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000)

Definition at line 57 of file stm32/f7/memorymap.h.

◆ UART7_BASE

#define UART7_BASE (PERIPH_BASE_APB1 + 0x7800)

Definition at line 67 of file stm32/f7/memorymap.h.

◆ UART8_BASE

#define UART8_BASE (PERIPH_BASE_APB1 + 0x7c00)

Definition at line 68 of file stm32/f7/memorymap.h.

◆ USART1_BASE

#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000)

Definition at line 75 of file stm32/f7/memorymap.h.

◆ USART2_BASE

#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)

Definition at line 54 of file stm32/f7/memorymap.h.

◆ USART3_BASE

#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)

Definition at line 55 of file stm32/f7/memorymap.h.

◆ USART6_BASE

#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400)

Definition at line 76 of file stm32/f7/memorymap.h.

◆ USB_OTG_FS_BASE

#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x00000)

Definition at line 134 of file stm32/f7/memorymap.h.

◆ USB_OTG_HS_BASE

#define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000)

Definition at line 130 of file stm32/f7/memorymap.h.

◆ WWDG_BASE

#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)

Definition at line 48 of file stm32/f7/memorymap.h.

Macros