libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
stm32/f7/memorymap.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * This library is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU Lesser General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or
7 * (at your option) any later version.
8 *
9 * This library is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU Lesser General Public License for more details.
13 *
14 * You should have received a copy of the GNU Lesser General Public License
15 * along with this library. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef LIBOPENCM3_MEMORYMAP_H
19#define LIBOPENCM3_MEMORYMAP_H
20
21#include <libopencm3/cm3/memorymap.h>
22
23/* --- STM32F7 specific peripheral definitions ----------------------------- */
24
25/* Memory map for all busses */
26#define FLASH_BASE (0x08000000U)
27#define PERIPH_BASE (0x40000000U)
28#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
29#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
30#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)
31#define PERIPH_BASE_AHB2 0x50000000U
32#define PERIPH_BASE_AHB3 0x60000000U
33
34/* Register boundary addresses */
35
36/* APB1 */
37#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
38#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
39#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
40#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
41#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
42#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
43#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800)
44#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00)
45#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)
46#define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x2400)
47#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
48#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
49#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
50/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
51#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
52#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
53#define SPDIF_BASE (PERIPH_BASE_APB1 + 0x4000)
54#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
55#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
56#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
57#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000)
58#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
59#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
60#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00)
61#define I2C4_BASE (PERIPH_BASE_APB1 + 0x6000)
62#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)
63#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)
64#define CEC_BASE (PERIPH_BASE_APB1 + 0x6C00)
65#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
66#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
67#define UART7_BASE (PERIPH_BASE_APB1 + 0x7800)
68#define UART8_BASE (PERIPH_BASE_APB1 + 0x7c00)
69/* PERIPH_BASE_APB1 + 0x7800 (0x4000 8000 - 0x4000 FFFF): Reserved */
70
71/* APB2 */
72#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000)
73#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400)
74/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */
75#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000)
76#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400)
77/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */
78#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000) /* TODO */
79#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2100) /* TODO */
80#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2200) /* TODO */
81#define ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300) /* TODO */
82/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */
83#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00) /* SDMMC */
84/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */
85#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
86#define SPI4_BASE (PERIPH_BASE_APB2 + 0x3400)
87#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800)
88#define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00)
89#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000)
90#define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400)
91#define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800)
92/* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 4FFF): Reserved */
93#define SPI5_BASE (PERIPH_BASE_APB2 + 0x5000)
94#define SPI6_BASE (PERIPH_BASE_APB2 + 0x5400)
95#define SAI1_BASE (PERIPH_BASE_APB2 + 0x5800)
96#define SAI2_BASE (PERIPH_BASE_APB2 + 0x5C00)
97#define LCD_TFT_BASE (PERIPH_BASE_APB2 + 0x6800)
98#define LTDC_BASE (PERIPH_BASE_APB2 + 0x6800) /* compat. with f4 */
99#define DSI_BASE (PERIPH_BASE_APB2 + 0x6C00)
100#define DFSDM1_BASE (PERIPH_BASE_APB2 + 0x7400)
101#define MDIOS_BASE (PERIPH_BASE_APB2 + 0x7800)
102/* PERIPH_BASE_APB2 + 0x6C00 (0x4001 7C00 - 0x4001 FFFF): Reserved */
103
104/* AHB1 */
105#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000)
106#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400)
107#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800)
108#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00)
109#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000)
110#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400)
111#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800)
112#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00)
113#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000)
114#define GPIO_PORT_J_BASE (PERIPH_BASE_AHB1 + 0x2400)
115#define GPIO_PORT_K_BASE (PERIPH_BASE_AHB1 + 0x2800)
116/* PERIPH_BASE_AHB1 + 0x2C00 (0x4002 2C00 - 0x4002 2FFF): Reserved */
117#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)
118/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */
119#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800)
120#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00)
121#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000)
122/* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */
123#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000)
124#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400)
125/* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */
126#define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000)
127
128#define DMA2D_BASE (PERIPH_BASE_AHB1 + 0xB000)
129
130#define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000)
131
132
133/* AHB2 */
134#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x00000)
135/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */
136#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000)
137/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5005 FFFF): Reserved */
138#define CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000)
139#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400)
140/* PERIPH_BASE_AHB2 + 0x60C00 (0x5006 0C00 - 0x5006 07FF): Reserved */
141#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800)
142/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */
143
144/* AHB3 */
145#define FMC1_BASE (PERIPH_BASE_AHB3 + 0x00000000U)
146#define FMC2_BASE (PERIPH_BASE_AHB3 + 0x10000000U)
147#define FMC3_BASE (PERIPH_BASE_AHB3 + 0x20000000U)
148#define QSPI_BASE (PERIPH_BASE_AHB3 + 0x30000000U)
149#define FMCC_BASE (PERIPH_BASE_AHB3 + 0x40000000U)
150#define QUADSPI_BASE (PERIPH_BASE_AHB3 + 0x40001000U)
151#define QSPIC_BASE QUADSPI_BASE /* Deprecated compat */
152#define FMC5_BASE (PERIPH_BASE_AHB3 + 0x60000000U)
153#define FMC6_BASE (PERIPH_BASE_AHB3 + 0x70000000U)
154
155/* Private peripherals */
156#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
157
158/* Device Electronic Signature */
159/* On F7 the base address are different depending on the device ID in DBBGMCU. */
160#define DESIG_FLASH_SIZE_BASE_449 (0x1FF0F422U)
161#define DESIG_FLASH_SIZE_BASE_451 (0x1FF0F422U)
162#define DESIG_FLASH_SIZE_BASE_452 (0x1FF07A22U)
163
164#define DESIG_UNIQUE_ID_BASE_449 (0x1FF0F420U)
165#define DESIG_UNIQUE_ID_BASE_451 (0x1FF0F420U)
166#define DESIG_UNIQUE_ID_BASE_452 (0x1FF07A10U)
167
168/* ST provided factory calibration values @ 3.3V */
169#define ST_VREFINT_CAL MMIO16(0x1FF07A4A)
170#define ST_TSENSE_CAL1_30C MMIO16(0x1FF07A4C)
171#define ST_TSENSE_CAL2_110C MMIO16(0x1FF07A4E)
172
173#endif