Collaboration diagram for FDCAN Defines:

Data Structures
struct	fdcan_standard_filter
	Structure describing standard ID filter. More...

struct	fdcan_extended_filter
	Structure describing extended ID filters. More...

struct	fdcan_rx_fifo_element
	Structure describing receive FIFO element. More...

struct	fdcan_tx_event_element
	Structure describing transmit event element. More...

struct	fdcan_tx_buffer_element
	Structure describing transmit buffer element. More...

Modules
	FDCAN block base addresses

	Named constants for FIFOs

	registers file in each FDCAN block.

	FDCAN CC control register bits

	FDCAN interrupt register flags

	FDCAN interrupt enable flags

	FDCAN_ILS interrupt line select flags

	FDCAN_TXBRP Transmit request pending bits

	FDCAN_TXBAR Transmit buffer add request bits

	FDCAN_TXBCR Transmit buffer cancel request bits

	FDCAN_TXBTO Transmit buffer transfer occured bits

	FDCAN_TXBCF Transmit buffer cancellation finished bits

	FDCAN_TXBTIE Transmit interrupt enable bits
	Each bit enables or disables transmit interrupt for transmit buffer slot.

	FDCAN_TXBCIE Transmit cancelled interrupt enable bits
	Each bit enables or disables transmit cancelled interrupt for transmit buffer slot.

	Standard ID filter match type
	Matching strategy for standard ID filters.

	Standard ID filter action
	Defines possible actions for standard ID filters.

	Extended ID filter action
	These are possible actions, extended filter can have.

	Extended ID filter match type
	Matching strategy for extended ID filters.

	FIFO / buffer flags

	FDCAN error return values

Macros
#define	CAN_MSG_SIZE 0x2800

#define	FDCAN_GFC(can_base) MMIO32(can_base + 0x0080)

#define	FDCAN_SIDFC(can_base) MMIO32(can_base + 0x0084)

#define	FDCAN_XIDFC(can_base) MMIO32(can_base + 0x0088)

#define	FDCAN_XIDAM(can_base) MMIO32(can_base + 0x0090)

#define	FDCAN_HPMS(can_base) MMIO32(can_base + 0x0094)

#define	FDCAN_NDAT1(can_base) MMIO32(can_base + 0x0098)

#define	FDCAN_HDAT2(can_base) MMIO32(can_base + 0x009C)

#define	FDCAN_RXFIC_BASE 0x00A0

#define	FDCAN_RXFI_OFFSET 0x0010

#define	FDCAN_RXFIC(can_base, fifo_id) MMIO32((can_base) + FDCAN_RXFIC_BASE + (FDCAN_RXFI_OFFSET * (fifo_id)))

#define	FDCAN_RXF0C(can_base) FDCAN_RXFIC(can_base, 0)

#define	FDCAN_RXF1C(can_base) FDCAN_RXFIC(can_base, 1)

#define	FDCAN_RXFIS_BASE 0x00A4

#define	FDCAN_RXFIA_BASE 0x00A8

#define	FDCAN_RXBC(can_base) MMIO32(can_base + 0x00AC)

#define	FDCAN_RXESC(can_base) MMIO32(can_base + 0x00BC)

#define	FDCAN_TXESC(can_base) MMIO32(can_base + 0x00C8)

#define	FDCAN_TXBRP(can_base) MMIO32(can_base + 0x00CC)

#define	FDCAN_TXBAR(can_base) MMIO32(can_base + 0x00D0)

#define	FDCAN_TXBCR(can_base) MMIO32(can_base + 0x00D4)

#define	FDCAN_TXBTO(can_base) MMIO32(can_base + 0x00D8)

#define	FDCAN_TXBCF(can_base) MMIO32(can_base + 0x00DC)

#define	FDCAN_TXBTIE(can_base) MMIO32(can_base + 0x00E0)

#define	FDCAN_TXBCIE(can_base) MMIO32(can_base + 0x00E4)

#define	FDCAN_TXEFC(can_base) MMIO32(can_base + 0x00F0)

#define	FDCAN_TXEFS(can_base) MMIO32(can_base + 0x00F4)

#define	FDCAN_TXEFA(can_base) MMIO32(can_base + 0x00F8)

#define	FDCAN_TTTMC(can_base) MMIO32(can_base + 0x0100)

#define	FDCAN_TTRMC(can_base) MMIO32(can_base + 0x0104)

#define	FDCAN_TTOCF(can_base) MMIO32(can_base + 0x0108)

#define	FDCAN_TTMLM(can_base) MMIO32(can_base + 0x010C)

#define	FDCAN_TURCF(can_base) MMIO32(can_base + 0x0110)

#define	FDCAN_TTOCN(can_base) MMIO32(can_base + 0x0114)

#define	FDCAN_TTGTP(can_base) MMIO32(can_base + 0x0118)

#define	FDCAN_TTTMK(can_base) MMIO32(can_base + 0x011C)

#define	FDCAN_TTTIR(can_base) MMIO32(can_base + 0x0120)

#define	FDCAN_TTIE(can_base) MMIO32(can_base + 0x0124)

#define	FDCAN_TTILS(can_base) MMIO32(can_base + 0x0128)

#define	FDCAN_TTOST(can_base) MMIO32(can_base + 0x012C)

#define	FDCAN_TURNA(can_base) MMIO32(can_base + 0x0130)

#define	FDCAN_TTLGT(can_base) MMIO32(can_base + 0x0134)

#define	FDCAN_TTCTC(can_base) MMIO32(can_base + 0x0138)

#define	FDCAN_TTCPT(can_base) MMIO32(can_base + 0x013C)

#define	FDCAN_TTCSM(can_base) MMIO32(can_base + 0x0140)

#define	FDCAN_TTTS(can_base) MMIO32(can_base + 0x0300)

#define	FDCAN_CCU_CCFG MMIO32(CAN_CCU_BASE + 0x0004)

#define	FDCAN_CCU_CREL MMIO32(CAN_CCU_BASE + 0x0000)

#define	FDCAN_GFC_RRFE (1 << 0)

#define	FDCAN_GFC_RRFS (1 << 1)

#define	FDCAN_GFC_ANFE_SHIFT 2
	ANFE[1:0]: Accept non-matching frames w/ extended ID. More...

#define	FDCAN_GFC_ANFE_MASK 0x3

#define	FDCAN_GFC_ANFS_SHIFT 4
	ANFS[1:0]: Accept non-matching frames w/ standard ID. More...

#define	FDCAN_GFC_ANFS_MASK 0x3

#define	FDCAN_FXS_MASK 0xFF

#define	FDCAN_FXS_SHIFT 16

#define	FDCAN_FXSA_MASK 0x3FFF
	Position of start address of relocatable object within register. More...

#define	FDCAN_FXSA_SHIFT 2

#define	FDCAN_SIDFC_LSS_MASK FDCAN_FXS_MASK
	LSS[7:0]: List size of standard ID filters. More...

#define	FDCAN_SIDFC_LSS_SHIFT FDCAN_FXS_SHIFT

#define	FDCAN_SIDFC_FLSSA_MASK FDCAN_FXSA_MASK
	LFSSA[13:0]: Filter List standard start address. More...

#define	FDCAN_SIDFC_FLSSA_SHIFT FDCAN_FXSA_SHIFT

#define	FDCAN_XIDFC_LSE_MASK FDCAN_FXS_MASK
	LSE[7:0]: List size of extended ID filters. More...

#define	FDCAN_XIDFC_LSE_SHIFT FDCAN_FXS_SHIFT

#define	FDCAN_XIDFC_FLESA_MASK FDCAN_FXSA_MASK
	LFSSA[7:0]: Filter List extended start address. More...

#define	FDCAN_XIDFC_FLESA_SHIFT FDCAN_FXSA_SHIFT

#define	FDCAN_TXBC_TFQS_MASK 0x3F
	TFQS[5:0]: Tx FIFO/Queue size. More...

#define	FDCAN_TXBC_TFQS_SHIFT 24

#define	FDCAN_TXBC_TBSA_MASK FDCAN_FXSA_MASK
	TBSA[7:0]: Transmit buffer start address. More...

#define	FDCAN_TXBC_TBSA_SHIFT FDCAN_FXSA_SHIFT

#define	FDCAN_TXEFC_EFS_MASK 0x3F

#define	FDCAN_TXEFC_EFS_SHIFT 16

#define	FDCAN_TXEFC_EFSA_MASK FDCAN_FXSA_MASK
	EFSA[7:0]: (Transmit) event FIFO start address. More...

#define	FDCAN_TXEFC_EFSA_SHIFT FDCAN_FXSA_SHIFT

#define	FDCAN_RXFIC_FIOM (1 << 31)

#define	FDCAN_RXFIC_FIWM_MASK 0x7F

#define	FDCAN_RXFIC_FIWM_SHIFT 24

#define	FDCAN_RXFIC_FIS_MASK 0x7F

#define	FDCAN_RXFIC_FIS_SHIFT 16

#define	FDCAN_RXFIC_FISA_MASK FDCAN_FXSA_MASK

#define	FDCAN_RXFIC_FISA_SHIFT FDCAN_FXSA_SHIFT

#define	FDCAN_RXF0C_F0OM FDCAN_RXFIC_FIOM

#define	FDCAN_RXF0C_F0WM_MASK FDCAN_RXFIC_FIWM_MASK
	F0WM[6:0]: FIFO0 watermark mode. More...

#define	FDCAN_RXF0C_F0WM_SHIFT FDCAN_RXFIC_FIWM_SHIFT

#define	FDCAN_RXF0C_F0S_MASK FDCAN_RXFIC_FIS_MASK
	F0S[6:0]: FIFO0 size. More...

#define	FDCAN_RXF0C_F0S_SHIFT FDCAN_RXFIC_FIS_SHIFT

#define	FDCAN_RXF0C_F0SA_MASK FDCAN_RXFIC_FISA_MASK
	F0SA[13:0]: FIFO0 start address. More...

#define	FDCAN_RXF0C_F0SA_SHIFT FDCAN_RXFIC_FISA_SHIFT

#define	FDCAN_RXF1C_F1OM FDCAN_RXFIC_FIOM

#define	FDCAN_RXF1C_F1WM_MASK FDCAN_RXFIC_FIWM_MASK
	F1WM[6:0]: FIFO1 watermark mode. More...

#define	FDCAN_RXF1C_F1WM_SHIFT FDCAN_RXFIC_FIWM_SHIFT

#define	FDCAN_RXF1C_F1S_MASK FDCAN_RXFIC_FIS_MASK
	F1S[6:0]: FIFO1 size. More...

#define	FDCAN_RXF1C_F1S_SHIFT FDCAN_RXFIC_FIS_SHIFT

#define	FDCAN_RXF1C_F1SA_MASK FDCAN_RXFIC_FISA_MASK
	F1SA[13:0]: FIFO1 start address. More...

#define	FDCAN_RXF1C_F1SA_SHIFT FDCAN_RXFIC_FISA_SHIFT

#define	FDCAN_RXESC_RBDS_MASK 0x7
	RBDS[3:0]: RX buffer data field size. More...

#define	FDCAN_RXESC_RBDS_SHIFT 8

#define	FDCAN_RXESC_F0DS_MASK 0x7
	F0DS[3:0]: FIFO0 data field size. More...

#define	FDCAN_RXESC_F0DS_SHIFT 0

#define	FDCAN_RXESC_F1DS_MASK 0x7
	F1DS[3:0]: FIFO1 data field size. More...

#define	FDCAN_RXESC_F1DS_SHIFT 4

#define	FDCAN_TXESC_TBDS_MASK 0x7
	TBDS[3:0]: TX buffer data field size. More...

#define	FDCAN_TXESC_TBDS_SHIFT 0

#define	FDCAN_RXFIFO_FL_MASK 0x7F

#define	FDCAN_RXFIFO_GI_MASK 0x3F

#define	FDCAN_RXFIFO_PI_MASK 0x3F

#define	FDCAN_RXFIFO_AI_MASK 0x3F

#define	FDCAN_TXFQS_TFFL_MASK 0x3F

#define	FDCAN_TXFQS_TFGI_MASK 0x1F

#define	FDCAN_TXFQS_TFQPI_MASK 0x1F

#define	FDCAN_TXEFS_EFFL_MASK 0x3F

#define	FDCAN_TXEFS_EFGI_MASK 0x1F

#define	FDCAN_TXEFS_EFPI_MASK 0x1F

#define	FDCAN_CCU_CCFG_CDIV_SHIFT 16
	CDIV[3:0]: Input clock divider. More...

#define	FDCAN_CCU_CCFG_CDIV_MASK 0xF

#define	FDCAN_LFSSA_OFFSET(can_base) (FDCAN_SIDFC(can_base) & (FDCAN_SIDFC_FLSSA_MASK << FDCAN_SIDFC_FLSSA_SHIFT))

#define	FDCAN_LFESA_OFFSET(can_base) (FDCAN_XIDFC(can_base) & (FDCAN_XIDFC_FLESA_MASK << FDCAN_XIDFC_FLESA_SHIFT))

#define	FDCAN_RXFIFO_OFFSET(can_base, fifo_id) (FDCAN_RXFIC(can_base, fifo_id) & (FDCAN_FXSA_MASK << FDCAN_FXSA_SHIFT))

#define	FDCAN_TXBUF_OFFSET(can_base) (FDCAN_TXBC(can_base) & (FDCAN_TXBC_TBSA_MASK << FDCAN_TXBC_TBSA_SHIFT))

#define	FDCAN_TXEVT_OFFSET(can_base) (FDCAN_TXEFC(can_base) & (FDCAN_TXEFC_EFSA_MASK << FDCAN_TXEFC_EFSA_SHIFT))

#define	FDCAN_BLOCK_ID(can_base) (((can_base) - CAN1)/(CAN2 - CAN1))

#define	FDCAN_CREL(can_base) MMIO32(can_base + 0x0000)

#define	FDCAN_ENDN(can_base) MMIO32(can_base + 0x0004)

#define	FDCAN_DBTP(can_base) MMIO32(can_base + 0x000C)

#define	FDCAN_TEST(can_base) MMIO32(can_base + 0x0010)

#define	FDCAN_RWD(can_base) MMIO32(can_base + 0x0014)

#define	FDCAN_CCCR(can_base) MMIO32(can_base + 0x0018)

#define	FDCAN_NBTP(can_base) MMIO32(can_base + 0x001C)

#define	FDCAN_TSCC(can_base) MMIO32(can_base + 0x0020)

#define	FDCAN_TSCV(can_base) MMIO32(can_base + 0x0024)

#define	FDCAN_TOCC(can_base) MMIO32(can_base + 0x0028)

#define	FDCAN_TOCV(can_base) MMIO32(can_base + 0x002C)

#define	FDCAN_ECR(can_base) MMIO32(can_base + 0x0040)

#define	FDCAN_PSR(can_base) MMIO32(can_base + 0x0044)

#define	FDCAN_TDCR(can_base) MMIO32(can_base + 0x0048)

#define	FDCAN_IR(can_base) MMIO32(can_base + 0x0050)

#define	FDCAN_IE(can_base) MMIO32(can_base + 0x0054)

#define	FDCAN_ILS(can_base) MMIO32(can_base + 0x0058)

#define	FDCAN_ILE(can_base) MMIO32(can_base + 0x005C)

#define	FDCAN_RXFIS(can_base, fifo_id) MMIO32(can_base + FDCAN_RXFIS_BASE + (FDCAN_RXFI_OFFSET * fifo_id))
	Generic access to Rx FIFO status registers. More...

#define	FDCAN_RXF0S(can_base) FDCAN_RXFIS(can_base, 0)

#define	FDCAN_RXF1S(can_base) FDCAN_RXFIS(can_base, 1)

#define	FDCAN_RXFIA(can_base, fifo_id) MMIO32(can_base + FDCAN_RXFIA_BASE + (FDCAN_RXFI_OFFSET * fifo_id))
	Generic access to Rx FIFO acknowledge registers. More...

#define	FDCAN_RXF0A(can_base) FDCAN_RXFIA(can_base, 0)

#define	FDCAN_RXF1A(can_base) FDCAN_RXFIA(can_base, 1)

#define	FDCAN_TXBC(can_base) MMIO32(can_base + 0x00C0)

#define	FDCAN_TXFQS(can_base) MMIO32(can_base + 0x00C4)

#define	FDCAN_CREL_DAY_SHIFT 0
	DAY[7:0]: FDCAN core revision date. More...

#define	FDCAN_CREL_DAY_MASK 0xFF

#define	FDCAN_CREL_MON_SHIFT 8
	MON[7:0]: FDCAN core revision month. More...

#define	FDCAN_CREL_MON_MASK 0xFF

#define	FDCAN_CREL_YEAR_SHIFT 16
	YEAR[3:0]: FDCAN core revision year. More...

#define	FDCAN_CREL_YEAR_MASK 0xF

#define	FDCAN_CREL_SUBSTEP_SHIFT 20
	SUBSTEP[3:0]: FDCAN core release sub stepping. More...

#define	FDCAN_CREL_SUBSTEP_MASK 0xF

#define	FDCAN_CREL_STEP_SHIFT 24
	STEP[3:0]: FDCAN core release stepping. More...

#define	FDCAN_CREL_STEP_MASK 0xF

#define	FDCAN_CREL_REL_SHIFT 28
	REL[3:0]: FDCAN core release number. More...

#define	FDCAN_CREL_REL_MASK 0xF

#define	FDCAN_DBTP_DSJW_SHIFT 0
	DSJW[3:0]: Synchronization jump width. More...

#define	FDCAN_DBTP_DSJW_MASK 0xF

#define	FDCAN_DBTP_DTSEG2_SHIFT 4
	DTSEG2[3:0]: Data time segment after sample point. More...

#define	FDCAN_DBTP_DTSEG2_MASK 0xF

#define	FDCAN_DBTP_DTSEG1_SHIFT 8
	DTSEG1[4:0]: Data time segment before sample point. More...

#define	FDCAN_DBTP_DTSEG1_MASK 0x1F

#define	FDCAN_DBTP_DBRP_SHIFT 16
	DBRP[4:0]: Data bit rate prescaler. More...

#define	FDCAN_DBTP_DBRP_MASK 0x1F

#define	FDCAN_DBTP_TDC (1 << 23)

#define	FDCAN_TEST_LBCK (1 << 4)

#define	FDCAN_TEST_TX_SHIFT 5
	TX[1:0]: Control of transmit pin. More...

#define	FDCAN_TEST_TX_MASK 0x3

#define	FDCAN_TEST_RX (1 << 7)

#define	FDCAN_RWD_WDC_SHIFT 0
	WDC[7:0]: RAM watchdog configuration. More...

#define	FDCAN_RWD_WDC_MASK 0xFF

#define	FDCAN_RWD_WDV_SHIFT 7
	WDV[7:0]: RAM watchdog actual value. More...

#define	FDCAN_RWD_WDV_MASK 0xFF

#define	FDCAN_CCCR_INIT_TIMEOUT 0x0000FFFF
	Timeout for FDCAN_CCCR register INIT bit to accept set value. More...

#define	FDCAN_NBTP_NTSEG2_SHIFT 0
	NTSEG2[6:0]: Nominal timing segment after sample point length. More...

#define	FDCAN_NBTP_NTSEG2_MASK 0x7F

#define	FDCAN_NBTP_NTSEG1_SHIFT 8
	NTSEG1[7:0]: Nominal timing segment before sample point length. More...

#define	FDCAN_NBTP_NTSEG1_MASK 0xFF

#define	FDCAN_NBTP_NBRP_SHIFT 16
	NBRP[8:0]: Norminal timing bit rate prescaler. More...

#define	FDCAN_NBTP_NBRP_MASK 0x1FF

#define	FDCAN_NBTP_NSJW_SHIFT 25
	NSJW[6:0]: Norminal timing resynchronization jumb width. More...

#define	FDCAN_NBTP_NSJW_MASK 0x7F

#define	FDCAN_TSCC_TSS_SHIFT 0
	TSS[1:0]: Timestamp select. More...

#define	FDCAN_TSCC_TSS_MASK 0x3

#define	FDCAN_TSCC_TCP_SHIFT 16
	TCP[3:0]: Timestamp counter prescaler. More...

#define	FDCAN_TSCC_TCP_MASK 0xF

#define	FDCAN_TSCV_TSC_SHIFT 0
	TSC[15:0]: Timestamp counter value. More...

#define	FDCAN_TSCV_TSC_MASK 0xFFFF

#define	FDCAN_TOCC_ETOC (1 << 0)

#define	FDCAN_TOCC_TOS_SHIFT 1
	TOS[1:0]: Timeout select. More...

#define	FDCAN_TOCC_TOS_MASK 0x3

#define	FDCAN_TOCC_TOP_SHIFT 16
	TOP[15:0]: Timeout period. More...

#define	FDCAN_TOCC_TOP_MASK 0xFFFF

#define	FDCAN_TOCV_TOC_SHIFT 0
	TOC[15:0]: Timeout counter. More...

#define	FDCAN_TOCV_TOC_MASK 0xFFFF

#define	FDCAN_ECR_TEC_SHIFT 0
	TEC[7:0]: Transmit error counter. More...

#define	FDCAN_ECR_TEC_MASK 0xFF

#define	FDCAN_ECR_REC_SHIFT 8
	REC[6:0]: Receive error counter. More...

#define	FDCAN_ECR_REC_MASK 0x7F

#define	FDCAN_ECR_RP (1 << 15)

#define	FDCAN_ECR_CEL_SHIFT 16
	CEL[7:0]: CAN error logging. More...

#define	FDCAN_ECR_CEL_MASK 0xFF

#define	FDCAN_PSR_LEC_SHIFT 0
	LEC[2:0]: Last error code. More...

#define	FDCAN_PSR_LEC_MASK 0x7

#define	FDCAN_PSR_ACT_SHIFT 3
	ACT[1:0]: CAN block activity. More...

#define	FDCAN_PSR_ACT_MASK 0x3

#define	FDCAN_PSR_EP (1 << 5)

#define	FDCAN_PSR_EW (1 << 6)

#define	FDCAN_PSR_BO (1 << 7)

#define	FDCAN_PSR_DLEC_SHIFT 8
	DLEC[2:0]: Last error code in data section. More...

#define	FDCAN_PSR_DLEC_MASK 0x7

#define	FDCAN_PSR_RESI (1 << 11)

#define	FDCAN_PSR_RBRSRESI1 (1 << 12)

#define	FDCAN_PSR_REDL (1 << 13)

#define	FDCAN_PSR_PXE (1 << 14)

#define	FDCAN_PSR_TDCV_SHIFT 16
	TDCV[6:0]: Transmitter delay compensation value. More...

#define	FDCAN_PSR_TDCV_MASK 0x7F

#define	FDCAN_TDCR_TDCF_SHIFT 0
	TDCF[6:0]: Transmitter delay compensation filter window length. More...

#define	FDCAN_TDCR_TDCF_MASK 0x7F

#define	FDCAN_TDCR_TDCO_SHIFT 8
	TDCO[6:0]: Transmitter delay compensation offset. More...

#define	FDCAN_TDCR_TDCO_MASK 0x7F

#define	FDCAN_ILE_INT0 (1 << 0)

#define	FDCAN_ILE_INT1 (1 << 1)

#define	FDCAN_XIDAM_EIDM_SHIFT 0
	EIDM[28:0]: Extended ID mask for filtering. More...

#define	FDCAN_XIDAM_EIDM_MASK 0x1FFFFFFF

#define	FDCAN_HPMS_BIDX_SHIFT 0
	BIDX[2:0]: Buffer index. More...

#define	FDCAN_HPMS_BIDX_MASK 0x7

#define	FDCAN_HPMS_MSI_SHIFT 6
	MSI[1:0]: Message storage indicator. More...

#define	FDCAN_HPMS_MSI_MASK 0x3

#define	FDCAN_HPMS_FIDX_SHIFT 8
	FIDX[4:0]: Filter index. More...

#define	FDCAN_HPMS_FIDX_MASK 0x1F

#define	FDCAN_HPMS_FLS (1 << 15)

#define	FDCAN_RXFIFO_FL_SHIFT 0
	Fill level of Rx FIFOs. More...

#define	FDCAN_RXFIFO_GI_SHIFT 8
	Get index of Rx FIFOs. More...

#define	FDCAN_RXFIFO_PI_SHIFT 16
	Put index of Rx FIFOs. More...

#define	FDCAN_RXFIFO_FF (1 << 24)

#define	FDCAN_RXFIFO_RFL (1 << 25)

#define	FDCAN_RXF0S_F0FL_SHIFT FDCAN_RXFIFO_FL_SHIFT
	F0FL[3:0]: Fill level of Rx FIFO 0. More...

#define	FDCAN_RXF0S_F0FL_MASK FDCAN_RXFIFO_FL_MASK

#define	FDCAN_RXF0S_F0GI_SHIFT FDCAN_RXFIFO_GI_SHIFT
	F0GI[1:0]: Get index of Rx FIFO 0. More...

#define	FDCAN_RXF0S_F0GI_MASK FDCAN_RXFIFO_GI_MASK

#define	FDCAN_RXF0S_F0PI_SHIFT FDCAN_RXFIFO_PI_SHIFT
	F0PI[1:0]: Put index of Rx FIFO 0. More...

#define	FDCAN_RXF0S_F0PI_MASK FDCAN_RXFIFO_PI_MASK

#define	FDCAN_RXF0S_F0F FDCAN_RXFIFO_FF

#define	FDCAN_RXF0S_RF0L FDCAN_RXFIFO_RFL

#define	FDCAN_RXFIFO_AI_SHIFT 0
	Rx FIFOs acknowledge index. More...

#define	FDCAN_RXF0A_R0AI_SHIFT FDCAN_RXFIFO_AI_SHIFT
	R0AI[2:0]: Rx FIFO 0 acknowledge index. More...

#define	FDCAN_RXF0A_R0AI_MASK FDCAN_RXFIFO_AI_MASK

#define	FDCAN_RXF1S_F1FL_SHIFT FDCAN_RXFIFO_FL_SHIFT
	F1FL[3:1]: Fill level of Rx FIFO 1. More...

#define	FDCAN_RXF1S_F1FL_MASK FDCAN_RXFIFO_FL_MASK

#define	FDCAN_RXF1S_F1GI_SHIFT FDCAN_RXFIFO_GI_SHIFT
	F1GI[1:1]: Get index of Rx FIFO 1. More...

#define	FDCAN_RXF1S_F1GI_MASK FDCAN_RXFIFO_GI_MASK

#define	FDCAN_RXF1S_F1PI_SHIFT FDCAN_RXFIFO_PI_SHIFT
	F1PI[1:1]: Put index of Rx FIFO 1. More...

#define	FDCAN_RXF1S_F1PI_MASK FDCAN_RXFIFO_PI_MASK

#define	FDCAN_RXF1S_F1F FDCAN_RXFIFO_FF

#define	FDCAN_RXF1S_RF1L FDCAN_RXFIFO_RFL

#define	FDCAN_RXF1A_R1AI_SHIFT FDCAN_RXFIFO_AI_SHIFT
	R1AI[2:0]: Rx FIFO 1 acknowledge index. More...

#define	FDCAN_RXF1A_R1AI_MASK FDCAN_RXFIFO_AI_MASK

#define	FDCAN_TXBC_TFQM (1 << 24)

#define	FDCAN_TXFQS_TFFL_SHIFT 0
	TFFL[2:0]: Tx FIFO free level. More...

#define	FDCAN_TXFQS_TFGI_SHIFT 8
	TFGI[1:0]: Tx FIFO get index. More...

#define	FDCAN_TXFQS_TFQPI_SHIFT 16
	TFQPI[1:0]: Tx FIFO put index. More...

#define	FDCAN_TXFQS_TFQF (1 << 21)

#define	FDCAN_TXEFS_EFFL_SHIFT 0
	EFFL[2:0]: Event FIFO fill level. More...

#define	FDCAN_TXEFS_EFGI_SHIFT 8
	EFG[1:0]: Event FIFO get index. More...

#define	FDCAN_TXEFS_EFPI_SHIFT 16
	EFPI[1:0]: Event FIFO put index. More...

#define	FDCAN_TXEFS_EFF (1 << 24)

#define	FDCAN_TXEFS_TEF (1 << 25)

#define	FDCAN_TXEFA_EFAI_SHIFT 0
	EFAI[1:0]: Event FIFO acknowledge index. More...

#define	FDCAN_TXEFA_EFAI_MASK 0x3

#define	FDCAN_SFT_SHIFT 30

#define	FDCAN_SFT_MASK 0x3

#define	FDCAN_SFEC_SHIFT 27

#define	FDCAN_SFEC_MASK 0x7

#define	FDCAN_SFID1_SHIFT 16

#define	FDCAN_SFID1_MASK 0x7FF

#define	FDCAN_SFID2_SHIFT 0

#define	FDCAN_SFID2_MASK 0x7FF

#define	FDCAN_EFEC_SHIFT 29

#define	FDCAN_EFEC_MASK 0x7

#define	FDCAN_EFID1_SHIFT 0

#define	FDCAN_EFID1_MASK 0x1FFFFFFF

#define	FDCAN_EFT_SHIFT 30

#define	FDCAN_EFT_MASK 0x3

#define	FDCAN_EFID2_SHIFT 0

#define	FDCAN_EFID2_MASK 0x1FFFFFFF

#define	FDCAN_FIFO_EID_SHIFT 0

#define	FDCAN_FIFO_EID_MASK 0x1FFFFFFF

#define	FDCAN_FIFO_SID_SHIFT 18

#define	FDCAN_FIFO_SID_MASK 0x7FF

#define	FDCAN_FIFO_DLC_SHIFT 16

#define	FDCAN_FIFO_DLC_MASK 0xF

#define	FDCAN_FIFO_MM_SHIFT 24

#define	FDCAN_FIFO_MM_MASK 0xFF

#define	FDCAN_FIFO_ANMF (1 << 31)

#define	FDCAN_FIFO_FIDX_SHIFT 24

#define	FDCAN_FIFO_FIDX_MASK 0x7F

#define	FDCAN_FIFO_RXTS_SHIFT 0

#define	FDCAN_FIFO_RXTS_MASK 0xFFFF

Functions
void	fdcan_init_std_filter_ram (uint32_t canport, uint32_t flssa, uint8_t lss)
	Initialize allocation of standard filter block in CAN message RAM. More...

void	fdcan_init_ext_filter_ram (uint32_t canport, uint32_t flesa, uint8_t lse)
	Initialize allocation of extended filter block in CAN message RAM. More...

void	fdcan_init_fifo_ram (uint32_t canport, unsigned fifo_id, uint32_t fxsa, uint8_t fxs)
	Initialize allocation of FIFO block in CAN message RAM. More...

void	fdcan_init_tx_event_ram (uint32_t canport, uint32_t tesa, uint8_t tes)
	Initialize allocation of transmit event block in CAN message RAM. More...

void	fdcan_init_tx_buffer_ram (uint32_t canport, uint32_t tbsa, uint8_t tbs)
	Initialize allocation of transmit queue block in CAN message RAM. More...

int	fdcan_set_rx_element_size (uint32_t canport, uint8_t rxbuf, uint8_t rxfifo0, uint8_t rxfifo1)
	Initialize size of data fields in reception buffers. More...

int	fdcan_set_tx_element_size (uint32_t canport, uint8_t txbuf)
	Initialize size of data fields in transmit buffers. More...

Detailed Description

Author: © 2021 Eduard Drusa <ventyl86 at netkosice dot sk>

LGPL License Terms libopencm3 License

Macro Definition Documentation

◆ CAN_MSG_SIZE

#define CAN_MSG_SIZE 0x2800

Definition at line 43 of file h7/fdcan.h.

◆ FDCAN_BLOCK_ID

#define FDCAN_BLOCK_ID ( can_base ) (((can_base) - CAN1)/(CAN2 - CAN1))

Definition at line 42 of file fdcan.h.

◆ FDCAN_CCCR

#define FDCAN_CCCR ( can_base ) MMIO32(can_base + 0x0018)

Definition at line 51 of file fdcan.h.

◆ FDCAN_CCCR_INIT_TIMEOUT

#define FDCAN_CCCR_INIT_TIMEOUT 0x0000FFFF

Timeout for FDCAN_CCCR register INIT bit to accept set value.

This timeout is required because FDCAN uses two different clocks feeding two different portions of block. There can be slight delay based on how clocks are set up. While amount of FDCAN_clk / FDCAN_pclk combinations is high and clock speeds may vary a lot, following value has been choosen as sane default. You are free to use any timeout value you want.

Definition at line 176 of file fdcan.h.

◆ FDCAN_CCU_CCFG

#define FDCAN_CCU_CCFG MMIO32(CAN_CCU_BASE + 0x0004)

Definition at line 101 of file h7/fdcan.h.

◆ FDCAN_CCU_CCFG_CDIV_MASK

#define FDCAN_CCU_CCFG_CDIV_MASK 0xF

Definition at line 225 of file h7/fdcan.h.

◆ FDCAN_CCU_CCFG_CDIV_SHIFT

#define FDCAN_CCU_CCFG_CDIV_SHIFT 16

CDIV[3:0]: Input clock divider.

Definition at line 224 of file h7/fdcan.h.

◆ FDCAN_CCU_CREL

#define FDCAN_CCU_CREL MMIO32(CAN_CCU_BASE + 0x0000)

Definition at line 102 of file h7/fdcan.h.

◆ FDCAN_CREL

#define FDCAN_CREL ( can_base ) MMIO32(can_base + 0x0000)

Definition at line 46 of file fdcan.h.

◆ FDCAN_CREL_DAY_MASK

#define FDCAN_CREL_DAY_MASK 0xFF

Definition at line 92 of file fdcan.h.

◆ FDCAN_CREL_DAY_SHIFT

#define FDCAN_CREL_DAY_SHIFT 0

DAY[7:0]: FDCAN core revision date.

Definition at line 91 of file fdcan.h.

◆ FDCAN_CREL_MON_MASK

#define FDCAN_CREL_MON_MASK 0xFF

Definition at line 96 of file fdcan.h.

◆ FDCAN_CREL_MON_SHIFT

#define FDCAN_CREL_MON_SHIFT 8

MON[7:0]: FDCAN core revision month.

Definition at line 95 of file fdcan.h.

◆ FDCAN_CREL_REL_MASK

#define FDCAN_CREL_REL_MASK 0xF

Definition at line 112 of file fdcan.h.

◆ FDCAN_CREL_REL_SHIFT

#define FDCAN_CREL_REL_SHIFT 28

REL[3:0]: FDCAN core release number.

Definition at line 111 of file fdcan.h.

◆ FDCAN_CREL_STEP_MASK

#define FDCAN_CREL_STEP_MASK 0xF

Definition at line 108 of file fdcan.h.

◆ FDCAN_CREL_STEP_SHIFT

#define FDCAN_CREL_STEP_SHIFT 24

STEP[3:0]: FDCAN core release stepping.

Definition at line 107 of file fdcan.h.

◆ FDCAN_CREL_SUBSTEP_MASK

#define FDCAN_CREL_SUBSTEP_MASK 0xF

Definition at line 104 of file fdcan.h.

◆ FDCAN_CREL_SUBSTEP_SHIFT

#define FDCAN_CREL_SUBSTEP_SHIFT 20

SUBSTEP[3:0]: FDCAN core release sub stepping.

Definition at line 103 of file fdcan.h.

◆ FDCAN_CREL_YEAR_MASK

#define FDCAN_CREL_YEAR_MASK 0xF

Definition at line 100 of file fdcan.h.

◆ FDCAN_CREL_YEAR_SHIFT

#define FDCAN_CREL_YEAR_SHIFT 16

YEAR[3:0]: FDCAN core revision year.

Definition at line 99 of file fdcan.h.

◆ FDCAN_DBTP

#define FDCAN_DBTP ( can_base ) MMIO32(can_base + 0x000C)

Definition at line 48 of file fdcan.h.

◆ FDCAN_DBTP_DBRP_MASK

#define FDCAN_DBTP_DBRP_MASK 0x1F

Definition at line 129 of file fdcan.h.

◆ FDCAN_DBTP_DBRP_SHIFT

#define FDCAN_DBTP_DBRP_SHIFT 16

DBRP[4:0]: Data bit rate prescaler.

Definition at line 128 of file fdcan.h.

◆ FDCAN_DBTP_DSJW_MASK

#define FDCAN_DBTP_DSJW_MASK 0xF

Definition at line 117 of file fdcan.h.

◆ FDCAN_DBTP_DSJW_SHIFT

#define FDCAN_DBTP_DSJW_SHIFT 0

DSJW[3:0]: Synchronization jump width.

Definition at line 116 of file fdcan.h.

◆ FDCAN_DBTP_DTSEG1_MASK

#define FDCAN_DBTP_DTSEG1_MASK 0x1F

Definition at line 125 of file fdcan.h.

◆ FDCAN_DBTP_DTSEG1_SHIFT

#define FDCAN_DBTP_DTSEG1_SHIFT 8

DTSEG1[4:0]: Data time segment before sample point.

Definition at line 124 of file fdcan.h.

◆ FDCAN_DBTP_DTSEG2_MASK

#define FDCAN_DBTP_DTSEG2_MASK 0xF

Definition at line 121 of file fdcan.h.

◆ FDCAN_DBTP_DTSEG2_SHIFT

#define FDCAN_DBTP_DTSEG2_SHIFT 4

DTSEG2[3:0]: Data time segment after sample point.

Definition at line 120 of file fdcan.h.

◆ FDCAN_DBTP_TDC

#define FDCAN_DBTP_TDC (1 << 23)

Definition at line 131 of file fdcan.h.

◆ FDCAN_ECR

#define FDCAN_ECR ( can_base ) MMIO32(can_base + 0x0040)

Definition at line 57 of file fdcan.h.

◆ FDCAN_ECR_CEL_MASK

#define FDCAN_ECR_CEL_MASK 0xFF

Definition at line 231 of file fdcan.h.

◆ FDCAN_ECR_CEL_SHIFT

#define FDCAN_ECR_CEL_SHIFT 16

CEL[7:0]: CAN error logging.

Definition at line 230 of file fdcan.h.

◆ FDCAN_ECR_REC_MASK

#define FDCAN_ECR_REC_MASK 0x7F

Definition at line 226 of file fdcan.h.

◆ FDCAN_ECR_REC_SHIFT

#define FDCAN_ECR_REC_SHIFT 8

REC[6:0]: Receive error counter.

Definition at line 225 of file fdcan.h.

◆ FDCAN_ECR_RP

#define FDCAN_ECR_RP (1 << 15)

Definition at line 228 of file fdcan.h.

◆ FDCAN_ECR_TEC_MASK

#define FDCAN_ECR_TEC_MASK 0xFF

Definition at line 222 of file fdcan.h.

◆ FDCAN_ECR_TEC_SHIFT

#define FDCAN_ECR_TEC_SHIFT 0

TEC[7:0]: Transmit error counter.

Definition at line 221 of file fdcan.h.

◆ FDCAN_EFEC_MASK

#define FDCAN_EFEC_MASK 0x7

Definition at line 593 of file fdcan.h.

◆ FDCAN_EFEC_SHIFT

#define FDCAN_EFEC_SHIFT 29

Definition at line 592 of file fdcan.h.

◆ FDCAN_EFID1_MASK

#define FDCAN_EFID1_MASK 0x1FFFFFFF

Definition at line 627 of file fdcan.h.

◆ FDCAN_EFID1_SHIFT

#define FDCAN_EFID1_SHIFT 0

Definition at line 626 of file fdcan.h.

◆ FDCAN_EFID2_MASK

#define FDCAN_EFID2_MASK 0x1FFFFFFF

Definition at line 654 of file fdcan.h.

◆ FDCAN_EFID2_SHIFT

#define FDCAN_EFID2_SHIFT 0

Definition at line 653 of file fdcan.h.

◆ FDCAN_EFT_MASK

#define FDCAN_EFT_MASK 0x3

Definition at line 630 of file fdcan.h.

◆ FDCAN_EFT_SHIFT

#define FDCAN_EFT_SHIFT 30

Definition at line 629 of file fdcan.h.

◆ FDCAN_ENDN

#define FDCAN_ENDN ( can_base ) MMIO32(can_base + 0x0004)

Definition at line 47 of file fdcan.h.

◆ FDCAN_FIFO_ANMF

#define FDCAN_FIFO_ANMF (1 << 31)

Definition at line 720 of file fdcan.h.

◆ FDCAN_FIFO_DLC_MASK

#define FDCAN_FIFO_DLC_MASK 0xF

Definition at line 715 of file fdcan.h.

◆ FDCAN_FIFO_DLC_SHIFT

#define FDCAN_FIFO_DLC_SHIFT 16

Definition at line 714 of file fdcan.h.

◆ FDCAN_FIFO_EID_MASK

#define FDCAN_FIFO_EID_MASK 0x1FFFFFFF

Definition at line 709 of file fdcan.h.

◆ FDCAN_FIFO_EID_SHIFT

#define FDCAN_FIFO_EID_SHIFT 0

Definition at line 708 of file fdcan.h.

◆ FDCAN_FIFO_FIDX_MASK

#define FDCAN_FIFO_FIDX_MASK 0x7F

Definition at line 722 of file fdcan.h.

◆ FDCAN_FIFO_FIDX_SHIFT

#define FDCAN_FIFO_FIDX_SHIFT 24

Definition at line 721 of file fdcan.h.

◆ FDCAN_FIFO_MM_MASK

#define FDCAN_FIFO_MM_MASK 0xFF

Definition at line 718 of file fdcan.h.

◆ FDCAN_FIFO_MM_SHIFT

#define FDCAN_FIFO_MM_SHIFT 24

Definition at line 717 of file fdcan.h.

◆ FDCAN_FIFO_RXTS_MASK

#define FDCAN_FIFO_RXTS_MASK 0xFFFF

Definition at line 725 of file fdcan.h.

◆ FDCAN_FIFO_RXTS_SHIFT

#define FDCAN_FIFO_RXTS_SHIFT 0

Definition at line 724 of file fdcan.h.

◆ FDCAN_FIFO_SID_MASK

#define FDCAN_FIFO_SID_MASK 0x7FF

Definition at line 712 of file fdcan.h.

◆ FDCAN_FIFO_SID_SHIFT

#define FDCAN_FIFO_SID_SHIFT 18

Definition at line 711 of file fdcan.h.

◆ FDCAN_FXS_MASK

#define FDCAN_FXS_MASK 0xFF

Definition at line 115 of file h7/fdcan.h.

◆ FDCAN_FXS_SHIFT

#define FDCAN_FXS_SHIFT 16

Definition at line 116 of file h7/fdcan.h.

◆ FDCAN_FXSA_MASK

#define FDCAN_FXSA_MASK 0x3FFF

Position of start address of relocatable object within register.

Definition at line 119 of file h7/fdcan.h.

◆ FDCAN_FXSA_SHIFT

#define FDCAN_FXSA_SHIFT 2

Definition at line 120 of file h7/fdcan.h.

◆ FDCAN_GFC

#define FDCAN_GFC ( can_base ) MMIO32(can_base + 0x0080)

Definition at line 45 of file h7/fdcan.h.

◆ FDCAN_GFC_ANFE_MASK

#define FDCAN_GFC_ANFE_MASK 0x3

Definition at line 109 of file h7/fdcan.h.

◆ FDCAN_GFC_ANFE_SHIFT

#define FDCAN_GFC_ANFE_SHIFT 2

ANFE[1:0]: Accept non-matching frames w/ extended ID.

Definition at line 108 of file h7/fdcan.h.

◆ FDCAN_GFC_ANFS_MASK

#define FDCAN_GFC_ANFS_MASK 0x3

Definition at line 113 of file h7/fdcan.h.

◆ FDCAN_GFC_ANFS_SHIFT

#define FDCAN_GFC_ANFS_SHIFT 4

ANFS[1:0]: Accept non-matching frames w/ standard ID.

Definition at line 112 of file h7/fdcan.h.

◆ FDCAN_GFC_RRFE

#define FDCAN_GFC_RRFE (1 << 0)

Definition at line 104 of file h7/fdcan.h.

◆ FDCAN_GFC_RRFS

#define FDCAN_GFC_RRFS (1 << 1)

Definition at line 105 of file h7/fdcan.h.

◆ FDCAN_HDAT2

#define FDCAN_HDAT2 ( can_base ) MMIO32(can_base + 0x009C)

Definition at line 53 of file h7/fdcan.h.

◆ FDCAN_HPMS

#define FDCAN_HPMS ( can_base ) MMIO32(can_base + 0x0094)

Definition at line 51 of file h7/fdcan.h.

◆ FDCAN_HPMS_BIDX_MASK

#define FDCAN_HPMS_BIDX_MASK 0x7

Definition at line 349 of file fdcan.h.

◆ FDCAN_HPMS_BIDX_SHIFT

#define FDCAN_HPMS_BIDX_SHIFT 0

BIDX[2:0]: Buffer index.

Definition at line 348 of file fdcan.h.

◆ FDCAN_HPMS_FIDX_MASK

#define FDCAN_HPMS_FIDX_MASK 0x1F

Definition at line 357 of file fdcan.h.

◆ FDCAN_HPMS_FIDX_SHIFT

#define FDCAN_HPMS_FIDX_SHIFT 8

FIDX[4:0]: Filter index.

Definition at line 356 of file fdcan.h.

◆ FDCAN_HPMS_FLS

#define FDCAN_HPMS_FLS (1 << 15)

Definition at line 359 of file fdcan.h.

◆ FDCAN_HPMS_MSI_MASK

#define FDCAN_HPMS_MSI_MASK 0x3

Definition at line 353 of file fdcan.h.

◆ FDCAN_HPMS_MSI_SHIFT

#define FDCAN_HPMS_MSI_SHIFT 6

MSI[1:0]: Message storage indicator.

Definition at line 352 of file fdcan.h.

◆ FDCAN_IE

#define FDCAN_IE ( can_base ) MMIO32(can_base + 0x0054)

Definition at line 61 of file fdcan.h.

◆ FDCAN_ILE

#define FDCAN_ILE ( can_base ) MMIO32(can_base + 0x005C)

Definition at line 63 of file fdcan.h.

◆ FDCAN_ILE_INT0

#define FDCAN_ILE_INT0 (1 << 0)

Definition at line 338 of file fdcan.h.

◆ FDCAN_ILE_INT1

#define FDCAN_ILE_INT1 (1 << 1)

Definition at line 339 of file fdcan.h.

◆ FDCAN_ILS

#define FDCAN_ILS ( can_base ) MMIO32(can_base + 0x0058)

Definition at line 62 of file fdcan.h.

◆ FDCAN_IR

#define FDCAN_IR ( can_base ) MMIO32(can_base + 0x0050)

Definition at line 60 of file fdcan.h.

◆ FDCAN_LFESA_OFFSET

#define FDCAN_LFESA_OFFSET ( can_base ) (FDCAN_XIDFC(can_base) & (FDCAN_XIDFC_FLESA_MASK << FDCAN_XIDFC_FLESA_SHIFT))

Definition at line 232 of file h7/fdcan.h.

◆ FDCAN_LFSSA_OFFSET

#define FDCAN_LFSSA_OFFSET ( can_base ) (FDCAN_SIDFC(can_base) & (FDCAN_SIDFC_FLSSA_MASK << FDCAN_SIDFC_FLSSA_SHIFT))

Definition at line 229 of file h7/fdcan.h.

◆ FDCAN_NBTP

#define FDCAN_NBTP ( can_base ) MMIO32(can_base + 0x001C)

Definition at line 52 of file fdcan.h.

◆ FDCAN_NBTP_NBRP_MASK

#define FDCAN_NBTP_NBRP_MASK 0x1FF

Definition at line 188 of file fdcan.h.

◆ FDCAN_NBTP_NBRP_SHIFT

#define FDCAN_NBTP_NBRP_SHIFT 16

NBRP[8:0]: Norminal timing bit rate prescaler.

Definition at line 187 of file fdcan.h.

◆ FDCAN_NBTP_NSJW_MASK

#define FDCAN_NBTP_NSJW_MASK 0x7F

Definition at line 192 of file fdcan.h.

◆ FDCAN_NBTP_NSJW_SHIFT

#define FDCAN_NBTP_NSJW_SHIFT 25

NSJW[6:0]: Norminal timing resynchronization jumb width.

Definition at line 191 of file fdcan.h.

◆ FDCAN_NBTP_NTSEG1_MASK

#define FDCAN_NBTP_NTSEG1_MASK 0xFF

Definition at line 184 of file fdcan.h.

◆ FDCAN_NBTP_NTSEG1_SHIFT

#define FDCAN_NBTP_NTSEG1_SHIFT 8

NTSEG1[7:0]: Nominal timing segment before sample point length.

Definition at line 183 of file fdcan.h.

◆ FDCAN_NBTP_NTSEG2_MASK

#define FDCAN_NBTP_NTSEG2_MASK 0x7F

Definition at line 180 of file fdcan.h.

◆ FDCAN_NBTP_NTSEG2_SHIFT

#define FDCAN_NBTP_NTSEG2_SHIFT 0

NTSEG2[6:0]: Nominal timing segment after sample point length.

Definition at line 179 of file fdcan.h.

◆ FDCAN_NDAT1

#define FDCAN_NDAT1 ( can_base ) MMIO32(can_base + 0x0098)

Definition at line 52 of file h7/fdcan.h.

◆ FDCAN_PSR

#define FDCAN_PSR ( can_base ) MMIO32(can_base + 0x0044)

Definition at line 58 of file fdcan.h.

◆ FDCAN_PSR_ACT_MASK

#define FDCAN_PSR_ACT_MASK 0x3

Definition at line 240 of file fdcan.h.

◆ FDCAN_PSR_ACT_SHIFT

#define FDCAN_PSR_ACT_SHIFT 3

ACT[1:0]: CAN block activity.

Definition at line 239 of file fdcan.h.

◆ FDCAN_PSR_BO

#define FDCAN_PSR_BO (1 << 7)

Definition at line 244 of file fdcan.h.

◆ FDCAN_PSR_DLEC_MASK

#define FDCAN_PSR_DLEC_MASK 0x7

Definition at line 247 of file fdcan.h.

◆ FDCAN_PSR_DLEC_SHIFT

#define FDCAN_PSR_DLEC_SHIFT 8

DLEC[2:0]: Last error code in data section.

Definition at line 246 of file fdcan.h.

◆ FDCAN_PSR_EP

#define FDCAN_PSR_EP (1 << 5)

Definition at line 242 of file fdcan.h.

◆ FDCAN_PSR_EW

#define FDCAN_PSR_EW (1 << 6)

Definition at line 243 of file fdcan.h.

◆ FDCAN_PSR_LEC_MASK

#define FDCAN_PSR_LEC_MASK 0x7

Definition at line 236 of file fdcan.h.

◆ FDCAN_PSR_LEC_SHIFT

#define FDCAN_PSR_LEC_SHIFT 0

LEC[2:0]: Last error code.

Definition at line 235 of file fdcan.h.

◆ FDCAN_PSR_PXE

#define FDCAN_PSR_PXE (1 << 14)

Definition at line 254 of file fdcan.h.

◆ FDCAN_PSR_RBRSRESI1

#define FDCAN_PSR_RBRSRESI1 (1 << 12)

Definition at line 252 of file fdcan.h.

◆ FDCAN_PSR_REDL

#define FDCAN_PSR_REDL (1 << 13)

Definition at line 253 of file fdcan.h.

◆ FDCAN_PSR_RESI

#define FDCAN_PSR_RESI (1 << 11)

Definition at line 249 of file fdcan.h.

◆ FDCAN_PSR_TDCV_MASK

#define FDCAN_PSR_TDCV_MASK 0x7F

Definition at line 258 of file fdcan.h.

◆ FDCAN_PSR_TDCV_SHIFT

#define FDCAN_PSR_TDCV_SHIFT 16

TDCV[6:0]: Transmitter delay compensation value.

Definition at line 257 of file fdcan.h.

◆ FDCAN_RWD

#define FDCAN_RWD ( can_base ) MMIO32(can_base + 0x0014)

Definition at line 50 of file fdcan.h.

◆ FDCAN_RWD_WDC_MASK

#define FDCAN_RWD_WDC_MASK 0xFF

Definition at line 142 of file fdcan.h.

◆ FDCAN_RWD_WDC_SHIFT

#define FDCAN_RWD_WDC_SHIFT 0

WDC[7:0]: RAM watchdog configuration.

Definition at line 141 of file fdcan.h.

◆ FDCAN_RWD_WDV_MASK

#define FDCAN_RWD_WDV_MASK 0xFF

Definition at line 146 of file fdcan.h.

◆ FDCAN_RWD_WDV_SHIFT

#define FDCAN_RWD_WDV_SHIFT 7

WDV[7:0]: RAM watchdog actual value.

Definition at line 145 of file fdcan.h.

◆ FDCAN_RXBC

#define FDCAN_RXBC ( can_base ) MMIO32(can_base + 0x00AC)

Definition at line 67 of file h7/fdcan.h.

◆ FDCAN_RXESC

#define FDCAN_RXESC ( can_base ) MMIO32(can_base + 0x00BC)

Definition at line 69 of file h7/fdcan.h.

◆ FDCAN_RXESC_F0DS_MASK

#define FDCAN_RXESC_F0DS_MASK 0x7

F0DS[3:0]: FIFO0 data field size.

Definition at line 198 of file h7/fdcan.h.

◆ FDCAN_RXESC_F0DS_SHIFT

#define FDCAN_RXESC_F0DS_SHIFT 0

Definition at line 199 of file h7/fdcan.h.

◆ FDCAN_RXESC_F1DS_MASK

#define FDCAN_RXESC_F1DS_MASK 0x7

F1DS[3:0]: FIFO1 data field size.

Definition at line 202 of file h7/fdcan.h.

◆ FDCAN_RXESC_F1DS_SHIFT

#define FDCAN_RXESC_F1DS_SHIFT 4

Definition at line 203 of file h7/fdcan.h.

◆ FDCAN_RXESC_RBDS_MASK

#define FDCAN_RXESC_RBDS_MASK 0x7

RBDS[3:0]: RX buffer data field size.

Definition at line 194 of file h7/fdcan.h.

◆ FDCAN_RXESC_RBDS_SHIFT

#define FDCAN_RXESC_RBDS_SHIFT 8

Definition at line 195 of file h7/fdcan.h.

◆ FDCAN_RXF0A

#define FDCAN_RXF0A ( can_base ) FDCAN_RXFIA(can_base, 0)

Definition at line 84 of file fdcan.h.

◆ FDCAN_RXF0A_R0AI_MASK

#define FDCAN_RXF0A_R0AI_MASK FDCAN_RXFIFO_AI_MASK

Definition at line 393 of file fdcan.h.

◆ FDCAN_RXF0A_R0AI_SHIFT

#define FDCAN_RXF0A_R0AI_SHIFT FDCAN_RXFIFO_AI_SHIFT

R0AI[2:0]: Rx FIFO 0 acknowledge index.

Definition at line 392 of file fdcan.h.

◆ FDCAN_RXF0C

#define FDCAN_RXF0C ( can_base ) FDCAN_RXFIC(can_base, 0)

Definition at line 61 of file h7/fdcan.h.

◆ FDCAN_RXF0C_F0OM

#define FDCAN_RXF0C_F0OM FDCAN_RXFIC_FIOM

Definition at line 165 of file h7/fdcan.h.

◆ FDCAN_RXF0C_F0S_MASK

#define FDCAN_RXF0C_F0S_MASK FDCAN_RXFIC_FIS_MASK

F0S[6:0]: FIFO0 size.

Definition at line 172 of file h7/fdcan.h.

◆ FDCAN_RXF0C_F0S_SHIFT

#define FDCAN_RXF0C_F0S_SHIFT FDCAN_RXFIC_FIS_SHIFT

Definition at line 173 of file h7/fdcan.h.

◆ FDCAN_RXF0C_F0SA_MASK

#define FDCAN_RXF0C_F0SA_MASK FDCAN_RXFIC_FISA_MASK

F0SA[13:0]: FIFO0 start address.

Definition at line 176 of file h7/fdcan.h.

◆ FDCAN_RXF0C_F0SA_SHIFT

#define FDCAN_RXF0C_F0SA_SHIFT FDCAN_RXFIC_FISA_SHIFT

Definition at line 177 of file h7/fdcan.h.

◆ FDCAN_RXF0C_F0WM_MASK

#define FDCAN_RXF0C_F0WM_MASK FDCAN_RXFIC_FIWM_MASK

F0WM[6:0]: FIFO0 watermark mode.

Definition at line 168 of file h7/fdcan.h.

◆ FDCAN_RXF0C_F0WM_SHIFT

#define FDCAN_RXF0C_F0WM_SHIFT FDCAN_RXFIC_FIWM_SHIFT

Definition at line 169 of file h7/fdcan.h.

◆ FDCAN_RXF0S

#define FDCAN_RXF0S ( can_base ) FDCAN_RXFIS(can_base, 0)

Definition at line 73 of file fdcan.h.

◆ FDCAN_RXF0S_F0F

#define FDCAN_RXF0S_F0F FDCAN_RXFIFO_FF

Definition at line 385 of file fdcan.h.

◆ FDCAN_RXF0S_F0FL_MASK

#define FDCAN_RXF0S_F0FL_MASK FDCAN_RXFIFO_FL_MASK

Definition at line 375 of file fdcan.h.

◆ FDCAN_RXF0S_F0FL_SHIFT

#define FDCAN_RXF0S_F0FL_SHIFT FDCAN_RXFIFO_FL_SHIFT

F0FL[3:0]: Fill level of Rx FIFO 0.

Definition at line 374 of file fdcan.h.

◆ FDCAN_RXF0S_F0GI_MASK

#define FDCAN_RXF0S_F0GI_MASK FDCAN_RXFIFO_GI_MASK

Definition at line 379 of file fdcan.h.

◆ FDCAN_RXF0S_F0GI_SHIFT

#define FDCAN_RXF0S_F0GI_SHIFT FDCAN_RXFIFO_GI_SHIFT

F0GI[1:0]: Get index of Rx FIFO 0.

Definition at line 378 of file fdcan.h.

◆ FDCAN_RXF0S_F0PI_MASK

#define FDCAN_RXF0S_F0PI_MASK FDCAN_RXFIFO_PI_MASK

Definition at line 383 of file fdcan.h.

◆ FDCAN_RXF0S_F0PI_SHIFT

#define FDCAN_RXF0S_F0PI_SHIFT FDCAN_RXFIFO_PI_SHIFT

F0PI[1:0]: Put index of Rx FIFO 0.

Definition at line 382 of file fdcan.h.

◆ FDCAN_RXF0S_RF0L

#define FDCAN_RXF0S_RF0L FDCAN_RXFIFO_RFL

Definition at line 386 of file fdcan.h.

◆ FDCAN_RXF1A

#define FDCAN_RXF1A ( can_base ) FDCAN_RXFIA(can_base, 1)

Definition at line 85 of file fdcan.h.

◆ FDCAN_RXF1A_R1AI_MASK

#define FDCAN_RXF1A_R1AI_MASK FDCAN_RXFIFO_AI_MASK

Definition at line 412 of file fdcan.h.

◆ FDCAN_RXF1A_R1AI_SHIFT

#define FDCAN_RXF1A_R1AI_SHIFT FDCAN_RXFIFO_AI_SHIFT

R1AI[2:0]: Rx FIFO 1 acknowledge index.

Definition at line 411 of file fdcan.h.

◆ FDCAN_RXF1C

#define FDCAN_RXF1C ( can_base ) FDCAN_RXFIC(can_base, 1)

Definition at line 62 of file h7/fdcan.h.

◆ FDCAN_RXF1C_F1OM

#define FDCAN_RXF1C_F1OM FDCAN_RXFIC_FIOM

Definition at line 179 of file h7/fdcan.h.

◆ FDCAN_RXF1C_F1S_MASK

#define FDCAN_RXF1C_F1S_MASK FDCAN_RXFIC_FIS_MASK

F1S[6:0]: FIFO1 size.

Definition at line 186 of file h7/fdcan.h.

◆ FDCAN_RXF1C_F1S_SHIFT

#define FDCAN_RXF1C_F1S_SHIFT FDCAN_RXFIC_FIS_SHIFT

Definition at line 187 of file h7/fdcan.h.

◆ FDCAN_RXF1C_F1SA_MASK

#define FDCAN_RXF1C_F1SA_MASK FDCAN_RXFIC_FISA_MASK

F1SA[13:0]: FIFO1 start address.

Definition at line 190 of file h7/fdcan.h.

◆ FDCAN_RXF1C_F1SA_SHIFT

#define FDCAN_RXF1C_F1SA_SHIFT FDCAN_RXFIC_FISA_SHIFT

Definition at line 191 of file h7/fdcan.h.

◆ FDCAN_RXF1C_F1WM_MASK

#define FDCAN_RXF1C_F1WM_MASK FDCAN_RXFIC_FIWM_MASK

F1WM[6:0]: FIFO1 watermark mode.

Definition at line 182 of file h7/fdcan.h.

◆ FDCAN_RXF1C_F1WM_SHIFT

#define FDCAN_RXF1C_F1WM_SHIFT FDCAN_RXFIC_FIWM_SHIFT

Definition at line 183 of file h7/fdcan.h.

◆ FDCAN_RXF1S

#define FDCAN_RXF1S ( can_base ) FDCAN_RXFIS(can_base, 1)

Definition at line 74 of file fdcan.h.

◆ FDCAN_RXF1S_F1F

#define FDCAN_RXF1S_F1F FDCAN_RXFIFO_FF

Definition at line 407 of file fdcan.h.

◆ FDCAN_RXF1S_F1FL_MASK

#define FDCAN_RXF1S_F1FL_MASK FDCAN_RXFIFO_FL_MASK

Definition at line 397 of file fdcan.h.

◆ FDCAN_RXF1S_F1FL_SHIFT

#define FDCAN_RXF1S_F1FL_SHIFT FDCAN_RXFIFO_FL_SHIFT

F1FL[3:1]: Fill level of Rx FIFO 1.

Definition at line 396 of file fdcan.h.

◆ FDCAN_RXF1S_F1GI_MASK

#define FDCAN_RXF1S_F1GI_MASK FDCAN_RXFIFO_GI_MASK

Definition at line 401 of file fdcan.h.

◆ FDCAN_RXF1S_F1GI_SHIFT

#define FDCAN_RXF1S_F1GI_SHIFT FDCAN_RXFIFO_GI_SHIFT

F1GI[1:1]: Get index of Rx FIFO 1.

Definition at line 400 of file fdcan.h.

◆ FDCAN_RXF1S_F1PI_MASK

#define FDCAN_RXF1S_F1PI_MASK FDCAN_RXFIFO_PI_MASK

Definition at line 405 of file fdcan.h.

◆ FDCAN_RXF1S_F1PI_SHIFT

#define FDCAN_RXF1S_F1PI_SHIFT FDCAN_RXFIFO_PI_SHIFT

F1PI[1:1]: Put index of Rx FIFO 1.

Definition at line 404 of file fdcan.h.

◆ FDCAN_RXF1S_RF1L

#define FDCAN_RXF1S_RF1L FDCAN_RXFIFO_RFL

Definition at line 408 of file fdcan.h.

◆ FDCAN_RXFI_OFFSET

#define FDCAN_RXFI_OFFSET 0x0010

Definition at line 56 of file h7/fdcan.h.

◆ FDCAN_RXFIA

#define FDCAN_RXFIA	(	can_base,
		fifo_id
	)	MMIO32(can_base + FDCAN_RXFIA_BASE + (FDCAN_RXFI_OFFSET * fifo_id))

Generic access to Rx FIFO acknowledge registers.

Parameters

can_base	FDCAN block base address FDCAN block base addresses
fifo_id	ID of FIFO, 0 or 1

Definition at line 81 of file fdcan.h.

◆ FDCAN_RXFIA_BASE

#define FDCAN_RXFIA_BASE 0x00A8

Definition at line 65 of file h7/fdcan.h.

◆ FDCAN_RXFIC

#define FDCAN_RXFIC	(	can_base,
		fifo_id
	)	MMIO32((can_base) + FDCAN_RXFIC_BASE + (FDCAN_RXFI_OFFSET * (fifo_id)))

Definition at line 58 of file h7/fdcan.h.

◆ FDCAN_RXFIC_BASE

#define FDCAN_RXFIC_BASE 0x00A0

Definition at line 55 of file h7/fdcan.h.

◆ FDCAN_RXFIC_FIOM

#define FDCAN_RXFIC_FIOM (1 << 31)

Definition at line 153 of file h7/fdcan.h.

◆ FDCAN_RXFIC_FIS_MASK

#define FDCAN_RXFIC_FIS_MASK 0x7F

Definition at line 158 of file h7/fdcan.h.

◆ FDCAN_RXFIC_FIS_SHIFT

#define FDCAN_RXFIC_FIS_SHIFT 16

Definition at line 159 of file h7/fdcan.h.

◆ FDCAN_RXFIC_FISA_MASK

#define FDCAN_RXFIC_FISA_MASK FDCAN_FXSA_MASK

Definition at line 162 of file h7/fdcan.h.

◆ FDCAN_RXFIC_FISA_SHIFT

#define FDCAN_RXFIC_FISA_SHIFT FDCAN_FXSA_SHIFT

Definition at line 163 of file h7/fdcan.h.

◆ FDCAN_RXFIC_FIWM_MASK

#define FDCAN_RXFIC_FIWM_MASK 0x7F

Definition at line 155 of file h7/fdcan.h.

◆ FDCAN_RXFIC_FIWM_SHIFT

#define FDCAN_RXFIC_FIWM_SHIFT 24

Definition at line 156 of file h7/fdcan.h.

◆ FDCAN_RXFIFO_AI_MASK

#define FDCAN_RXFIFO_AI_MASK 0x3F

Definition at line 213 of file h7/fdcan.h.

◆ FDCAN_RXFIFO_AI_SHIFT

#define FDCAN_RXFIFO_AI_SHIFT 0

Rx FIFOs acknowledge index.

Definition at line 389 of file fdcan.h.

◆ FDCAN_RXFIFO_FF

#define FDCAN_RXFIFO_FF (1 << 24)

Definition at line 370 of file fdcan.h.

◆ FDCAN_RXFIFO_FL_MASK

#define FDCAN_RXFIFO_FL_MASK 0x7F

Definition at line 209 of file h7/fdcan.h.

◆ FDCAN_RXFIFO_FL_SHIFT

#define FDCAN_RXFIFO_FL_SHIFT 0

Fill level of Rx FIFOs.

Definition at line 362 of file fdcan.h.

◆ FDCAN_RXFIFO_GI_MASK

#define FDCAN_RXFIFO_GI_MASK 0x3F

Definition at line 210 of file h7/fdcan.h.

◆ FDCAN_RXFIFO_GI_SHIFT

#define FDCAN_RXFIFO_GI_SHIFT 8

Get index of Rx FIFOs.

Definition at line 365 of file fdcan.h.

◆ FDCAN_RXFIFO_OFFSET

#define FDCAN_RXFIFO_OFFSET	(	can_base,
		fifo_id
	)	(FDCAN_RXFIC(can_base, fifo_id) & (FDCAN_FXSA_MASK << FDCAN_FXSA_SHIFT))

Definition at line 235 of file h7/fdcan.h.

◆ FDCAN_RXFIFO_PI_MASK

#define FDCAN_RXFIFO_PI_MASK 0x3F

Definition at line 211 of file h7/fdcan.h.

◆ FDCAN_RXFIFO_PI_SHIFT

#define FDCAN_RXFIFO_PI_SHIFT 16

Put index of Rx FIFOs.

Definition at line 368 of file fdcan.h.

◆ FDCAN_RXFIFO_RFL

#define FDCAN_RXFIFO_RFL (1 << 25)

Definition at line 371 of file fdcan.h.

◆ FDCAN_RXFIS

#define FDCAN_RXFIS	(	can_base,
		fifo_id
	)	MMIO32(can_base + FDCAN_RXFIS_BASE + (FDCAN_RXFI_OFFSET * fifo_id))

Generic access to Rx FIFO status registers.

Parameters

can_base	FDCAN block base address FDCAN block base addresses
fifo_id	ID of FIFO, 0 or 1

Definition at line 70 of file fdcan.h.

◆ FDCAN_RXFIS_BASE

#define FDCAN_RXFIS_BASE 0x00A4

Definition at line 64 of file h7/fdcan.h.

◆ FDCAN_SFEC_MASK

#define FDCAN_SFEC_MASK 0x7

Definition at line 540 of file fdcan.h.

◆ FDCAN_SFEC_SHIFT

#define FDCAN_SFEC_SHIFT 27

Definition at line 539 of file fdcan.h.

◆ FDCAN_SFID1_MASK

#define FDCAN_SFID1_MASK 0x7FF

Definition at line 576 of file fdcan.h.

◆ FDCAN_SFID1_SHIFT

#define FDCAN_SFID1_SHIFT 16

Definition at line 575 of file fdcan.h.

◆ FDCAN_SFID2_MASK

#define FDCAN_SFID2_MASK 0x7FF

Definition at line 579 of file fdcan.h.

◆ FDCAN_SFID2_SHIFT

#define FDCAN_SFID2_SHIFT 0

Definition at line 578 of file fdcan.h.

◆ FDCAN_SFT_MASK

#define FDCAN_SFT_MASK 0x3

Definition at line 518 of file fdcan.h.

◆ FDCAN_SFT_SHIFT

#define FDCAN_SFT_SHIFT 30

Definition at line 517 of file fdcan.h.

◆ FDCAN_SIDFC

#define FDCAN_SIDFC ( can_base ) MMIO32(can_base + 0x0084)

Definition at line 47 of file h7/fdcan.h.

◆ FDCAN_SIDFC_FLSSA_MASK

#define FDCAN_SIDFC_FLSSA_MASK FDCAN_FXSA_MASK

LFSSA[13:0]: Filter List standard start address.

Definition at line 127 of file h7/fdcan.h.

◆ FDCAN_SIDFC_FLSSA_SHIFT

#define FDCAN_SIDFC_FLSSA_SHIFT FDCAN_FXSA_SHIFT

Definition at line 128 of file h7/fdcan.h.

◆ FDCAN_SIDFC_LSS_MASK

#define FDCAN_SIDFC_LSS_MASK FDCAN_FXS_MASK

LSS[7:0]: List size of standard ID filters.

Definition at line 123 of file h7/fdcan.h.

◆ FDCAN_SIDFC_LSS_SHIFT

#define FDCAN_SIDFC_LSS_SHIFT FDCAN_FXS_SHIFT

Definition at line 124 of file h7/fdcan.h.

◆ FDCAN_TDCR

#define FDCAN_TDCR ( can_base ) MMIO32(can_base + 0x0048)

Definition at line 59 of file fdcan.h.

◆ FDCAN_TDCR_TDCF_MASK

#define FDCAN_TDCR_TDCF_MASK 0x7F

Definition at line 262 of file fdcan.h.

◆ FDCAN_TDCR_TDCF_SHIFT

#define FDCAN_TDCR_TDCF_SHIFT 0

TDCF[6:0]: Transmitter delay compensation filter window length.

Definition at line 261 of file fdcan.h.

◆ FDCAN_TDCR_TDCO_MASK

#define FDCAN_TDCR_TDCO_MASK 0x7F

Definition at line 266 of file fdcan.h.

◆ FDCAN_TDCR_TDCO_SHIFT

#define FDCAN_TDCR_TDCO_SHIFT 8

TDCO[6:0]: Transmitter delay compensation offset.

Definition at line 265 of file fdcan.h.

◆ FDCAN_TEST

#define FDCAN_TEST ( can_base ) MMIO32(can_base + 0x0010)

Definition at line 49 of file fdcan.h.

◆ FDCAN_TEST_LBCK

#define FDCAN_TEST_LBCK (1 << 4)

Definition at line 133 of file fdcan.h.

◆ FDCAN_TEST_RX

#define FDCAN_TEST_RX (1 << 7)

Definition at line 138 of file fdcan.h.

◆ FDCAN_TEST_TX_MASK

#define FDCAN_TEST_TX_MASK 0x3

Definition at line 136 of file fdcan.h.

◆ FDCAN_TEST_TX_SHIFT

#define FDCAN_TEST_TX_SHIFT 5

TX[1:0]: Control of transmit pin.

Definition at line 135 of file fdcan.h.

◆ FDCAN_TOCC

#define FDCAN_TOCC ( can_base ) MMIO32(can_base + 0x0028)

Definition at line 55 of file fdcan.h.

◆ FDCAN_TOCC_ETOC

#define FDCAN_TOCC_ETOC (1 << 0)

Definition at line 207 of file fdcan.h.

◆ FDCAN_TOCC_TOP_MASK

#define FDCAN_TOCC_TOP_MASK 0xFFFF

Definition at line 214 of file fdcan.h.

◆ FDCAN_TOCC_TOP_SHIFT

#define FDCAN_TOCC_TOP_SHIFT 16

TOP[15:0]: Timeout period.

Definition at line 213 of file fdcan.h.

◆ FDCAN_TOCC_TOS_MASK

#define FDCAN_TOCC_TOS_MASK 0x3

Definition at line 210 of file fdcan.h.

◆ FDCAN_TOCC_TOS_SHIFT

#define FDCAN_TOCC_TOS_SHIFT 1

TOS[1:0]: Timeout select.

Definition at line 209 of file fdcan.h.

◆ FDCAN_TOCV

#define FDCAN_TOCV ( can_base ) MMIO32(can_base + 0x002C)

Definition at line 56 of file fdcan.h.

◆ FDCAN_TOCV_TOC_MASK

#define FDCAN_TOCV_TOC_MASK 0xFFFF

Definition at line 218 of file fdcan.h.

◆ FDCAN_TOCV_TOC_SHIFT

#define FDCAN_TOCV_TOC_SHIFT 0

TOC[15:0]: Timeout counter.

Definition at line 217 of file fdcan.h.

◆ FDCAN_TSCC

#define FDCAN_TSCC ( can_base ) MMIO32(can_base + 0x0020)

Definition at line 53 of file fdcan.h.

◆ FDCAN_TSCC_TCP_MASK

#define FDCAN_TSCC_TCP_MASK 0xF

Definition at line 200 of file fdcan.h.

◆ FDCAN_TSCC_TCP_SHIFT

#define FDCAN_TSCC_TCP_SHIFT 16

TCP[3:0]: Timestamp counter prescaler.

Definition at line 199 of file fdcan.h.

◆ FDCAN_TSCC_TSS_MASK

#define FDCAN_TSCC_TSS_MASK 0x3

Definition at line 196 of file fdcan.h.

◆ FDCAN_TSCC_TSS_SHIFT

#define FDCAN_TSCC_TSS_SHIFT 0

TSS[1:0]: Timestamp select.

Definition at line 195 of file fdcan.h.

◆ FDCAN_TSCV

#define FDCAN_TSCV ( can_base ) MMIO32(can_base + 0x0024)

Definition at line 54 of file fdcan.h.

◆ FDCAN_TSCV_TSC_MASK

#define FDCAN_TSCV_TSC_MASK 0xFFFF

Definition at line 205 of file fdcan.h.

◆ FDCAN_TSCV_TSC_SHIFT

#define FDCAN_TSCV_TSC_SHIFT 0

TSC[15:0]: Timestamp counter value.

Definition at line 204 of file fdcan.h.

◆ FDCAN_TTCPT

#define FDCAN_TTCPT ( can_base ) MMIO32(can_base + 0x013C)

Definition at line 97 of file h7/fdcan.h.

◆ FDCAN_TTCSM

#define FDCAN_TTCSM ( can_base ) MMIO32(can_base + 0x0140)

Definition at line 98 of file h7/fdcan.h.

◆ FDCAN_TTCTC

#define FDCAN_TTCTC ( can_base ) MMIO32(can_base + 0x0138)

Definition at line 96 of file h7/fdcan.h.

◆ FDCAN_TTGTP

#define FDCAN_TTGTP ( can_base ) MMIO32(can_base + 0x0118)

Definition at line 88 of file h7/fdcan.h.

◆ FDCAN_TTIE

#define FDCAN_TTIE ( can_base ) MMIO32(can_base + 0x0124)

Definition at line 91 of file h7/fdcan.h.

◆ FDCAN_TTILS

#define FDCAN_TTILS ( can_base ) MMIO32(can_base + 0x0128)

Definition at line 92 of file h7/fdcan.h.

◆ FDCAN_TTLGT

#define FDCAN_TTLGT ( can_base ) MMIO32(can_base + 0x0134)

Definition at line 95 of file h7/fdcan.h.

◆ FDCAN_TTMLM

#define FDCAN_TTMLM ( can_base ) MMIO32(can_base + 0x010C)

Definition at line 85 of file h7/fdcan.h.

◆ FDCAN_TTOCF

#define FDCAN_TTOCF ( can_base ) MMIO32(can_base + 0x0108)

Definition at line 84 of file h7/fdcan.h.

◆ FDCAN_TTOCN

#define FDCAN_TTOCN ( can_base ) MMIO32(can_base + 0x0114)

Definition at line 87 of file h7/fdcan.h.

◆ FDCAN_TTOST

#define FDCAN_TTOST ( can_base ) MMIO32(can_base + 0x012C)

Definition at line 93 of file h7/fdcan.h.

◆ FDCAN_TTRMC

#define FDCAN_TTRMC ( can_base ) MMIO32(can_base + 0x0104)

Definition at line 83 of file h7/fdcan.h.

◆ FDCAN_TTTIR

#define FDCAN_TTTIR ( can_base ) MMIO32(can_base + 0x0120)

Definition at line 90 of file h7/fdcan.h.

◆ FDCAN_TTTMC

#define FDCAN_TTTMC ( can_base ) MMIO32(can_base + 0x0100)

Definition at line 82 of file h7/fdcan.h.

◆ FDCAN_TTTMK

#define FDCAN_TTTMK ( can_base ) MMIO32(can_base + 0x011C)

Definition at line 89 of file h7/fdcan.h.

◆ FDCAN_TTTS

#define FDCAN_TTTS ( can_base ) MMIO32(can_base + 0x0300)

Definition at line 99 of file h7/fdcan.h.

◆ FDCAN_TURCF

#define FDCAN_TURCF ( can_base ) MMIO32(can_base + 0x0110)

Definition at line 86 of file h7/fdcan.h.

◆ FDCAN_TURNA

#define FDCAN_TURNA ( can_base ) MMIO32(can_base + 0x0130)

Definition at line 94 of file h7/fdcan.h.

◆ FDCAN_TXBAR

#define FDCAN_TXBAR ( can_base ) MMIO32(can_base + 0x00D0)

Definition at line 72 of file h7/fdcan.h.

◆ FDCAN_TXBC

#define FDCAN_TXBC ( can_base ) MMIO32(can_base + 0x00C0)

Definition at line 87 of file fdcan.h.

◆ FDCAN_TXBC_TBSA_MASK

#define FDCAN_TXBC_TBSA_MASK FDCAN_FXSA_MASK

TBSA[7:0]: Transmit buffer start address.

Definition at line 143 of file h7/fdcan.h.

◆ FDCAN_TXBC_TBSA_SHIFT

#define FDCAN_TXBC_TBSA_SHIFT FDCAN_FXSA_SHIFT

Definition at line 144 of file h7/fdcan.h.

◆ FDCAN_TXBC_TFQM

#define FDCAN_TXBC_TFQM (1 << 24)

Definition at line 414 of file fdcan.h.

◆ FDCAN_TXBC_TFQS_MASK

#define FDCAN_TXBC_TFQS_MASK 0x3F

TFQS[5:0]: Tx FIFO/Queue size.

Definition at line 139 of file h7/fdcan.h.

◆ FDCAN_TXBC_TFQS_SHIFT

#define FDCAN_TXBC_TFQS_SHIFT 24

Definition at line 140 of file h7/fdcan.h.

◆ FDCAN_TXBCF

#define FDCAN_TXBCF ( can_base ) MMIO32(can_base + 0x00DC)

Definition at line 75 of file h7/fdcan.h.

◆ FDCAN_TXBCIE

#define FDCAN_TXBCIE ( can_base ) MMIO32(can_base + 0x00E4)

Definition at line 77 of file h7/fdcan.h.

◆ FDCAN_TXBCR

#define FDCAN_TXBCR ( can_base ) MMIO32(can_base + 0x00D4)

Definition at line 73 of file h7/fdcan.h.

◆ FDCAN_TXBRP

#define FDCAN_TXBRP ( can_base ) MMIO32(can_base + 0x00CC)

Definition at line 71 of file h7/fdcan.h.

◆ FDCAN_TXBTIE

#define FDCAN_TXBTIE ( can_base ) MMIO32(can_base + 0x00E0)

Definition at line 76 of file h7/fdcan.h.

◆ FDCAN_TXBTO

#define FDCAN_TXBTO ( can_base ) MMIO32(can_base + 0x00D8)

Definition at line 74 of file h7/fdcan.h.

◆ FDCAN_TXBUF_OFFSET

#define FDCAN_TXBUF_OFFSET ( can_base ) (FDCAN_TXBC(can_base) & (FDCAN_TXBC_TBSA_MASK << FDCAN_TXBC_TBSA_SHIFT))

Definition at line 238 of file h7/fdcan.h.

◆ FDCAN_TXEFA

#define FDCAN_TXEFA ( can_base ) MMIO32(can_base + 0x00F8)

Definition at line 80 of file h7/fdcan.h.

◆ FDCAN_TXEFA_EFAI_MASK

#define FDCAN_TXEFA_EFAI_MASK 0x3

Definition at line 503 of file fdcan.h.

◆ FDCAN_TXEFA_EFAI_SHIFT

#define FDCAN_TXEFA_EFAI_SHIFT 0

EFAI[1:0]: Event FIFO acknowledge index.

Definition at line 502 of file fdcan.h.

◆ FDCAN_TXEFC

#define FDCAN_TXEFC ( can_base ) MMIO32(can_base + 0x00F0)

Definition at line 78 of file h7/fdcan.h.

◆ FDCAN_TXEFC_EFS_MASK

#define FDCAN_TXEFC_EFS_MASK 0x3F

Definition at line 146 of file h7/fdcan.h.

◆ FDCAN_TXEFC_EFS_SHIFT

#define FDCAN_TXEFC_EFS_SHIFT 16

Definition at line 147 of file h7/fdcan.h.

◆ FDCAN_TXEFC_EFSA_MASK

#define FDCAN_TXEFC_EFSA_MASK FDCAN_FXSA_MASK

EFSA[7:0]: (Transmit) event FIFO start address.

Definition at line 150 of file h7/fdcan.h.

◆ FDCAN_TXEFC_EFSA_SHIFT

#define FDCAN_TXEFC_EFSA_SHIFT FDCAN_FXSA_SHIFT

Definition at line 151 of file h7/fdcan.h.

◆ FDCAN_TXEFS

#define FDCAN_TXEFS ( can_base ) MMIO32(can_base + 0x00F4)

Definition at line 79 of file h7/fdcan.h.

◆ FDCAN_TXEFS_EFF

#define FDCAN_TXEFS_EFF (1 << 24)

Definition at line 498 of file fdcan.h.

◆ FDCAN_TXEFS_EFFL_MASK

#define FDCAN_TXEFS_EFFL_MASK 0x3F

Definition at line 219 of file h7/fdcan.h.

◆ FDCAN_TXEFS_EFFL_SHIFT

#define FDCAN_TXEFS_EFFL_SHIFT 0

EFFL[2:0]: Event FIFO fill level.

Definition at line 490 of file fdcan.h.

◆ FDCAN_TXEFS_EFGI_MASK

#define FDCAN_TXEFS_EFGI_MASK 0x1F

Definition at line 220 of file h7/fdcan.h.

◆ FDCAN_TXEFS_EFGI_SHIFT

#define FDCAN_TXEFS_EFGI_SHIFT 8

EFG[1:0]: Event FIFO get index.

Definition at line 493 of file fdcan.h.

◆ FDCAN_TXEFS_EFPI_MASK

#define FDCAN_TXEFS_EFPI_MASK 0x1F

Definition at line 221 of file h7/fdcan.h.

◆ FDCAN_TXEFS_EFPI_SHIFT

#define FDCAN_TXEFS_EFPI_SHIFT 16

EFPI[1:0]: Event FIFO put index.

Definition at line 496 of file fdcan.h.

◆ FDCAN_TXEFS_TEF

#define FDCAN_TXEFS_TEF (1 << 25)

Definition at line 499 of file fdcan.h.

◆ FDCAN_TXESC

#define FDCAN_TXESC ( can_base ) MMIO32(can_base + 0x00C8)

Definition at line 70 of file h7/fdcan.h.

◆ FDCAN_TXESC_TBDS_MASK

#define FDCAN_TXESC_TBDS_MASK 0x7

TBDS[3:0]: TX buffer data field size.

Definition at line 206 of file h7/fdcan.h.

◆ FDCAN_TXESC_TBDS_SHIFT

#define FDCAN_TXESC_TBDS_SHIFT 0

Definition at line 207 of file h7/fdcan.h.

◆ FDCAN_TXEVT_OFFSET

#define FDCAN_TXEVT_OFFSET ( can_base ) (FDCAN_TXEFC(can_base) & (FDCAN_TXEFC_EFSA_MASK << FDCAN_TXEFC_EFSA_SHIFT))

Definition at line 241 of file h7/fdcan.h.

◆ FDCAN_TXFQS

#define FDCAN_TXFQS ( can_base ) MMIO32(can_base + 0x00C4)

Definition at line 88 of file fdcan.h.

◆ FDCAN_TXFQS_TFFL_MASK

#define FDCAN_TXFQS_TFFL_MASK 0x3F

Definition at line 215 of file h7/fdcan.h.

◆ FDCAN_TXFQS_TFFL_SHIFT

#define FDCAN_TXFQS_TFFL_SHIFT 0

TFFL[2:0]: Tx FIFO free level.

Definition at line 417 of file fdcan.h.

◆ FDCAN_TXFQS_TFGI_MASK

#define FDCAN_TXFQS_TFGI_MASK 0x1F

Definition at line 216 of file h7/fdcan.h.

◆ FDCAN_TXFQS_TFGI_SHIFT

#define FDCAN_TXFQS_TFGI_SHIFT 8

TFGI[1:0]: Tx FIFO get index.

Definition at line 420 of file fdcan.h.

◆ FDCAN_TXFQS_TFQF

#define FDCAN_TXFQS_TFQF (1 << 21)

Definition at line 425 of file fdcan.h.

◆ FDCAN_TXFQS_TFQPI_MASK

#define FDCAN_TXFQS_TFQPI_MASK 0x1F

Definition at line 217 of file h7/fdcan.h.

◆ FDCAN_TXFQS_TFQPI_SHIFT

#define FDCAN_TXFQS_TFQPI_SHIFT 16

TFQPI[1:0]: Tx FIFO put index.

Definition at line 423 of file fdcan.h.

◆ FDCAN_XIDAM

#define FDCAN_XIDAM ( can_base ) MMIO32(can_base + 0x0090)

Definition at line 49 of file h7/fdcan.h.

◆ FDCAN_XIDAM_EIDM_MASK

#define FDCAN_XIDAM_EIDM_MASK 0x1FFFFFFF

Definition at line 344 of file fdcan.h.

◆ FDCAN_XIDAM_EIDM_SHIFT

#define FDCAN_XIDAM_EIDM_SHIFT 0

EIDM[28:0]: Extended ID mask for filtering.

Definition at line 343 of file fdcan.h.

◆ FDCAN_XIDFC

#define FDCAN_XIDFC ( can_base ) MMIO32(can_base + 0x0088)

Definition at line 48 of file h7/fdcan.h.

◆ FDCAN_XIDFC_FLESA_MASK

#define FDCAN_XIDFC_FLESA_MASK FDCAN_FXSA_MASK

LFSSA[7:0]: Filter List extended start address.

Definition at line 135 of file h7/fdcan.h.

◆ FDCAN_XIDFC_FLESA_SHIFT

#define FDCAN_XIDFC_FLESA_SHIFT FDCAN_FXSA_SHIFT

Definition at line 136 of file h7/fdcan.h.

◆ FDCAN_XIDFC_LSE_MASK

#define FDCAN_XIDFC_LSE_MASK FDCAN_FXS_MASK

LSE[7:0]: List size of extended ID filters.

Definition at line 131 of file h7/fdcan.h.

◆ FDCAN_XIDFC_LSE_SHIFT

#define FDCAN_XIDFC_LSE_SHIFT FDCAN_FXS_SHIFT

Definition at line 132 of file h7/fdcan.h.

Function Documentation

◆ fdcan_init_ext_filter_ram()

void fdcan_init_ext_filter_ram	(	uint32_t	canport,
		uint32_t	flesa,
		uint8_t	lse
	)

Initialize allocation of extended filter block in CAN message RAM.

Allows specifying size of extended filtering block (in term of available filtering rules and filter base address within CAN message RAM. Note, that there are no limitations nor checking on address provided. It is possible to share whole filtering block or portion of it between multiple CAN interfaces.

Parameters

[in]	canport	FDCAN block base address. See FDCAN block base addresses.
[in]	flesa	extended filtering block start address offset in message RAM
[in]	lse	amount of extended filters

Definition at line 127 of file fdcan.c.

References FDCAN_XIDFC, FDCAN_XIDFC_FLESA_SHIFT, and FDCAN_XIDFC_LSE_SHIFT.

Referenced by fdcan_init_filter().

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◆ fdcan_init_fifo_ram()

void fdcan_init_fifo_ram	(	uint32_t	canport,
		unsigned	fifo_id,
		uint32_t	fxsa,
		uint8_t	fxs
	)

Initialize allocation of FIFO block in CAN message RAM.

Allows specifying size of FIFO block (in term of available messages in FIFO and FIFO base address within CAN message RAM. Note, that there are no limitations nor checking on address provided.

Parameters

[in]	canport	FDCAN block base address. See FDCAN block base addresses.
[in]	fifo_id	ID of fifo being configured
[in]	fxsa	FIFO block start address offset in message RAM
[in]	fxs	number of elements to assign

Definition at line 143 of file fdcan.c.

References FDCAN_RXFIC, FDCAN_RXFIC_FIS_MASK, FDCAN_RXFIC_FIS_SHIFT, FDCAN_RXFIC_FISA_MASK, and FDCAN_RXFIC_FISA_SHIFT.

Referenced by fdcan_start().

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◆ fdcan_init_std_filter_ram()

void fdcan_init_std_filter_ram	(	uint32_t	canport,
		uint32_t	flssa,
		uint8_t	lss
	)

Initialize allocation of standard filter block in CAN message RAM.

Allows specifying size of standard filtering block (in term of available filtering rules and filter base address within CAN message RAM. Note, that there are no limitations nor checking on address provided. It is possible to share whole filtering block or portion of it between multiple CAN interfaces.

Parameters

[in]	canport	FDCAN block base address. See FDCAN block base addresses.
[in]	flssa	standard filtering block start address offset in message RAM
[in]	lss	amount of standard filters

Definition at line 111 of file fdcan.c.

References FDCAN_SIDFC, FDCAN_SIDFC_FLSSA_SHIFT, and FDCAN_SIDFC_LSS_SHIFT.

Referenced by fdcan_init_filter().

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◆ fdcan_init_tx_buffer_ram()

void fdcan_init_tx_buffer_ram	(	uint32_t	canport,
		uint32_t	tbsa,
		uint8_t	tbs
	)

Initialize allocation of transmit queue block in CAN message RAM.

Allows specifying size of transmit queue block (in term of allocated buffers and block base address within CAN message RAM. Note, that there are no limitations nor checking on address provided.

Parameters

[in]	canport	FDCAN block base address. See FDCAN block base addresses.
[in]	tbsa	block start address offset in message RAM
[in]	tbs	number of elements to assign

Definition at line 183 of file fdcan.c.

References FDCAN_TXBC, FDCAN_TXBC_TBSA_MASK, FDCAN_TXBC_TBSA_SHIFT, FDCAN_TXBC_TFQS_MASK, and FDCAN_TXBC_TFQS_SHIFT.

Referenced by fdcan_start().

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◆ fdcan_init_tx_event_ram()

void fdcan_init_tx_event_ram	(	uint32_t	canport,
		uint32_t	tesa,
		uint8_t	tes
	)

Initialize allocation of transmit event block in CAN message RAM.

Allows specifying size of transmit event block (in term of allocated events and block base address within CAN message RAM. Note, that there are no limitations nor checking on address provided.

Parameters

[in]	canport	FDCAN block base address. See FDCAN block base addresses.
[in]	tesa	block start address offset in message RAM
[in]	tes	number of elements to assign

Definition at line 163 of file fdcan.c.

References FDCAN_TXEFC, FDCAN_TXEFC_EFS_MASK, FDCAN_TXEFC_EFS_SHIFT, FDCAN_TXEFC_EFSA_MASK, and FDCAN_TXEFC_EFSA_SHIFT.

Referenced by fdcan_start().

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◆ fdcan_set_rx_element_size()

int fdcan_set_rx_element_size	(	uint32_t	canport,
		uint8_t	rxbuf,
		uint8_t	rxfifo0,
		uint8_t	rxfifo1
	)

Initialize size of data fields in reception buffers.

Configures maximum size of message payload, which can be stored in different reception buffers. Each buffer can have maximum payload size configured independently. Buffers can only be configured to sizes which are valid sizes of FDCAN payload. Sizes smaller than 8 are automatically padded to 8.

Note: If you change these values, then content of reception buffers is invalidated. You may also want to recalculate base addresses of objects in message RAM as their size might have changed.

Parameters

[in]	canport	FDCAN block base address. See FDCAN block base addresses.
[in]	rxbuf	maximum storable payload size of dedicated RX buffer
[in]	rxfifo0	maximum storable payload size of RX FIFO 0
[in]	rxfifo1	maximum storable payload size of RX FIFO 1

Returns: operation return status. See FDCAN error return values.

Definition at line 209 of file fdcan.c.

References FDCAN_E_INVALID, FDCAN_E_OK, fdcan_length_to_dlc(), FDCAN_RXESC, FDCAN_RXESC_F0DS_SHIFT, FDCAN_RXESC_F1DS_SHIFT, and FDCAN_RXESC_RBDS_SHIFT.

Referenced by fdcan_start().

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◆ fdcan_set_tx_element_size()

int fdcan_set_tx_element_size	(	uint32_t	canport,
		uint8_t	txbuf
	)

Initialize size of data fields in transmit buffers.

Configures maximum size of message payload, which can be stored either in dedicated transmit buffer or into transmit queue/FIFO. One size is applied both to transmit buffer and transmit queue / FIFO. Buffers can only be configured to sizes which are valid sizes of FDCAN payload. Sizes smaller than 8 are automatically padded to 8 bytes.

Note: If you change these values, then content of transmission buffers is invalidated. You may also want to recalculate base addresses of objects in message RAM as their size might have changed.

Parameters

[in]	canport	FDCAN block base address. See FDCAN block base addresses.
[in]	txbuf	maximum storable payload size of TX buffer / FIFO / queue

Returns: operation return status. See FDCAN error return values.

Definition at line 261 of file fdcan.c.

References FDCAN_E_INVALID, FDCAN_E_OK, fdcan_length_to_dlc(), FDCAN_TXESC, and FDCAN_TXESC_TBDS_SHIFT.

Referenced by fdcan_start().

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Data Structures

Modules

Macros

Functions

Detailed Description

Macro Definition Documentation

◆ CAN_MSG_SIZE

◆ FDCAN_BLOCK_ID

◆ FDCAN_CCCR

◆ FDCAN_CCCR_INIT_TIMEOUT

◆ FDCAN_CCU_CCFG

◆ FDCAN_CCU_CCFG_CDIV_MASK

◆ FDCAN_CCU_CCFG_CDIV_SHIFT

◆ FDCAN_CCU_CREL

◆ FDCAN_CREL

◆ FDCAN_CREL_DAY_MASK

◆ FDCAN_CREL_DAY_SHIFT

◆ FDCAN_CREL_MON_MASK

◆ FDCAN_CREL_MON_SHIFT

◆ FDCAN_CREL_REL_MASK

◆ FDCAN_CREL_REL_SHIFT

◆ FDCAN_CREL_STEP_MASK

◆ FDCAN_CREL_STEP_SHIFT

◆ FDCAN_CREL_SUBSTEP_MASK

◆ FDCAN_CREL_SUBSTEP_SHIFT

◆ FDCAN_CREL_YEAR_MASK

◆ FDCAN_CREL_YEAR_SHIFT

◆ FDCAN_DBTP

◆ FDCAN_DBTP_DBRP_MASK

◆ FDCAN_DBTP_DBRP_SHIFT

◆ FDCAN_DBTP_DSJW_MASK

◆ FDCAN_DBTP_DSJW_SHIFT

◆ FDCAN_DBTP_DTSEG1_MASK

◆ FDCAN_DBTP_DTSEG1_SHIFT

◆ FDCAN_DBTP_DTSEG2_MASK

◆ FDCAN_DBTP_DTSEG2_SHIFT

◆ FDCAN_DBTP_TDC

◆ FDCAN_ECR

◆ FDCAN_ECR_CEL_MASK

◆ FDCAN_ECR_CEL_SHIFT

◆ FDCAN_ECR_REC_MASK

◆ FDCAN_ECR_REC_SHIFT

◆ FDCAN_ECR_RP

◆ FDCAN_ECR_TEC_MASK

◆ FDCAN_ECR_TEC_SHIFT

◆ FDCAN_EFEC_MASK

◆ FDCAN_EFEC_SHIFT

◆ FDCAN_EFID1_MASK

◆ FDCAN_EFID1_SHIFT

◆ FDCAN_EFID2_MASK

◆ FDCAN_EFID2_SHIFT

◆ FDCAN_EFT_MASK

◆ FDCAN_EFT_SHIFT

◆ FDCAN_ENDN

◆ FDCAN_FIFO_ANMF

◆ FDCAN_FIFO_DLC_MASK

◆ FDCAN_FIFO_DLC_SHIFT

◆ FDCAN_FIFO_EID_MASK

◆ FDCAN_FIFO_EID_SHIFT

◆ FDCAN_FIFO_FIDX_MASK

◆ FDCAN_FIFO_FIDX_SHIFT

◆ FDCAN_FIFO_MM_MASK

◆ FDCAN_FIFO_MM_SHIFT

◆ FDCAN_FIFO_RXTS_MASK

◆ FDCAN_FIFO_RXTS_SHIFT

◆ FDCAN_FIFO_SID_MASK

◆ FDCAN_FIFO_SID_SHIFT

◆ FDCAN_FXS_MASK

◆ FDCAN_FXS_SHIFT

◆ FDCAN_FXSA_MASK

◆ FDCAN_FXSA_SHIFT

◆ FDCAN_GFC

◆ FDCAN_GFC_ANFE_MASK

◆ FDCAN_GFC_ANFE_SHIFT

◆ FDCAN_GFC_ANFS_MASK

◆ FDCAN_GFC_ANFS_SHIFT

◆ FDCAN_GFC_RRFE

◆ FDCAN_GFC_RRFS

◆ FDCAN_HDAT2

◆ FDCAN_HPMS