#include <libopencm3/cm3/memorymap.h>
Go to the source code of this file.
Macros | |
| #define | FLASH_BASE 0x08000000U |
| #define | PERIPH_BASE 0x40000000U |
| #define | PERIPH_BASE_APB1 0x40000000U |
| #define | PERIPH_BASE_APB2 0x40010000U |
| #define | PERIPH_BASE_APB3 0x50000000U |
| #define | PERIPH_BASE_AHB1 0x40020000U |
| #define | PERIPH_BASE_AHB2 0x48020000U |
| #define | PERIPH_BASE_AHB3 0x51000000U |
| #define | PERIPH_BASE_AHB4 0x58000000U |
| #define | GPIO_PORT_A_BASE 0x58020000U |
| #define | GPIO_PORT_B_BASE 0x58020400U |
| #define | GPIO_PORT_C_BASE 0x58020800U |
| #define | GPIO_PORT_D_BASE 0x58020C00U |
| #define | GPIO_PORT_E_BASE 0x58021000U |
| #define | GPIO_PORT_F_BASE 0x58021400U |
| #define | GPIO_PORT_G_BASE 0x58021800U |
| #define | GPIO_PORT_H_BASE 0x58021C00U |
| #define | GPIO_PORT_I_BASE 0x58022000U |
| #define | GPIO_PORT_J_BASE 0x58022400U |
| #define | GPIO_PORT_K_BASE 0x58022800U |
| #define | RCC_BASE 0x58024400U |
| #define | POWER_CONTROL_BASE 0x58024800U |
| #define | CRC_BASE 0x58024C00U |
| #define | BDMA_BASE 0x58025400U |
| #define | DMAMUX2_BASE 0x58025800U |
| #define | ADC3_BASE 0x58026000U |
| #define | HSEM_BASE 0x58026400U |
| #define | SAI4_BASE 0x58005400U |
| #define | IWDG1_BASE 0x58004800U |
| #define | RTC_BASE 0x58004000U |
| #define | VREF_BASE 0x58003C00U |
| #define | COMP1_BASE 0x58003800U |
| #define | LPTIM5_BASE 0x58003000U |
| #define | LPTIM4_BASE 0x58002C00U |
| #define | LPTIM3_BASE 0x58002800U |
| #define | LPTIM2_BASE 0x58002400U |
| #define | I2C4_BASE 0x58001C00U |
| #define | SPI6_BASE 0x58001400U |
| #define | LPUART1_BASE 0x58000C00U |
| #define | SYSCFG_BASE 0x58000400U |
| #define | EXTI_BASE 0x58000000U |
| #define | DELAY_SDMMC1_BASE 0x52008000U |
| #define | SDMMC1_BASE 0x52007000U |
| #define | DELAY_QSPI_BASE 0x52006000U |
| #define | QUADSPI_BASE 0x52005000U |
| #define | FMC_BASE 0x52004000U |
| #define | JPEG_BASE 0x52003000U |
| #define | FLASH_MEM_INTERFACE_BASE 0x52002000U |
| #define | CHROMART_BASE 0x52001000U |
| #define | MDMA_BASE 0x52000000U |
| #define | GPV_BASE 0x51000000U |
| #define | WWDG1_BASE 0x50003000U |
| #define | LTDC_BASE 0x50001000U |
| #define | DELAY_SDMMC2_BASE 0x48022800U |
| #define | SDMMC2_BASE 0x48022400U |
| #define | RNG_BASE 0x48021800U |
| #define | HASH_BASE 0x48021400U |
| #define | CRYPTO_BASE 0x48021000U |
| #define | DCMI_BASE 0x48020000U |
| #define | USB2_OTG_FS_BASE 0x40080000U |
| #define | USB1_OTG_HS_BASE 0x40040000U |
| #define | ETHERNET_MAC_BASE 0x40028000U |
| #define | ADC1_ADC2_BASE 0x40022000U |
| #define | DMAMUX1_BASE 0x40020800U |
| #define | DMA2_BASE 0x40020400U |
| #define | DMA1_BASE 0x40020000U |
| #define | HRTIM_BASE 0x40017400U |
| #define | DFSDM1_BASE 0x40017000U |
| #define | SAI3_BASE 0x40016000U |
| #define | SAI2_BASE 0x40015C00U |
| #define | SAI1_BASE 0x40015800U |
| #define | SPI5_BASE 0x40015000U |
| #define | TIM17_BASE 0x40014800U |
| #define | TIM16_BASE 0x40014400U |
| #define | TIM15_BASE 0x40014000U |
| #define | SPI4_BASE 0x40013400U |
| #define | SPI1_BASE 0x40013000U |
| #define | USART6_BASE 0x40011400U |
| #define | USART1_BASE 0x40011000U |
| #define | TIM8_BASE 0x40010400U |
| #define | TIM1_BASE 0x40010000U |
| #define | CAN_MSG_BASE 0x4000AC00U |
| #define | CAN_CCU_BASE 0x4000A800U |
| #define | FDCAN2_BASE 0x4000A400U |
| #define | FDCAN1_BASE 0x4000A000U |
| #define | MDIOS_BASE 0x40009400U |
| #define | OPAMP_BASE 0x40009000U |
| #define | SWPMI_BASE 0x40008800U |
| #define | CRS_BASE 0x40008400U |
| #define | UART8_BASE 0x40007C00U |
| #define | UART7_BASE 0x40007800U |
| #define | DAC_BASE 0x40007400U |
| #define | HDMI_CEC_BASE 0x40006C00U |
| #define | I2C3_BASE 0x40005C00U |
| #define | I2C2_BASE 0x40005800U |
| #define | I2C1_BASE 0x40005400U |
| #define | UART5_BASE 0x40005000U |
| #define | UART4_BASE 0x40004C00U |
| #define | USART3_BASE 0x40004800U |
| #define | USART2_BASE 0x40004400U |
| #define | SPDIFRX1_BASE 0x40004000U |
| #define | SPI3_BASE 0x40003C00U |
| #define | SPI2_BASE 0x40003800U |
| #define | LPTIM1_BASE 0x40002400U |
| #define | TIM14_BASE 0x40002000U |
| #define | TIM13_BASE 0x40001C00U |
| #define | TIM12_BASE 0x40001800U |
| #define | TIM7_BASE 0x40001400U |
| #define | TIM6_BASE 0x40001000U |
| #define | TIM5_BASE 0x40000C00U |
| #define | TIM4_BASE 0x40000800U |
| #define | TIM3_BASE 0x40000400U |
| #define | TIM2_BASE 0x40000000U |
| #define | DBGMCU_BASE 0x5C001000U |
Macro Definition Documentation
◆ ADC1_ADC2_BASE
| #define ADC1_ADC2_BASE 0x40022000U |
Definition at line 102 of file stm32/h7/memorymap.h.
◆ ADC3_BASE
| #define ADC3_BASE 0x58026000U |
Definition at line 55 of file stm32/h7/memorymap.h.
◆ BDMA_BASE
| #define BDMA_BASE 0x58025400U |
Definition at line 53 of file stm32/h7/memorymap.h.
◆ CAN_CCU_BASE
| #define CAN_CCU_BASE 0x4000A800U |
Definition at line 126 of file stm32/h7/memorymap.h.
◆ CAN_MSG_BASE
| #define CAN_MSG_BASE 0x4000AC00U |
Definition at line 125 of file stm32/h7/memorymap.h.
◆ CHROMART_BASE
| #define CHROMART_BASE 0x52001000U |
Definition at line 82 of file stm32/h7/memorymap.h.
◆ COMP1_BASE
| #define COMP1_BASE 0x58003800U |
Definition at line 63 of file stm32/h7/memorymap.h.
◆ CRC_BASE
| #define CRC_BASE 0x58024C00U |
Definition at line 52 of file stm32/h7/memorymap.h.
◆ CRS_BASE
| #define CRS_BASE 0x40008400U |
Definition at line 132 of file stm32/h7/memorymap.h.
◆ CRYPTO_BASE
| #define CRYPTO_BASE 0x48021000U |
Definition at line 95 of file stm32/h7/memorymap.h.
◆ DAC_BASE
| #define DAC_BASE 0x40007400U |
Definition at line 135 of file stm32/h7/memorymap.h.
◆ DBGMCU_BASE
| #define DBGMCU_BASE 0x5C001000U |
Definition at line 159 of file stm32/h7/memorymap.h.
◆ DCMI_BASE
| #define DCMI_BASE 0x48020000U |
Definition at line 96 of file stm32/h7/memorymap.h.
◆ DELAY_QSPI_BASE
| #define DELAY_QSPI_BASE 0x52006000U |
Definition at line 77 of file stm32/h7/memorymap.h.
◆ DELAY_SDMMC1_BASE
| #define DELAY_SDMMC1_BASE 0x52008000U |
Definition at line 75 of file stm32/h7/memorymap.h.
◆ DELAY_SDMMC2_BASE
| #define DELAY_SDMMC2_BASE 0x48022800U |
Definition at line 91 of file stm32/h7/memorymap.h.
◆ DFSDM1_BASE
| #define DFSDM1_BASE 0x40017000U |
Definition at line 109 of file stm32/h7/memorymap.h.
◆ DMA1_BASE
| #define DMA1_BASE 0x40020000U |
Definition at line 105 of file stm32/h7/memorymap.h.
◆ DMA2_BASE
| #define DMA2_BASE 0x40020400U |
Definition at line 104 of file stm32/h7/memorymap.h.
◆ DMAMUX1_BASE
| #define DMAMUX1_BASE 0x40020800U |
Definition at line 103 of file stm32/h7/memorymap.h.
◆ DMAMUX2_BASE
| #define DMAMUX2_BASE 0x58025800U |
Definition at line 54 of file stm32/h7/memorymap.h.
◆ ETHERNET_MAC_BASE
| #define ETHERNET_MAC_BASE 0x40028000U |
Definition at line 101 of file stm32/h7/memorymap.h.
◆ EXTI_BASE
| #define EXTI_BASE 0x58000000U |
Definition at line 72 of file stm32/h7/memorymap.h.
◆ FDCAN1_BASE
| #define FDCAN1_BASE 0x4000A000U |
Definition at line 128 of file stm32/h7/memorymap.h.
◆ FDCAN2_BASE
| #define FDCAN2_BASE 0x4000A400U |
Definition at line 127 of file stm32/h7/memorymap.h.
◆ FLASH_BASE
| #define FLASH_BASE 0x08000000U |
Definition at line 26 of file stm32/h7/memorymap.h.
◆ FLASH_MEM_INTERFACE_BASE
| #define FLASH_MEM_INTERFACE_BASE 0x52002000U |
Definition at line 81 of file stm32/h7/memorymap.h.
◆ FMC_BASE
| #define FMC_BASE 0x52004000U |
Definition at line 79 of file stm32/h7/memorymap.h.
◆ GPIO_PORT_A_BASE
| #define GPIO_PORT_A_BASE 0x58020000U |
Definition at line 39 of file stm32/h7/memorymap.h.
◆ GPIO_PORT_B_BASE
| #define GPIO_PORT_B_BASE 0x58020400U |
Definition at line 40 of file stm32/h7/memorymap.h.
◆ GPIO_PORT_C_BASE
| #define GPIO_PORT_C_BASE 0x58020800U |
Definition at line 41 of file stm32/h7/memorymap.h.
◆ GPIO_PORT_D_BASE
| #define GPIO_PORT_D_BASE 0x58020C00U |
Definition at line 42 of file stm32/h7/memorymap.h.
◆ GPIO_PORT_E_BASE
| #define GPIO_PORT_E_BASE 0x58021000U |
Definition at line 43 of file stm32/h7/memorymap.h.
◆ GPIO_PORT_F_BASE
| #define GPIO_PORT_F_BASE 0x58021400U |
Definition at line 44 of file stm32/h7/memorymap.h.
◆ GPIO_PORT_G_BASE
| #define GPIO_PORT_G_BASE 0x58021800U |
Definition at line 45 of file stm32/h7/memorymap.h.
◆ GPIO_PORT_H_BASE
| #define GPIO_PORT_H_BASE 0x58021C00U |
Definition at line 46 of file stm32/h7/memorymap.h.
◆ GPIO_PORT_I_BASE
| #define GPIO_PORT_I_BASE 0x58022000U |
Definition at line 47 of file stm32/h7/memorymap.h.
◆ GPIO_PORT_J_BASE
| #define GPIO_PORT_J_BASE 0x58022400U |
Definition at line 48 of file stm32/h7/memorymap.h.
◆ GPIO_PORT_K_BASE
| #define GPIO_PORT_K_BASE 0x58022800U |
Definition at line 49 of file stm32/h7/memorymap.h.
◆ GPV_BASE
| #define GPV_BASE 0x51000000U |
Definition at line 84 of file stm32/h7/memorymap.h.
◆ HASH_BASE
| #define HASH_BASE 0x48021400U |
Definition at line 94 of file stm32/h7/memorymap.h.
◆ HDMI_CEC_BASE
| #define HDMI_CEC_BASE 0x40006C00U |
Definition at line 136 of file stm32/h7/memorymap.h.
◆ HRTIM_BASE
| #define HRTIM_BASE 0x40017400U |
Definition at line 108 of file stm32/h7/memorymap.h.
◆ HSEM_BASE
| #define HSEM_BASE 0x58026400U |
Definition at line 56 of file stm32/h7/memorymap.h.
◆ I2C1_BASE
| #define I2C1_BASE 0x40005400U |
Definition at line 139 of file stm32/h7/memorymap.h.
◆ I2C2_BASE
| #define I2C2_BASE 0x40005800U |
Definition at line 138 of file stm32/h7/memorymap.h.
◆ I2C3_BASE
| #define I2C3_BASE 0x40005C00U |
Definition at line 137 of file stm32/h7/memorymap.h.
◆ I2C4_BASE
| #define I2C4_BASE 0x58001C00U |
Definition at line 68 of file stm32/h7/memorymap.h.
◆ IWDG1_BASE
| #define IWDG1_BASE 0x58004800U |
Definition at line 60 of file stm32/h7/memorymap.h.
◆ JPEG_BASE
| #define JPEG_BASE 0x52003000U |
Definition at line 80 of file stm32/h7/memorymap.h.
◆ LPTIM1_BASE
| #define LPTIM1_BASE 0x40002400U |
Definition at line 147 of file stm32/h7/memorymap.h.
◆ LPTIM2_BASE
| #define LPTIM2_BASE 0x58002400U |
Definition at line 67 of file stm32/h7/memorymap.h.
◆ LPTIM3_BASE
| #define LPTIM3_BASE 0x58002800U |
Definition at line 66 of file stm32/h7/memorymap.h.
◆ LPTIM4_BASE
| #define LPTIM4_BASE 0x58002C00U |
Definition at line 65 of file stm32/h7/memorymap.h.
◆ LPTIM5_BASE
| #define LPTIM5_BASE 0x58003000U |
Definition at line 64 of file stm32/h7/memorymap.h.
◆ LPUART1_BASE
| #define LPUART1_BASE 0x58000C00U |
Definition at line 70 of file stm32/h7/memorymap.h.
◆ LTDC_BASE
| #define LTDC_BASE 0x50001000U |
Definition at line 88 of file stm32/h7/memorymap.h.
◆ MDIOS_BASE
| #define MDIOS_BASE 0x40009400U |
Definition at line 129 of file stm32/h7/memorymap.h.
◆ MDMA_BASE
| #define MDMA_BASE 0x52000000U |
Definition at line 83 of file stm32/h7/memorymap.h.
◆ OPAMP_BASE
| #define OPAMP_BASE 0x40009000U |
Definition at line 130 of file stm32/h7/memorymap.h.
◆ PERIPH_BASE
| #define PERIPH_BASE 0x40000000U |
Definition at line 27 of file stm32/h7/memorymap.h.
◆ PERIPH_BASE_AHB1
| #define PERIPH_BASE_AHB1 0x40020000U |
Definition at line 31 of file stm32/h7/memorymap.h.
◆ PERIPH_BASE_AHB2
| #define PERIPH_BASE_AHB2 0x48020000U |
Definition at line 32 of file stm32/h7/memorymap.h.
◆ PERIPH_BASE_AHB3
| #define PERIPH_BASE_AHB3 0x51000000U |
Definition at line 33 of file stm32/h7/memorymap.h.
◆ PERIPH_BASE_AHB4
| #define PERIPH_BASE_AHB4 0x58000000U |
Definition at line 34 of file stm32/h7/memorymap.h.
◆ PERIPH_BASE_APB1
| #define PERIPH_BASE_APB1 0x40000000U |
Definition at line 28 of file stm32/h7/memorymap.h.
◆ PERIPH_BASE_APB2
| #define PERIPH_BASE_APB2 0x40010000U |
Definition at line 29 of file stm32/h7/memorymap.h.
◆ PERIPH_BASE_APB3
| #define PERIPH_BASE_APB3 0x50000000U |
Definition at line 30 of file stm32/h7/memorymap.h.
◆ POWER_CONTROL_BASE
| #define POWER_CONTROL_BASE 0x58024800U |
Definition at line 51 of file stm32/h7/memorymap.h.
◆ QUADSPI_BASE
| #define QUADSPI_BASE 0x52005000U |
Definition at line 78 of file stm32/h7/memorymap.h.
◆ RCC_BASE
| #define RCC_BASE 0x58024400U |
Definition at line 50 of file stm32/h7/memorymap.h.
◆ RNG_BASE
| #define RNG_BASE 0x48021800U |
Definition at line 93 of file stm32/h7/memorymap.h.
◆ RTC_BASE
| #define RTC_BASE 0x58004000U |
Definition at line 61 of file stm32/h7/memorymap.h.
◆ SAI1_BASE
| #define SAI1_BASE 0x40015800U |
Definition at line 112 of file stm32/h7/memorymap.h.
◆ SAI2_BASE
| #define SAI2_BASE 0x40015C00U |
Definition at line 111 of file stm32/h7/memorymap.h.
◆ SAI3_BASE
| #define SAI3_BASE 0x40016000U |
Definition at line 110 of file stm32/h7/memorymap.h.
◆ SAI4_BASE
| #define SAI4_BASE 0x58005400U |
Definition at line 59 of file stm32/h7/memorymap.h.
◆ SDMMC1_BASE
| #define SDMMC1_BASE 0x52007000U |
Definition at line 76 of file stm32/h7/memorymap.h.
◆ SDMMC2_BASE
| #define SDMMC2_BASE 0x48022400U |
Definition at line 92 of file stm32/h7/memorymap.h.
◆ SPDIFRX1_BASE
| #define SPDIFRX1_BASE 0x40004000U |
Definition at line 144 of file stm32/h7/memorymap.h.
◆ SPI1_BASE
| #define SPI1_BASE 0x40013000U |
Definition at line 118 of file stm32/h7/memorymap.h.
◆ SPI2_BASE
| #define SPI2_BASE 0x40003800U |
Definition at line 146 of file stm32/h7/memorymap.h.
◆ SPI3_BASE
| #define SPI3_BASE 0x40003C00U |
Definition at line 145 of file stm32/h7/memorymap.h.
◆ SPI4_BASE
| #define SPI4_BASE 0x40013400U |
Definition at line 117 of file stm32/h7/memorymap.h.
◆ SPI5_BASE
| #define SPI5_BASE 0x40015000U |
Definition at line 113 of file stm32/h7/memorymap.h.
◆ SPI6_BASE
| #define SPI6_BASE 0x58001400U |
Definition at line 69 of file stm32/h7/memorymap.h.
◆ SWPMI_BASE
| #define SWPMI_BASE 0x40008800U |
Definition at line 131 of file stm32/h7/memorymap.h.
◆ SYSCFG_BASE
| #define SYSCFG_BASE 0x58000400U |
Definition at line 71 of file stm32/h7/memorymap.h.
◆ TIM12_BASE
| #define TIM12_BASE 0x40001800U |
Definition at line 150 of file stm32/h7/memorymap.h.
◆ TIM13_BASE
| #define TIM13_BASE 0x40001C00U |
Definition at line 149 of file stm32/h7/memorymap.h.
◆ TIM14_BASE
| #define TIM14_BASE 0x40002000U |
Definition at line 148 of file stm32/h7/memorymap.h.
◆ TIM15_BASE
| #define TIM15_BASE 0x40014000U |
Definition at line 116 of file stm32/h7/memorymap.h.
◆ TIM16_BASE
| #define TIM16_BASE 0x40014400U |
Definition at line 115 of file stm32/h7/memorymap.h.
◆ TIM17_BASE
| #define TIM17_BASE 0x40014800U |
Definition at line 114 of file stm32/h7/memorymap.h.
◆ TIM1_BASE
| #define TIM1_BASE 0x40010000U |
Definition at line 122 of file stm32/h7/memorymap.h.
◆ TIM2_BASE
| #define TIM2_BASE 0x40000000U |
Definition at line 156 of file stm32/h7/memorymap.h.
◆ TIM3_BASE
| #define TIM3_BASE 0x40000400U |
Definition at line 155 of file stm32/h7/memorymap.h.
◆ TIM4_BASE
| #define TIM4_BASE 0x40000800U |
Definition at line 154 of file stm32/h7/memorymap.h.
◆ TIM5_BASE
| #define TIM5_BASE 0x40000C00U |
Definition at line 153 of file stm32/h7/memorymap.h.
◆ TIM6_BASE
| #define TIM6_BASE 0x40001000U |
Definition at line 152 of file stm32/h7/memorymap.h.
◆ TIM7_BASE
| #define TIM7_BASE 0x40001400U |
Definition at line 151 of file stm32/h7/memorymap.h.
◆ TIM8_BASE
| #define TIM8_BASE 0x40010400U |
Definition at line 121 of file stm32/h7/memorymap.h.
◆ UART4_BASE
| #define UART4_BASE 0x40004C00U |
Definition at line 141 of file stm32/h7/memorymap.h.
◆ UART5_BASE
| #define UART5_BASE 0x40005000U |
Definition at line 140 of file stm32/h7/memorymap.h.
◆ UART7_BASE
| #define UART7_BASE 0x40007800U |
Definition at line 134 of file stm32/h7/memorymap.h.
◆ UART8_BASE
| #define UART8_BASE 0x40007C00U |
Definition at line 133 of file stm32/h7/memorymap.h.
◆ USART1_BASE
| #define USART1_BASE 0x40011000U |
Definition at line 120 of file stm32/h7/memorymap.h.
◆ USART2_BASE
| #define USART2_BASE 0x40004400U |
Definition at line 143 of file stm32/h7/memorymap.h.
◆ USART3_BASE
| #define USART3_BASE 0x40004800U |
Definition at line 142 of file stm32/h7/memorymap.h.
◆ USART6_BASE
| #define USART6_BASE 0x40011400U |
Definition at line 119 of file stm32/h7/memorymap.h.
◆ USB1_OTG_HS_BASE
| #define USB1_OTG_HS_BASE 0x40040000U |
Definition at line 100 of file stm32/h7/memorymap.h.
◆ USB2_OTG_FS_BASE
| #define USB2_OTG_FS_BASE 0x40080000U |
Definition at line 99 of file stm32/h7/memorymap.h.
◆ VREF_BASE
| #define VREF_BASE 0x58003C00U |
Definition at line 62 of file stm32/h7/memorymap.h.
◆ WWDG1_BASE
| #define WWDG1_BASE 0x50003000U |
Definition at line 87 of file stm32/h7/memorymap.h.
