libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
dwt.c
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1/** @defgroup CM3_dwt_file DWT
2 *
3 * @ingroup CM3_files
4 *
5 * @brief <b>libopencm3 Cortex-M Data Watchpoint and Trace unit</b>
6 *
7 * The DWT provides
8 * * Comparators, that support
9 * * watch points
10 * * data tracing
11 * * signalling to ETM
12 * * PC value tracing
13 * * cycle count matching
14 * * extra PC sampling
15 * * Sampling as a result of a clock count
16 * * external access for sampling
17 * * exception trace
18 * * performance profiling counters.
19 *
20 * Which of these features are available is unfortunately implementation defined.
21 *
22 * @see ARMv7m Architecture Reference Manual (Chapter ARMv7-M Debug)
23 *
24 * LGPL License Terms @ref lgpl_license
25 * @{
26 */
27/*
28 * This file is part of the libopencm3 project.
29 *
30 * Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
31 *
32 * This library is free software: you can redistribute it and/or modify
33 * it under the terms of the GNU Lesser General Public License as published by
34 * the Free Software Foundation, either version 3 of the License, or
35 * (at your option) any later version.
36 *
37 * This library is distributed in the hope that it will be useful,
38 * but WITHOUT ANY WARRANTY; without even the implied warranty of
39 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
40 * GNU Lesser General Public License for more details.
41 *
42 * You should have received a copy of the GNU Lesser General Public License
43 * along with this library. If not, see <http://www.gnu.org/licenses/>.
44 */
45
46#include <libopencm3/cm3/scs.h>
47#include <libopencm3/cm3/dwt.h>
48
49/*---------------------------------------------------------------------------*/
50/** @brief DebugTrace Enable the CPU cycle counter
51 *
52 * This function will try to enable the CPU cycle counter that is intended for
53 * benchmarking performance of the code. If function fails, the cycle counter
54 * isn't available on this architecture.
55 *
56 * @return true, if success
57 */
59{
60#if defined(__ARM_ARCH_6M__)
61 return false; /* Not supported on ARMv6M */
62#endif /* defined(__ARM_ARCH_6M__) */
63
64#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
65 /* Note TRCENA is for 7M and above*/
67 if (DWT_CTRL & DWT_CTRL_NOCYCCNT) {
68 return false; /* Not supported in implementation */
69 }
70
71 DWT_CYCCNT = 0;
72 DWT_CTRL |= DWT_CTRL_CYCCNTENA;
73 return true;
74#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
75
76 /* not supported on other architectures */
77 return false;
78}
79/*---------------------------------------------------------------------------*/
80/** @brief DebugTrace Read the CPU cycle counter
81 *
82 * This function reads the core cycle counter if it is enabled. It is the
83 * fastest clock running on the system.
84 *
85 * @note The CPU cycle counter must be enabled by @ref dwt_enable_cycle_counter
86 *
87 * @returns 0 if cycle counter is not supported or enabled, the cycle counter
88 * value otherwise.
89 */
91{
92#if defined(__ARM_ARCH_6M__)
93 return 0; /* Not supported on ARMv6M */
94#endif /* defined(__ARM_ARCH_6M__) */
95
96#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
97 if (DWT_CTRL & DWT_CTRL_CYCCNTENA) {
98 return DWT_CYCCNT;
99 } else {
100 return 0; /* not supported or enabled */
101 }
102#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
103}
104
105/**@}*/
uint32_t dwt_read_cycle_counter(void)
DebugTrace Read the CPU cycle counter.
Definition: dwt.c:90
bool dwt_enable_cycle_counter(void)
DebugTrace Enable the CPU cycle counter.
Definition: dwt.c:58
#define DWT_CTRL
DWT Control register Purpose Provides configuration and status information for the DWT block,...
Definition: dwt.h:47
#define SCS_DEMCR
Debug Exception and Monitor Control Register (DEMCR).
Definition: scs.h:105
#define SCS_DEMCR_TRCENA
Definition: scs.h:131