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| #define | SYSCFG_CFGR1 MMIO32(SYSCFG_BASE + 0x00) |
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| #define | SYSCFG_CFGR2 MMIO32(SYSCFG_BASE + 0x04) |
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| #define | SYSCFG_EXTICR(i) MMIO32(SYSCFG_BASE + 0x08 + (i)*4) |
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| #define | SYSCFG_EXTICR1 SYSCFG_EXTICR(0) |
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| #define | SYSCFG_EXTICR2 SYSCFG_EXTICR(1) |
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| #define | SYSCFG_EXTICR3 SYSCFG_EXTICR(2) |
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| #define | SYSCFG_EXTICR4 SYSCFG_EXTICR(3) |
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| #define | COMP1_CTRL MMIO32(SYSCFG_BASE + 0x18) |
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| #define | COMP2_CTRL MMIO32(SYSCFG_BASE + 0x1C) |
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| #define | SYSCFG_CFGR3 MMIO32(SYSCFG_BASE + 0x20) |
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| #define | SYSCFG_CFGR1_MEM_MODE_SHIFT 0 |
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| #define | SYSCFG_CFGR1_MEM_MODE (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT) |
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| #define | SYSCFG_CFGR1_MEM_MODE_FLASH (0 << SYSCFG_CFGR1_MEM_MODE_SHIFT) |
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| #define | SYSCFG_CFGR1_MEM_MODE_SYSTEM (1 << SYSCFG_CFGR1_MEM_MODE_SHIFT) |
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| #define | SYSCFG_CFGR1_MEM_MODE_SRAM (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT) |
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| #define | SYSCFG_CFGR1_UFB (1<<3) |
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| #define | SYSCFG_CFGR1_BOOT_MODE_SHIFT 8 |
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| #define | SYSCFG_CFGR1_BOOT_MODE (3 << SYSCFG_CFGR1_BOOT_MODE_SHIFT) |
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| #define | SYSCFG_CFGR1_BOOT_MODE_FLASH (0 << SYSCFG_CFGR1_BOOT_MODE_SHIFT) |
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| #define | SYSCFG_CFGR1_BOOT_MODE_SYSTEM (1 << SYSCFG_CFGR1_BOOT_MODE_SHIFT) |
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| #define | SYSCFG_CFGR1_BOOT_MODE_SRAM (3 << SYSCFG_CFGR1_BOOT_MODE_SHIFT) |
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| #define | SYSCFG_CFGR2_FWDIS (1 << 0) |
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| #define | SYSCFG_CFGR2_I2C_PB6_FMP (1 << 8) |
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| #define | SYSCFG_CFGR2_I2C_PB7_FMP (1 << 9) |
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| #define | SYSCFG_CFGR2_I2C_PB8_FMP (1 << 10) |
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| #define | SYSCFG_CFGR2_I2C_PB9_FMP (1 << 11) |
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| #define | SYSCFG_CFGR2_I2C1_FMP (1 << 12) |
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| #define | SYSCFG_CFGR2_I2C2_FMP (1 << 13) |
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| #define | SYSCFG_CFGR2_I2C3_FMP (1 << 14) |
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| #define | SYSCFG_CFGR3_EN_VREFINT (1 << 0) |
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| #define | SYSCFG_CFGR3_SEL_VREF_OUT_SHIFT 4 |
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| #define | SYSCFG_CFGR3_SEL_VREF_OUT (3 << SYSCFG_CFGR3_EN_VREFINT_SHIFT) |
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| #define | SYSCFG_CFGR3_SEL_VREF_OUT_PB0 (1 << SYSCFG_CFGR3_EN_VREFINT_SHIFT) |
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| #define | SYSCFG_CFGR3_SEL_VREF_OUT_PB1 (2 << SYSCFG_CFGR3_EN_VREFINT_SHIFT) |
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| #define | SYSCFG_CFGR3_ENBUF_VREFINT_ADC (1 << 8) |
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| #define | SYSCFG_CFGR3_ENBUF_SENSOR_ADC (1 << 9) |
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| #define | SYSCFG_CFGR3_ENBUF_VREFINT_COMP (1 << 12) |
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| #define | SYSCFG_CFGR3_ENREF_HSI48 (1 << 13) |
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| #define | SYSCFG_CFGR3_REF_HSI48_RDYF (1 << 26) |
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| #define | SYSCFG_CFGR3_SENSOR_ADC_RDYF (1 << 27) |
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| #define | SYSCFG_CFGR3_VREFINT_ADC_RDYF (1 << 28) |
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| #define | SYSCFG_CFGR3_VREFINT_COMP_RDYF (1 << 29) |
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| #define | SYSCFG_CFGR3_VREFINT_RDYF (1 << 30) |
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| #define | SYSCFG_CFGR3_REF_LOCK (1 << 31) |
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| #define | SYSCFG_EXTICR_FIELDSIZE 4 |
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| #define | SYSCFG_EXTICR_GPIOA 0 |
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| #define | SYSCFG_EXTICR_GPIOB 1 |
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| #define | SYSCFG_EXTICR_GPIOC 2 |
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| #define | SYSCFG_EXTICR_GPIOD 3 |
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| #define | SYSCFG_EXTICR_GPIOE 4 |
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| #define | SYSCFG_EXTICR_GPIOH 5 |
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