libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
adc_common_v1.c
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1/** @addtogroup adc_file ADC peripheral API
2@ingroup peripheral_apis
3
4@author @htmlonly © @endhtmlonly
52009 Edward Cheeseman <evbuilder@users.sourceforge.net>
6@author @htmlonly &copy; @endhtmlonly
72012 Ken Sarkies <ksarkies@internode.on.net>
8@author @htmlonly &copy; @endhtmlonly
92014 Karl Palsson <karlp@tweak.net.au>
10
11This library supports one style of the Analog to Digital Conversion System in
12the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics.
13
14The style of ADC Peripheral supported by this code is found in the F1, F2,
15F37x, F38x, F4, and L1 series devices (at the time of writing) but is quite
16different to the style found on the F0 and F30x and F31x.
17Devices can have up to three A/D converters each with their own set of
18registers.
19However all the A/D converters share a common clock. On most devices, this is
20prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum
21of 8, though on the L1 this is always a divider from the HSI. (And therefore HSI
22_must_ be enabled before attempting to enable the ADC)
23
24Each A/D converter has up to ADC_MAX_CHANNELS channels:
25@li On ADC1 the analog channels 16 and 17 are internally connected to the
26temperature sensor and V<sub>REFINT</sub>, respectively.
27@li On ADC2 (if available) the analog channels 16 and 17 are internally
28connected to V<sub>SS</sub>.
29@li On ADC3 (if available) the analog channels 9, 14, 15, 16 and 17 are
30internally connected to V<sub>SS</sub>.
31
32The conversions can occur as a one-off conversion whereby the process stops once
33conversion is complete. The conversions can also be continuous wherein a new
34conversion starts immediately the previous conversion has ended.
35
36Conversion can occur as a single channel conversion or a scan of a group of
37channels in either continuous or one-off mode. If more than one channel is
38converted in a scan group, DMA must be used to transfer the data as there is
39only one result register available. An interrupt can be set to occur at the end
40of conversion, which occurs after all channels have been scanned.
41
42A discontinuous mode allows a subgroup of group of a channels to be converted in
43bursts of a given length.
44
45Injected conversions allow a second group of channels to be converted separately
46from the regular group. An interrupt can be set to occur at the end of
47conversion, which occurs after all channels have been scanned.
48
49@section adc_api_ex Basic ADC Handling API.
50
51Example 1: Simple single channel conversion polled. Enable the peripheral clock
52and ADC, reset ADC and set the prescaler divider. Set dual mode to independent
53(default). Enable triggering for a software trigger.
54
55@code
56 rcc_periph_clock_enable(RCC_ADC1);
57 adc_power_off(ADC1);
58 rcc_periph_reset_pulse(RST_ADC1);
59 rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2);
60 adc_set_dual_mode(ADC_CR1_DUALMOD_IND);
61 adc_disable_scan_mode(ADC1);
62 adc_set_single_conversion_mode(ADC1);
63 adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC);
64 adc_enable_trigger(ADC1, ADC_CR2_EXTSEL_SWSTART);
65 adc_power_on(ADC1);
66 adc_reset_calibration(ADC1);
67 adc_calibration(ADC1);
68 adc_start_conversion_regular(ADC1);
69 while (! adc_eoc(ADC1));
70 reg16 = adc_read_regular(ADC1);
71@endcode
72
73LGPL License Terms @ref lgpl_license
74 */
75
76/*
77 * This file is part of the libopencm3 project.
78 *
79 * Copyright (C) 2014 Karl Palsson <karlp@tweak.net.au>
80 *
81 * This library is free software: you can redistribute it and/or modify
82 * it under the terms of the GNU Lesser General Public License as published by
83 * the Free Software Foundation, either version 3 of the License, or
84 * (at your option) any later version.
85 *
86 * This library is distributed in the hope that it will be useful,
87 * but WITHOUT ANY WARRANTY; without even the implied warranty of
88 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
89 * GNU Lesser General Public License for more details.
90 *
91 * You should have received a copy of the GNU Lesser General Public License
92 * along with this library. If not, see <http://www.gnu.org/licenses/>.
93 */
94
95/**@{*/
96
98
99/*---------------------------------------------------------------------------*/
100/** @brief ADC Off
101
102Turn off the ADC to reduce power consumption to a few microamps.
103
104@param[in] adc Unsigned int32. ADC block register address base @ref
105adc_reg_base.
106*/
107
108void adc_power_off(uint32_t adc)
109{
110 ADC_CR2(adc) &= ~ADC_CR2_ADON;
111}
112
113/*---------------------------------------------------------------------------*/
114/** @brief ADC Enable Analog Watchdog for Regular Conversions
115
116The analog watchdog allows the monitoring of an analog signal between two
117threshold levels. The thresholds must be preset.
118
119@param[in] adc Unsigned int32. ADC block register address base @ref
120adc_reg_base.
121*/
122
124{
125 ADC_CR1(adc) |= ADC_CR1_AWDEN;
126}
127
128/*---------------------------------------------------------------------------*/
129/** @brief ADC Disable Analog Watchdog for Regular Conversions
130
131@param[in] adc Unsigned int32. ADC block register address base @ref
132adc_reg_base.
133*/
134
136{
137 ADC_CR1(adc) &= ~ADC_CR1_AWDEN;
138}
139
140/*---------------------------------------------------------------------------*/
141/** @brief ADC Enable Analog Watchdog for Injected Conversions
142
143The analog watchdog allows the monitoring of an analog signal between two
144threshold levels. The thresholds must be preset. Comparison is done before data
145alignment takes place, so the thresholds are left-aligned.
146
147@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
148*/
149
151{
152 ADC_CR1(adc) |= ADC_CR1_JAWDEN;
153}
154
155/*---------------------------------------------------------------------------*/
156/** @brief ADC Disable Analog Watchdog for Injected Conversions
157
158@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
159*/
160
162{
163 ADC_CR1(adc) &= ~ADC_CR1_JAWDEN;
164}
165
166/*---------------------------------------------------------------------------*/
167/** @brief ADC Enable Discontinuous Mode for Regular Conversions
168
169In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the
170defined regular channel group. The subgroup is defined by the number of
171consecutive channels to be converted. After a subgroup has been converted
172the next trigger will start conversion of the immediately following subgroup
173of the same length or until the whole group has all been converted. When the
174the whole group has been converted, the next trigger will restart conversion
175of the subgroup at the beginning of the whole group.
176
177@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
178@param[in] length Unsigned int8. Number of channels in the group @ref
179adc_cr1_discnum
180*/
181
182void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length)
183{
184 if ((length-1) > 7) {
185 return;
186 }
187 ADC_CR1(adc) |= ADC_CR1_DISCEN;
188 ADC_CR1(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT);
189}
190
191/*---------------------------------------------------------------------------*/
192/** @brief ADC Disable Discontinuous Mode for Regular Conversions
193
194@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
195*/
196
198{
199 ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
200}
201
202/*---------------------------------------------------------------------------*/
203/** @brief ADC Enable Discontinuous Mode for Injected Conversions
204
205In this mode the ADC converts sequentially one channel of the defined group of
206injected channels, cycling back to the first channel in the group once the
207entire group has been converted.
208
209@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
210*/
211
213{
214 ADC_CR1(adc) |= ADC_CR1_JDISCEN;
215}
216
217/*---------------------------------------------------------------------------*/
218/** @brief ADC Disable Discontinuous Mode for Injected Conversions
219
220@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
221*/
222
224{
225 ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
226}
227
228
229/*---------------------------------------------------------------------------*/
230/** @brief ADC Enable Automatic Injected Conversions
231
232The ADC converts a defined injected group of channels immediately after the
233regular channels have been converted. The external trigger on the injected
234channels is disabled as required.
235
236@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
237*/
238
240{
242 ADC_CR1(adc) |= ADC_CR1_JAUTO;
243}
244
245/*---------------------------------------------------------------------------*/
246/** @brief ADC Disable Automatic Injected Conversions
247
248@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
249*/
250
252{
253 ADC_CR1(adc) &= ~ADC_CR1_JAUTO;
254}
255
256/*---------------------------------------------------------------------------*/
257/** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels
258
259The analog watchdog allows the monitoring of an analog signal between two
260threshold levels. The thresholds must be preset. Comparison is done before data
261alignment takes place, so the thresholds are left-aligned.
262
263@note The analog watchdog must be enabled for either or both of the regular or
264injected channels. If neither are enabled, the analog watchdog feature will be
265disabled.
266@ref adc_enable_analog_watchdog_injected, @ref
267adc_enable_analog_watchdog_regular.
268
269@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
270*/
271
273{
274 ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
275}
276
277/*---------------------------------------------------------------------------*/
278/** @brief ADC Enable Analog Watchdog for a Selected Channel
279
280The analog watchdog allows the monitoring of an analog signal between two
281threshold levels. The thresholds must be preset. Comparison is done before data
282alignment takes place, so the thresholds are left-aligned.
283
284@note The analog watchdog must be enabled for either or both of the regular or
285injected channels. If neither are enabled, the analog watchdog feature will be
286disabled. If both are enabled, the same channel number is monitored.
287@ref adc_enable_analog_watchdog_injected, @ref
288adc_enable_analog_watchdog_regular.
289
290@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
291@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel
292*/
293
295 uint8_t channel)
296{
297 uint32_t reg32;
298
299 reg32 = (ADC_CR1(adc) & ~ADC_CR1_AWDCH_MASK); /* Clear bits [4:0]. */
300 if (channel <= ADC_CR1_AWDCH_MAX) {
301 reg32 |= channel;
302 }
303 ADC_CR1(adc) = reg32;
304 ADC_CR1(adc) |= ADC_CR1_AWDSGL;
305}
306
307/*---------------------------------------------------------------------------*/
308/** @brief ADC Set Scan Mode
309
310In this mode a conversion consists of a scan of the predefined set of channels,
311regular and injected, each channel conversion immediately following the
312previous one. It can use single, continuous or discontinuous mode.
313
314@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
315*/
316
317void adc_enable_scan_mode(uint32_t adc)
318{
319 ADC_CR1(adc) |= ADC_CR1_SCAN;
320}
321
322/*---------------------------------------------------------------------------*/
323/** @brief ADC Disable Scan Mode
324
325@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
326*/
327
328void adc_disable_scan_mode(uint32_t adc)
329{
330 ADC_CR1(adc) &= ~ADC_CR1_SCAN;
331}
332
333/*---------------------------------------------------------------------------*/
334/** @brief ADC Enable Injected End-Of-Conversion Interrupt
335
336@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
337*/
338
340{
341 ADC_CR1(adc) |= ADC_CR1_JEOCIE;
342}
343
344/*---------------------------------------------------------------------------*/
345/** @brief ADC Disable Injected End-Of-Conversion Interrupt
346
347@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
348*/
349
351{
352 ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
353}
354
355/*---------------------------------------------------------------------------*/
356/** @brief ADC Enable Analog Watchdog Interrupt
357
358@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
359*/
360
361void adc_enable_awd_interrupt(uint32_t adc)
362{
363 ADC_CR1(adc) |= ADC_CR1_AWDIE;
364}
365
366/*---------------------------------------------------------------------------*/
367/** @brief ADC Disable Analog Watchdog Interrupt
368
369@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
370*/
371
373{
374 ADC_CR1(adc) &= ~ADC_CR1_AWDIE;
375}
376
377
378/*---------------------------------------------------------------------------*/
379/** @brief ADC Enable Regular End-Of-Conversion Interrupt
380
381@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
382*/
383
384void adc_enable_eoc_interrupt(uint32_t adc)
385{
386 ADC_CR1(adc) |= ADC_CR1_EOCIE;
387}
388
389/*---------------------------------------------------------------------------*/
390/** @brief ADC Disable Regular End-Of-Conversion Interrupt
391
392@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
393*/
394
396{
397 ADC_CR1(adc) &= ~ADC_CR1_EOCIE;
398}
399
400
401/*---------------------------------------------------------------------------*/
402/** @brief ADC Set the Data as Left Aligned
403
404@param[in] adc Unsigned int32. ADC block register address base @ref
405adc_reg_base.
406*/
407
408void adc_set_left_aligned(uint32_t adc)
409{
410 ADC_CR2(adc) |= ADC_CR2_ALIGN;
411}
412
413/*---------------------------------------------------------------------------*/
414/** @brief ADC Set the Data as Right Aligned
415
416@param[in] adc Unsigned int32. ADC block register address base @ref
417adc_reg_base.
418*/
419
420void adc_set_right_aligned(uint32_t adc)
421{
422 ADC_CR2(adc) &= ~ADC_CR2_ALIGN;
423}
424
425/*---------------------------------------------------------------------------*/
426/** @brief ADC Read the End-of-Conversion Flag
427
428This flag is set after all channels of a regular or injected group have been
429converted.
430
431@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
432@returns bool. End of conversion flag.
433*/
434
435bool adc_eoc(uint32_t adc)
436{
437 return (ADC_SR(adc) & ADC_SR_EOC) != 0;
438}
439
440/*---------------------------------------------------------------------------*/
441/** @brief ADC Read the End-of-Conversion Flag for Injected Conversion
442
443This flag is set after all channels of an injected group have been converted.
444
445@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
446@returns bool. End of conversion flag.
447*/
448
449bool adc_eoc_injected(uint32_t adc)
450{
451 return (ADC_SR(adc) & ADC_SR_JEOC) != 0;
452}
453
454/*---------------------------------------------------------------------------*/
455/** @brief ADC Read from the Regular Conversion Result Register
456
457The result read back is 12 bits, right or left aligned within the first 16 bits.
458For ADC1 only, the higher 16 bits will hold the result from ADC2 if
459an appropriate dual mode has been set @see adc_set_dual_mode.
460
461@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
462@returns Unsigned int32 conversion result.
463*/
464
465uint32_t adc_read_regular(uint32_t adc)
466{
467 return ADC_DR(adc);
468}
469
470/*---------------------------------------------------------------------------*/
471/** @brief ADC Read from an Injected Conversion Result Register
472
473The result read back from the selected injected result register (one of four)
474is 12 bits, right or left aligned within the first 16 bits. The result can have
475a negative value if the injected channel offset has been set @see
476adc_set_injected_offset.
477
478@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
479@param[in] reg Unsigned int8. Register number (1 ... 4).
480@returns Unsigned int32 conversion result.
481*/
482
483uint32_t adc_read_injected(uint32_t adc, uint8_t reg)
484{
485 switch (reg) {
486 case 1:
487 return ADC_JDR1(adc);
488 case 2:
489 return ADC_JDR2(adc);
490 case 3:
491 return ADC_JDR3(adc);
492 case 4:
493 return ADC_JDR4(adc);
494 }
495 return 0;
496}
497
498/*---------------------------------------------------------------------------*/
499/** @brief ADC Enable Continuous Conversion Mode
500
501In this mode the ADC starts a new conversion of a single channel or a channel
502group immediately following completion of the previous channel group conversion.
503
504@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
505*/
506
508{
509 ADC_CR2(adc) |= ADC_CR2_CONT;
510}
511
512
513/*---------------------------------------------------------------------------*/
514/** @brief ADC Enable Single Conversion Mode
515
516In this mode the ADC performs a conversion of one channel or a channel group
517and stops.
518
519@param[in] adc Unsigned int32. ADC block register address base @ref
520adc_reg_base.
521*/
522
524{
525 ADC_CR2(adc) &= ~ADC_CR2_CONT;
526}
527
528/*---------------------------------------------------------------------------*/
529/** @brief ADC Set Analog Watchdog Upper Threshold
530
531@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
532@param[in] threshold Upper threshold value, 12bit right aligned.
533*/
534
535void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold)
536{
537 uint32_t reg32 = 0;
538
539 reg32 = (uint32_t)threshold;
540 reg32 &= ADC_HT_MSK;
541 ADC_HTR(adc) = reg32;
542}
543
544/*---------------------------------------------------------------------------*/
545/** @brief ADC Set Analog Watchdog Lower Threshold
546
547@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
548@param[in] threshold Lower threshold value, 12bit right aligned.
549*/
550
551void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold)
552{
553 uint32_t reg32 = 0;
554
555 reg32 = (uint32_t)threshold;
556 reg32 &= ADC_LT_MSK;
557 ADC_LTR(adc) = reg32;
558}
559
560/*---------------------------------------------------------------------------*/
561
562/** @brief ADC Set a Regular Channel Conversion Sequence
563
564Define a sequence of channels to be converted as a regular group with a length
565from 1 to ADC_REGULAR_SEQUENCE_MAX channels. If this is called during
566conversion, the current conversion is reset and conversion begins again with
567the newly defined group.
568
569@param[in] adc Unsigned int32. ADC block base address @ref adc_reg_base.
570@param[in] length Unsigned int8. Number of channels in the group.
571@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..31.
572 */
573
574void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
575{
576 uint32_t fifth6 = 0;
577 uint32_t fourth6 = 0;
578 uint32_t third6 = 0;
579 uint32_t second6 = 0;
580 uint32_t first6 = 0;
581 uint8_t i = 0;
582
583 if (length > ADC_SQR_MAX_CHANNELS_REGULAR) {
584 return;
585 }
586
587 for (i = 1; i <= length; i++) {
588 if (i <= 6) {
589 first6 |= (channel[i - 1] << ((i - 1) * 5));
590 }
591 if ((i > 6) && (i <= 12)) {
592 second6 |= (channel[i - 1] << ((i - 6 - 1) * 5));
593 }
594 if ((i > 12) && (i <= 18)) {
595 third6 |= (channel[i - 1] << ((i - 12 - 1) * 5));
596 }
597 if ((i > 18) && (i <= 24)) {
598 fourth6 |= (channel[i - 1] << ((i - 18 - 1) * 5));
599 }
600 if ((i > 24) && (i <= 28)) {
601 fifth6 |= (channel[i - 1] << ((i - 24 - 1) * 5));
602 }
603 }
604#if defined(ADC_SQR5)
605 ADC_SQR1(adc) = fifth6 | ((length - 1) << ADC_SQR1_L_LSB);
606 ADC_SQR2(adc) = fourth6;
607 ADC_SQR3(adc) = third6;
608 ADC_SQR4(adc) = second6;
609 ADC_SQR5(adc) = first6;
610#else
611 ADC_SQR1(adc) = third6 | ((length - 1) << ADC_SQR1_L_LSB);
612 ADC_SQR2(adc) = second6;
613 ADC_SQR3(adc) = first6;
614#endif
615}
616
617
618/*---------------------------------------------------------------------------*/
619/** @brief ADC Set an Injected Channel Conversion Sequence
620
621Defines a sequence of channels to be converted as an injected group with a
622length from 1 to 4 channels. If this is called during conversion, the current
623conversion is reset and conversion begins again with the newly defined group.
624
625@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
626@param[in] length Unsigned int8. Number of channels in the group.
627@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18
628*/
629
630void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
631{
632 uint32_t reg32 = 0;
633 uint8_t i = 0;
634
635 /* Maximum sequence length is 4 channels. Minimum sequence is 1.*/
636 if ((length - 1) > 3) {
637 return;
638 }
639
640 for (i = 0; i < length; i++) {
641 reg32 |= ADC_JSQR_JSQ_VAL(4 - i, channel[length - i - 1]);
642 }
643
644 reg32 |= ADC_JSQR_JL_VAL(length);
645
646 ADC_JSQR(adc) = reg32;
647}
648
649
650/*----------------------------------------------------------------------------*/
651/** @brief ADC Set the Injected Channel Data Offset
652
653This value is subtracted from the injected channel results after conversion is
654complete, and can result in negative results. A separate value can be specified
655for each injected data register.
656
657@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
658@param[in] reg Unsigned int8. Register number (1 ... 4).
659@param[in] offset Unsigned int32.
660*/
661
662void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset)
663{
664 switch (reg) {
665 case 1:
666 ADC_JOFR1(adc) = offset;
667 break;
668 case 2:
669 ADC_JOFR2(adc) = offset;
670 break;
671 case 3:
672 ADC_JOFR3(adc) = offset;
673 break;
674 case 4:
675 ADC_JOFR4(adc) = offset;
676 break;
677 }
678}
679
680/*---------------------------------------------------------------------------*/
681/** @brief ADC Software Triggered Conversion on Regular Channels
682
683This starts conversion on a set of defined regular channels if the ADC trigger
684is set to be a software trigger. It is cleared by hardware once conversion
685starts.
686
687Special F1 Note this is a software trigger and requires triggering to be
688enabled and the trigger source to be set appropriately otherwise conversion
689will not start. This is not the same as the ADC start conversion operation.
690
691@param[in] adc Unsigned int32. ADC block register address base @ref
692adc_reg_base.
693*/
694
696{
697 /* Start conversion on regular channels. */
698 ADC_CR2(adc) |= ADC_CR2_SWSTART;
699
700 /* Wait until the ADC starts the conversion. */
701 while (ADC_CR2(adc) & ADC_CR2_SWSTART);
702}
703
704/*---------------------------------------------------------------------------*/
705/** @brief ADC Software Triggered Conversion on Injected Channels
706
707This starts conversion on a set of defined injected channels if the ADC trigger
708is set to be a software trigger. It is cleared by hardware once conversion
709starts.
710
711Special F1 Note this is a software trigger and requires triggering to be
712enabled and the trigger source to be set appropriately otherwise conversion
713will not start. This is not the same as the ADC start conversion operation.
714
715@param[in] adc Unsigned int32. ADC block register address base @ref
716adc_reg_base.
717*/
718
720{
721 /* Start conversion on injected channels. */
723
724 /* Wait until the ADC starts the conversion. */
725 while (ADC_CR2(adc) & ADC_CR2_JSWSTART);
726}
727
728
729/*---------------------------------------------------------------------------*/
730/** @brief ADC Enable DMA Transfers
731
732@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
733*/
734
735void adc_enable_dma(uint32_t adc)
736{
737 ADC_CR2(adc) |= ADC_CR2_DMA;
738}
739
740/*---------------------------------------------------------------------------*/
741/** @brief ADC Disable DMA Transfers
742
743@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
744*/
745
746void adc_disable_dma(uint32_t adc)
747{
748 ADC_CR2(adc) &= ~ADC_CR2_DMA;
749}
750
751/*---------------------------------------------------------------------------*/
752/** @brief Read a Status Flag.
753
754@param[in] adc Unsigned int32. ADC register address base @ref adc_reg_base
755@param[in] flag Unsigned int32. Status register flag @ref adc_sr_values.
756@returns boolean: flag set.
757*/
758
759bool adc_get_flag(uint32_t adc, uint32_t flag)
760{
761 return ADC_SR(adc) & flag;
762}
763
764/*---------------------------------------------------------------------------*/
765/** @brief Clear a Status Flag.
766
767@param[in] adc Unsigned int32. ADC register address base @ref adc_reg_base
768@param[in] flag Unsigned int32. Status register flag @ref adc_sr_values.
769*/
770
771void adc_clear_flag(uint32_t adc, uint32_t flag)
772{
773 /* All defined bits are 'r' or 'rc_w0' */
774 ADC_SR(adc) = ~flag;
775}
776
777/*---------------------------------------------------------------------------*/
778
779/**@}*/
#define ADC_CR2_DMA
#define ADC_CR1_DISCNUM_SHIFT
#define ADC_JSQR_JL_VAL(val)
#define ADC_JSQR_JSQ_VAL(n, val)
#define ADC_CR1_JAWDEN
#define ADC_CR2_CONT
#define ADC_CR1_JEOCIE
Interrupt enable for injected channels.
#define ADC_CR1_AWDSGL
Enable the watchdog on a single channel in scan mode.
#define ADC_CR2_SWSTART
#define ADC_CR1_JAUTO
Automatic Injection Group conversion.
#define ADC_CR1_AWDEN
#define ADC_CR2(block)
Definition: adc_common_v1.h:58
#define ADC_CR1(block)
Definition: adc_common_v1.h:55
void adc_disable_external_trigger_injected(uint32_t adc)
ADC Disable an External Trigger for Injected Channels.
#define ADC_SQR1_L_LSB
#define ADC_CR1_EOCIE
Interrupt enable EOC.
#define ADC_HT_MSK
#define ADC_SR(block)
Definition: adc_common_v1.h:52
#define ADC_LT_MSK
#define ADC_CR1_SCAN
Scan mode.
#define ADC_CR1_DISCEN
Discontinuous mode on regular channels.
#define ADC_CR2_JSWSTART
#define ADC_CR1_JDISCEN
Discontinuous mode on injected channels.
#define ADC_CR1_AWDIE
Analog watchdog interrupt enable.
#define ADC_CR2_ALIGN
void adc_disable_awd_interrupt(uint32_t adc)
ADC Disable Analog Watchdog Interrupt.
void adc_start_conversion_regular(uint32_t adc)
ADC Software Triggered Conversion on Regular Channels.
void adc_enable_awd_interrupt(uint32_t adc)
ADC Enable Analog Watchdog Interrupt.
bool adc_get_flag(uint32_t adc, uint32_t flag)
Read a Status Flag.
void adc_disable_automatic_injected_group_conversion(uint32_t adc)
ADC Disable Automatic Injected Conversions.
void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold)
ADC Set Analog Watchdog Upper Threshold.
void adc_power_off(uint32_t adc)
ADC Off.
void adc_enable_discontinuous_mode_injected(uint32_t adc)
ADC Enable Discontinuous Mode for Injected Conversions.
void adc_set_continuous_conversion_mode(uint32_t adc)
ADC Enable Continuous Conversion Mode.
void adc_set_single_conversion_mode(uint32_t adc)
ADC Enable Single Conversion Mode.
void adc_disable_discontinuous_mode_regular(uint32_t adc)
ADC Disable Discontinuous Mode for Regular Conversions.
void adc_start_conversion_injected(uint32_t adc)
ADC Software Triggered Conversion on Injected Channels.
uint32_t adc_read_regular(uint32_t adc)
ADC Read from the Regular Conversion Result Register.
void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length)
ADC Enable Discontinuous Mode for Regular Conversions.
void adc_disable_eoc_interrupt_injected(uint32_t adc)
ADC Disable Injected End-Of-Conversion Interrupt.
void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
ADC Set an Injected Channel Conversion Sequence.
void adc_enable_eoc_interrupt(uint32_t adc)
ADC Enable Regular End-Of-Conversion Interrupt.
void adc_disable_eoc_interrupt(uint32_t adc)
ADC Disable Regular End-Of-Conversion Interrupt.
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
ADC Enable Analog Watchdog for All Regular and/or Injected Channels.
void adc_disable_scan_mode(uint32_t adc)
ADC Disable Scan Mode.
void adc_disable_dma(uint32_t adc)
ADC Disable DMA Transfers.
void adc_set_left_aligned(uint32_t adc)
ADC Set the Data as Left Aligned.
void adc_set_right_aligned(uint32_t adc)
ADC Set the Data as Right Aligned.
void adc_clear_flag(uint32_t adc, uint32_t flag)
Clear a Status Flag.
void adc_enable_automatic_injected_group_conversion(uint32_t adc)
ADC Enable Automatic Injected Conversions.
void adc_enable_eoc_interrupt_injected(uint32_t adc)
ADC Enable Injected End-Of-Conversion Interrupt.
void adc_enable_analog_watchdog_injected(uint32_t adc)
ADC Enable Analog Watchdog for Injected Conversions.
uint32_t adc_read_injected(uint32_t adc, uint8_t reg)
ADC Read from an Injected Conversion Result Register.
void adc_enable_dma(uint32_t adc)
ADC Enable DMA Transfers.
void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset)
ADC Set the Injected Channel Data Offset.
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel)
ADC Enable Analog Watchdog for a Selected Channel.
void adc_disable_analog_watchdog_injected(uint32_t adc)
ADC Disable Analog Watchdog for Injected Conversions.
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
ADC Set a Regular Channel Conversion Sequence.
void adc_enable_analog_watchdog_regular(uint32_t adc)
ADC Enable Analog Watchdog for Regular Conversions.
bool adc_eoc_injected(uint32_t adc)
ADC Read the End-of-Conversion Flag for Injected Conversion.
void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold)
ADC Set Analog Watchdog Lower Threshold.
bool adc_eoc(uint32_t adc)
ADC Read the End-of-Conversion Flag.
void adc_enable_scan_mode(uint32_t adc)
ADC Set Scan Mode.
void adc_disable_discontinuous_mode_injected(uint32_t adc)
ADC Disable Discontinuous Mode for Injected Conversions.
void adc_disable_analog_watchdog_regular(uint32_t adc)
ADC Disable Analog Watchdog for Regular Conversions.
#define ADC_SR_EOC
End of conversion.
#define ADC_SR_JEOC
Injected channel end of conversion.
#define ADC_JSQR(block)
Definition: l1/adc.h:76
#define ADC_JDR2(block)
Definition: l1/adc.h:80
#define ADC_SQR4(block)
Definition: l1/adc.h:68
#define ADC_LTR(block)
Definition: l1/adc.h:56
#define ADC_HTR(block)
Definition: l1/adc.h:53
#define ADC_JDR3(block)
Definition: l1/adc.h:81
#define ADC_DR(block)
Definition: l1/adc.h:85
#define ADC_JOFR2(block)
Definition: l1/adc.h:48
#define ADC_JOFR3(block)
Definition: l1/adc.h:49
#define ADC_SQR1(block)
Definition: l1/adc.h:59
#define ADC_SQR3(block)
Definition: l1/adc.h:65
#define ADC_CR1_AWDCH_MAX
Definition: l1/adc.h:121
#define ADC_JOFR1(block)
Definition: l1/adc.h:47
#define ADC_SQR2(block)
Definition: l1/adc.h:62
#define ADC_SQR5(block)
Definition: l1/adc.h:72
#define ADC_JOFR4(block)
Definition: l1/adc.h:50
#define ADC_JDR1(block)
Definition: l1/adc.h:79
#define ADC_SQR_MAX_CHANNELS_REGULAR
Definition: l1/adc.h:174
#define ADC_JDR4(block)
Definition: l1/adc.h:82