Go to the source code of this file.

Macros
#define	RI_BASE ROUTING_BASE - 0x04

#define	RI_ICR MMIO32(RI_BASE + 0x04)

#define	RI_ASCR1 MMIO32(RI_BASE + 0x08)

#define	RI_ASCR2 MMIO32(RI_BASE + 0x0c)

#define	RI_HYSCR1 MMIO32(RI_BASE + 0x10)

#define	RI_HYSCR2 MMIO32(RI_BASE + 0x14)

#define	RI_HYSCR3 MMIO32(RI_BASE + 0x18)

#define	RI_HYSCR4 MMIO32(RI_BASE + 0x1c)

#define	RI_ASMR1 MMIO32(RI_BASE + 0x20)

#define	RI_CMR1 MMIO32(RI_BASE + 0x24)

#define	RI_CICR1 MMIO32(RI_BASE + 0x28)

#define	RI_ASMR2 MMIO32(RI_BASE + 0x2c)

#define	RI_CMR2 MMIO32(RI_BASE + 0x30)

#define	RI_CICR2 MMIO32(RI_BASE + 0x34)

#define	RI_ASMR3 MMIO32(RI_BASE + 0x38)

#define	RI_CMR3 MMIO32(RI_BASE + 0x3c)

#define	RI_CICR3 MMIO32(RI_BASE + 0x40)

#define	RI_ASMR4 MMIO32(RI_BASE + 0x44)

#define	RI_CMR4 MMIO32(RI_BASE + 0x48)

#define	RI_CICR4 MMIO32(RI_BASE + 0x4c)

#define	RI_ASMR5 MMIO32(RI_BASE + 0x50)

#define	RI_CMR5 MMIO32(RI_BASE + 0x54)

#define	RI_CICR5 MMIO32(RI_BASE + 0x58)

#define	RI_ICR_IC1IOS_SHIFT 0
	RI input capture register. More...

#define	RI_ICR_IC1IOS_MASK 0xf

#define	RI_ICR_IC2IOS_SHIFT 4

#define	RI_ICR_IC2IOS_MASK 0xf

#define	RI_ICR_IC3IOS_SHIFT 8

#define	RI_ICR_IC3IOS_MASK 0xf

#define	RI_ICR_IC4IOS_SHIFT 12

#define	RI_ICR_IC4IOS_MASK 0xf

#define	RI_ICR_TIM_SHIFT 16

#define	RI_ICR_TIM_MASK 0x3

#define	RI_ICR_IC1 (1 << 18)

#define	RI_ICR_IC2 (1 << 19)

#define	RI_ICR_IC3 (1 << 20)

#define	RI_ICR_IC4 (1 << 21)

#define	RI_ASCR1_CH0_GR1_1 (1 << 0)
	RI analog switches control register 1. More...

#define	RI_ASCR1_CH1_GR1_2 (1 << 1)

#define	RI_ASCR1_CH2_GR1_3 (1 << 2)

#define	RI_ASCR1_CH3_GR1_4 (1 << 3)

#define	RI_ASCR1_CH4 (1 << 4)

#define	RI_ASCR1_CH5 (1 << 5)

#define	RI_ASCR1_CH6_GR2_1 (1 << 6)

#define	RI_ASCR1_CH7_GR2_2 (1 << 7)

#define	RI_ASCR1_CH8_GR3_1 (1 << 8)

#define	RI_ASCR1_CH9_GR3_2 (1 << 9)

#define	RI_ASCR1_CH10_GR8_1 (1 << 10)

#define	RI_ASCR1_CH11_GR8_2 (1 << 11)

#define	RI_ASCR1_CH12_GR8_3 (1 << 12)

#define	RI_ASCR1_CH13_GR8_4 (1 << 13)

#define	RI_ASCR1_CH14_GR9_1 (1 << 14)

#define	RI_ASCR1_CH15_GR9_2 (1 << 15)

#define	RI_ASCR1_CH31_GR11_5 (1 << 16)

#define	RI_ASCR1_CH18_GR7_1 (1 << 18)

#define	RI_ASCR1_CH19_GR7_2 (1 << 19)

#define	RI_ASCR1_CH20_GR7_3 (1 << 20)

#define	RI_ASCR1_CH21_GR7_4 (1 << 21)

#define	RI_ASCR1_CH22 (1 << 22)

#define	RI_ASCR1_CH23 (1 << 23)

#define	RI_ASCR1_CH24 (1 << 24)

#define	RI_ASCR1_CH25 (1 << 25)

#define	RI_ASCR1_VCOMP (1 << 26)

#define	RI_ASCR1_CH27_GR11_1 (1 << 27)

#define	RI_ASCR1_CH28_GR11_2 (1 << 28)

#define	RI_ASCR1_CH29_GR11_3 (1 << 29)

#define	RI_ASCR1_CH30_GR11_4 (1 << 30)

#define	RI_ASCR1_SCM (1 << 31)

#define	RI_ASCR2_GR10_1 (1 << 0)
	RI analog switches control register 2. More...

#define	RI_ASCR2_GR10_2 (1 << 1)

#define	RI_ASCR2_GR10_3 (1 << 2)

#define	RI_ASCR2_GR10_4 (1 << 3)

#define	RI_ASCR2_GR6_1 (1 << 4)

#define	RI_ASCR2_GR6_2 (1 << 5)

#define	RI_ASCR2_GR5_1 (1 << 6)

#define	RI_ASCR2_GR5_2 (1 << 7)

#define	RI_ASCR2_GR5_3 (1 << 8)

#define	RI_ASCR2_GR4_1 (1 << 9)

#define	RI_ASCR2_GR4_2 (1 << 10)

#define	RI_ASCR2_GR4_3 (1 << 11)

#define	RI_ASCR2_CH0B_GR3_3 (1 << 16)

#define	RI_ASCR2_CH1B_GR3_4 (1 << 17)

#define	RI_ASCR2_CH2B_GR3_5 (1 << 18)

#define	RI_ASCR2_CH3B_GR9_3 (1 << 19)

#define	RI_ASCR2_CH6B_GR9_4 (1 << 20)

#define	RI_ASCR2_CH7B_GR2_3 (1 << 21)

#define	RI_ASCR2_CH8B_GR2_4 (1 << 22)

#define	RI_ASCR2_CH9B_GR2_5 (1 << 23)

#define	RI_ASCR2_CH10B_GR7_5 (1 << 24)

#define	RI_ASCR2_CH11B_GR7_6 (1 << 25)

#define	RI_ASCR2_CH12B_GR7_7 (1 << 26)

#define	RI_ASCR2_GR6_3 (1 << 27)

#define	RI_ASCR2_GR6_4 (1 << 28)

#define	RI_HYSCR1_PA(x) (x)
	RI hysteresis control register 1. More...

#define	RI_HYSCR1_PB(x) (x << 16)

#define	RI_HYSCR2_PC(x) (x)
	RI hysteresis control register 2. More...

#define	RI_HYSCR2_PD(x) (x << 16)

#define	RI_HYSCR3_PE(x) (x)
	RI hysteresis control register 3. More...

#define	RI_HYSCR3_PF(x) (x << 16)

#define	RI_HYSCR2_PG(x) (x)
	RI hysteresis control register 4. More...

#define	RI_ASMR1_PA(x) (x)
	Analog switch mode register (RI_ASMR1) More...

#define	RI_CMR1_PA(x) (x)
	Channel mask register (RI_CMR1) More...

#define	RI_CICR1_PA(x) (x)
	Channel identification for capture register (RI_CICR1) More...

#define	RI_ASMR2_PB(x) (x)
	Analog switch mode register (RI_ASMR2) More...

#define	RI_CMR2_PB(x) (x)
	Channel mask register (RI_CMR2) More...

#define	RI_CICR2_PB(x) (x)
	Channel identification for capture register (RI_CICR2) More...

#define	RI_ASMR3_PC(x) (x)
	Analog switch mode register (RI_ASMR3) More...

#define	RI_CMR3_PC(x) (x)
	Channel mask register (RI_CMR3) More...

#define	RI_CICR3_PC(x) (x)
	Channel identification for capture register (RI_CICR3) More...

#define	RI_ASMR4_PF(x) (x)
	Analog switch mode register (RI_ASMR4) More...

#define	RI_CMR4_PF(x) (x)
	Channel mask register (RI_CMRF) More...

#define	RI_CICR4_PF(x) (x)
	Channel identification for capture register (RI_CICR4) More...

#define	RI_ASMR5_PG(x) (x)
	Analog switch mode register (RI_ASMR5) More...

#define	RI_CMR5_PG(x) (x)
	Channel mask register (RI_CMR5) More...

#define	RI_CICR5_PG(x) (x)
	Channel identification for capture register (RI_CICR5) More...

Macros