libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
Routing Interface registers

Register definitions for the STM32L1xx Routing Interface More...

Collaboration diagram for Routing Interface registers:

Macros

#define RI_BASE   ROUTING_BASE - 0x04
 
#define RI_ICR   MMIO32(RI_BASE + 0x04)
 
#define RI_ASCR1   MMIO32(RI_BASE + 0x08)
 
#define RI_ASCR2   MMIO32(RI_BASE + 0x0c)
 
#define RI_HYSCR1   MMIO32(RI_BASE + 0x10)
 
#define RI_HYSCR2   MMIO32(RI_BASE + 0x14)
 
#define RI_HYSCR3   MMIO32(RI_BASE + 0x18)
 
#define RI_HYSCR4   MMIO32(RI_BASE + 0x1c)
 
#define RI_ASMR1   MMIO32(RI_BASE + 0x20)
 
#define RI_CMR1   MMIO32(RI_BASE + 0x24)
 
#define RI_CICR1   MMIO32(RI_BASE + 0x28)
 
#define RI_ASMR2   MMIO32(RI_BASE + 0x2c)
 
#define RI_CMR2   MMIO32(RI_BASE + 0x30)
 
#define RI_CICR2   MMIO32(RI_BASE + 0x34)
 
#define RI_ASMR3   MMIO32(RI_BASE + 0x38)
 
#define RI_CMR3   MMIO32(RI_BASE + 0x3c)
 
#define RI_CICR3   MMIO32(RI_BASE + 0x40)
 
#define RI_ASMR4   MMIO32(RI_BASE + 0x44)
 
#define RI_CMR4   MMIO32(RI_BASE + 0x48)
 
#define RI_CICR4   MMIO32(RI_BASE + 0x4c)
 
#define RI_ASMR5   MMIO32(RI_BASE + 0x50)
 
#define RI_CMR5   MMIO32(RI_BASE + 0x54)
 
#define RI_CICR5   MMIO32(RI_BASE + 0x58)
 
#define RI_ICR_IC1IOS_SHIFT   0
 RI input capture register. More...
 
#define RI_ICR_IC1IOS_MASK   0xf
 
#define RI_ICR_IC2IOS_SHIFT   4
 
#define RI_ICR_IC2IOS_MASK   0xf
 
#define RI_ICR_IC3IOS_SHIFT   8
 
#define RI_ICR_IC3IOS_MASK   0xf
 
#define RI_ICR_IC4IOS_SHIFT   12
 
#define RI_ICR_IC4IOS_MASK   0xf
 
#define RI_ICR_TIM_SHIFT   16
 
#define RI_ICR_TIM_MASK   0x3
 
#define RI_ICR_IC1   (1 << 18)
 
#define RI_ICR_IC2   (1 << 19)
 
#define RI_ICR_IC3   (1 << 20)
 
#define RI_ICR_IC4   (1 << 21)
 
#define RI_ASCR1_CH0_GR1_1   (1 << 0)
 RI analog switches control register 1. More...
 
#define RI_ASCR1_CH1_GR1_2   (1 << 1)
 
#define RI_ASCR1_CH2_GR1_3   (1 << 2)
 
#define RI_ASCR1_CH3_GR1_4   (1 << 3)
 
#define RI_ASCR1_CH4   (1 << 4)
 
#define RI_ASCR1_CH5   (1 << 5)
 
#define RI_ASCR1_CH6_GR2_1   (1 << 6)
 
#define RI_ASCR1_CH7_GR2_2   (1 << 7)
 
#define RI_ASCR1_CH8_GR3_1   (1 << 8)
 
#define RI_ASCR1_CH9_GR3_2   (1 << 9)
 
#define RI_ASCR1_CH10_GR8_1   (1 << 10)
 
#define RI_ASCR1_CH11_GR8_2   (1 << 11)
 
#define RI_ASCR1_CH12_GR8_3   (1 << 12)
 
#define RI_ASCR1_CH13_GR8_4   (1 << 13)
 
#define RI_ASCR1_CH14_GR9_1   (1 << 14)
 
#define RI_ASCR1_CH15_GR9_2   (1 << 15)
 
#define RI_ASCR1_CH31_GR11_5   (1 << 16)
 
#define RI_ASCR1_CH18_GR7_1   (1 << 18)
 
#define RI_ASCR1_CH19_GR7_2   (1 << 19)
 
#define RI_ASCR1_CH20_GR7_3   (1 << 20)
 
#define RI_ASCR1_CH21_GR7_4   (1 << 21)
 
#define RI_ASCR1_CH22   (1 << 22)
 
#define RI_ASCR1_CH23   (1 << 23)
 
#define RI_ASCR1_CH24   (1 << 24)
 
#define RI_ASCR1_CH25   (1 << 25)
 
#define RI_ASCR1_VCOMP   (1 << 26)
 
#define RI_ASCR1_CH27_GR11_1   (1 << 27)
 
#define RI_ASCR1_CH28_GR11_2   (1 << 28)
 
#define RI_ASCR1_CH29_GR11_3   (1 << 29)
 
#define RI_ASCR1_CH30_GR11_4   (1 << 30)
 
#define RI_ASCR1_SCM   (1 << 31)
 
#define RI_ASCR2_GR10_1   (1 << 0)
 RI analog switches control register 2. More...
 
#define RI_ASCR2_GR10_2   (1 << 1)
 
#define RI_ASCR2_GR10_3   (1 << 2)
 
#define RI_ASCR2_GR10_4   (1 << 3)
 
#define RI_ASCR2_GR6_1   (1 << 4)
 
#define RI_ASCR2_GR6_2   (1 << 5)
 
#define RI_ASCR2_GR5_1   (1 << 6)
 
#define RI_ASCR2_GR5_2   (1 << 7)
 
#define RI_ASCR2_GR5_3   (1 << 8)
 
#define RI_ASCR2_GR4_1   (1 << 9)
 
#define RI_ASCR2_GR4_2   (1 << 10)
 
#define RI_ASCR2_GR4_3   (1 << 11)
 
#define RI_ASCR2_CH0B_GR3_3   (1 << 16)
 
#define RI_ASCR2_CH1B_GR3_4   (1 << 17)
 
#define RI_ASCR2_CH2B_GR3_5   (1 << 18)
 
#define RI_ASCR2_CH3B_GR9_3   (1 << 19)
 
#define RI_ASCR2_CH6B_GR9_4   (1 << 20)
 
#define RI_ASCR2_CH7B_GR2_3   (1 << 21)
 
#define RI_ASCR2_CH8B_GR2_4   (1 << 22)
 
#define RI_ASCR2_CH9B_GR2_5   (1 << 23)
 
#define RI_ASCR2_CH10B_GR7_5   (1 << 24)
 
#define RI_ASCR2_CH11B_GR7_6   (1 << 25)
 
#define RI_ASCR2_CH12B_GR7_7   (1 << 26)
 
#define RI_ASCR2_GR6_3   (1 << 27)
 
#define RI_ASCR2_GR6_4   (1 << 28)
 
#define RI_HYSCR1_PA(x)   (x)
 RI hysteresis control register 1. More...
 
#define RI_HYSCR1_PB(x)   (x << 16)
 
#define RI_HYSCR2_PC(x)   (x)
 RI hysteresis control register 2. More...
 
#define RI_HYSCR2_PD(x)   (x << 16)
 
#define RI_HYSCR3_PE(x)   (x)
 RI hysteresis control register 3. More...
 
#define RI_HYSCR3_PF(x)   (x << 16)
 
#define RI_HYSCR2_PG(x)   (x)
 RI hysteresis control register 4. More...
 
#define RI_ASMR1_PA(x)   (x)
 Analog switch mode register (RI_ASMR1) More...
 
#define RI_CMR1_PA(x)   (x)
 Channel mask register (RI_CMR1) More...
 
#define RI_CICR1_PA(x)   (x)
 Channel identification for capture register (RI_CICR1) More...
 
#define RI_ASMR2_PB(x)   (x)
 Analog switch mode register (RI_ASMR2) More...
 
#define RI_CMR2_PB(x)   (x)
 Channel mask register (RI_CMR2) More...
 
#define RI_CICR2_PB(x)   (x)
 Channel identification for capture register (RI_CICR2) More...
 
#define RI_ASMR3_PC(x)   (x)
 Analog switch mode register (RI_ASMR3) More...
 
#define RI_CMR3_PC(x)   (x)
 Channel mask register (RI_CMR3) More...
 
#define RI_CICR3_PC(x)   (x)
 Channel identification for capture register (RI_CICR3) More...
 
#define RI_ASMR4_PF(x)   (x)
 Analog switch mode register (RI_ASMR4) More...
 
#define RI_CMR4_PF(x)   (x)
 Channel mask register (RI_CMRF) More...
 
#define RI_CICR4_PF(x)   (x)
 Channel identification for capture register (RI_CICR4) More...
 
#define RI_ASMR5_PG(x)   (x)
 Analog switch mode register (RI_ASMR5) More...
 
#define RI_CMR5_PG(x)   (x)
 Channel mask register (RI_CMR5) More...
 
#define RI_CICR5_PG(x)   (x)
 Channel identification for capture register (RI_CICR5) More...
 

Detailed Description

Register definitions for the STM32L1xx Routing Interface

Version
1.0.0

LGPL License Terms libopencm3 License

Macro Definition Documentation

◆ RI_ASCR1

#define RI_ASCR1   MMIO32(RI_BASE + 0x08)

Definition at line 43 of file ri.h.

◆ RI_ASCR1_CH0_GR1_1

#define RI_ASCR1_CH0_GR1_1   (1 << 0)

RI analog switches control register 1.

The RI_ASCR1 register is used to configure the analog switches of the I/Os linked to the ADC. These I/Os are pointed to by the ADC channel number.

Definition at line 93 of file ri.h.

◆ RI_ASCR1_CH10_GR8_1

#define RI_ASCR1_CH10_GR8_1   (1 << 10)

Definition at line 103 of file ri.h.

◆ RI_ASCR1_CH11_GR8_2

#define RI_ASCR1_CH11_GR8_2   (1 << 11)

Definition at line 104 of file ri.h.

◆ RI_ASCR1_CH12_GR8_3

#define RI_ASCR1_CH12_GR8_3   (1 << 12)

Definition at line 105 of file ri.h.

◆ RI_ASCR1_CH13_GR8_4

#define RI_ASCR1_CH13_GR8_4   (1 << 13)

Definition at line 106 of file ri.h.

◆ RI_ASCR1_CH14_GR9_1

#define RI_ASCR1_CH14_GR9_1   (1 << 14)

Definition at line 107 of file ri.h.

◆ RI_ASCR1_CH15_GR9_2

#define RI_ASCR1_CH15_GR9_2   (1 << 15)

Definition at line 108 of file ri.h.

◆ RI_ASCR1_CH18_GR7_1

#define RI_ASCR1_CH18_GR7_1   (1 << 18)

Definition at line 111 of file ri.h.

◆ RI_ASCR1_CH19_GR7_2

#define RI_ASCR1_CH19_GR7_2   (1 << 19)

Definition at line 112 of file ri.h.

◆ RI_ASCR1_CH1_GR1_2

#define RI_ASCR1_CH1_GR1_2   (1 << 1)

Definition at line 94 of file ri.h.

◆ RI_ASCR1_CH20_GR7_3

#define RI_ASCR1_CH20_GR7_3   (1 << 20)

Definition at line 113 of file ri.h.

◆ RI_ASCR1_CH21_GR7_4

#define RI_ASCR1_CH21_GR7_4   (1 << 21)

Definition at line 114 of file ri.h.

◆ RI_ASCR1_CH22

#define RI_ASCR1_CH22   (1 << 22)

Definition at line 115 of file ri.h.

◆ RI_ASCR1_CH23

#define RI_ASCR1_CH23   (1 << 23)

Definition at line 116 of file ri.h.

◆ RI_ASCR1_CH24

#define RI_ASCR1_CH24   (1 << 24)

Definition at line 117 of file ri.h.

◆ RI_ASCR1_CH25

#define RI_ASCR1_CH25   (1 << 25)

Definition at line 118 of file ri.h.

◆ RI_ASCR1_CH27_GR11_1

#define RI_ASCR1_CH27_GR11_1   (1 << 27)

Definition at line 120 of file ri.h.

◆ RI_ASCR1_CH28_GR11_2

#define RI_ASCR1_CH28_GR11_2   (1 << 28)

Definition at line 121 of file ri.h.

◆ RI_ASCR1_CH29_GR11_3

#define RI_ASCR1_CH29_GR11_3   (1 << 29)

Definition at line 122 of file ri.h.

◆ RI_ASCR1_CH2_GR1_3

#define RI_ASCR1_CH2_GR1_3   (1 << 2)

Definition at line 95 of file ri.h.

◆ RI_ASCR1_CH30_GR11_4

#define RI_ASCR1_CH30_GR11_4   (1 << 30)

Definition at line 123 of file ri.h.

◆ RI_ASCR1_CH31_GR11_5

#define RI_ASCR1_CH31_GR11_5   (1 << 16)

Definition at line 109 of file ri.h.

◆ RI_ASCR1_CH3_GR1_4

#define RI_ASCR1_CH3_GR1_4   (1 << 3)

Definition at line 96 of file ri.h.

◆ RI_ASCR1_CH4

#define RI_ASCR1_CH4   (1 << 4)

Definition at line 97 of file ri.h.

◆ RI_ASCR1_CH5

#define RI_ASCR1_CH5   (1 << 5)

Definition at line 98 of file ri.h.

◆ RI_ASCR1_CH6_GR2_1

#define RI_ASCR1_CH6_GR2_1   (1 << 6)

Definition at line 99 of file ri.h.

◆ RI_ASCR1_CH7_GR2_2

#define RI_ASCR1_CH7_GR2_2   (1 << 7)

Definition at line 100 of file ri.h.

◆ RI_ASCR1_CH8_GR3_1

#define RI_ASCR1_CH8_GR3_1   (1 << 8)

Definition at line 101 of file ri.h.

◆ RI_ASCR1_CH9_GR3_2

#define RI_ASCR1_CH9_GR3_2   (1 << 9)

Definition at line 102 of file ri.h.

◆ RI_ASCR1_SCM

#define RI_ASCR1_SCM   (1 << 31)

Definition at line 124 of file ri.h.

◆ RI_ASCR1_VCOMP

#define RI_ASCR1_VCOMP   (1 << 26)

Definition at line 119 of file ri.h.

◆ RI_ASCR2

#define RI_ASCR2   MMIO32(RI_BASE + 0x0c)

Definition at line 44 of file ri.h.

◆ RI_ASCR2_CH0B_GR3_3

#define RI_ASCR2_CH0B_GR3_3   (1 << 16)

Definition at line 146 of file ri.h.

◆ RI_ASCR2_CH10B_GR7_5

#define RI_ASCR2_CH10B_GR7_5   (1 << 24)

Definition at line 154 of file ri.h.

◆ RI_ASCR2_CH11B_GR7_6

#define RI_ASCR2_CH11B_GR7_6   (1 << 25)

Definition at line 155 of file ri.h.

◆ RI_ASCR2_CH12B_GR7_7

#define RI_ASCR2_CH12B_GR7_7   (1 << 26)

Definition at line 156 of file ri.h.

◆ RI_ASCR2_CH1B_GR3_4

#define RI_ASCR2_CH1B_GR3_4   (1 << 17)

Definition at line 147 of file ri.h.

◆ RI_ASCR2_CH2B_GR3_5

#define RI_ASCR2_CH2B_GR3_5   (1 << 18)

Definition at line 148 of file ri.h.

◆ RI_ASCR2_CH3B_GR9_3

#define RI_ASCR2_CH3B_GR9_3   (1 << 19)

Definition at line 149 of file ri.h.

◆ RI_ASCR2_CH6B_GR9_4

#define RI_ASCR2_CH6B_GR9_4   (1 << 20)

Definition at line 150 of file ri.h.

◆ RI_ASCR2_CH7B_GR2_3

#define RI_ASCR2_CH7B_GR2_3   (1 << 21)

Definition at line 151 of file ri.h.

◆ RI_ASCR2_CH8B_GR2_4

#define RI_ASCR2_CH8B_GR2_4   (1 << 22)

Definition at line 152 of file ri.h.

◆ RI_ASCR2_CH9B_GR2_5

#define RI_ASCR2_CH9B_GR2_5   (1 << 23)

Definition at line 153 of file ri.h.

◆ RI_ASCR2_GR10_1

#define RI_ASCR2_GR10_1   (1 << 0)

RI analog switches control register 2.

The RI_ASCR2 register is used to configure the analog switches of groups of I/Os not linked to the ADC. In this way, predefined groups of I/Os can be connected together.

Definition at line 133 of file ri.h.

◆ RI_ASCR2_GR10_2

#define RI_ASCR2_GR10_2   (1 << 1)

Definition at line 134 of file ri.h.

◆ RI_ASCR2_GR10_3

#define RI_ASCR2_GR10_3   (1 << 2)

Definition at line 135 of file ri.h.

◆ RI_ASCR2_GR10_4

#define RI_ASCR2_GR10_4   (1 << 3)

Definition at line 136 of file ri.h.

◆ RI_ASCR2_GR4_1

#define RI_ASCR2_GR4_1   (1 << 9)

Definition at line 142 of file ri.h.

◆ RI_ASCR2_GR4_2

#define RI_ASCR2_GR4_2   (1 << 10)

Definition at line 143 of file ri.h.

◆ RI_ASCR2_GR4_3

#define RI_ASCR2_GR4_3   (1 << 11)

Definition at line 144 of file ri.h.

◆ RI_ASCR2_GR5_1

#define RI_ASCR2_GR5_1   (1 << 6)

Definition at line 139 of file ri.h.

◆ RI_ASCR2_GR5_2

#define RI_ASCR2_GR5_2   (1 << 7)

Definition at line 140 of file ri.h.

◆ RI_ASCR2_GR5_3

#define RI_ASCR2_GR5_3   (1 << 8)

Definition at line 141 of file ri.h.

◆ RI_ASCR2_GR6_1

#define RI_ASCR2_GR6_1   (1 << 4)

Definition at line 137 of file ri.h.

◆ RI_ASCR2_GR6_2

#define RI_ASCR2_GR6_2   (1 << 5)

Definition at line 138 of file ri.h.

◆ RI_ASCR2_GR6_3

#define RI_ASCR2_GR6_3   (1 << 27)

Definition at line 157 of file ri.h.

◆ RI_ASCR2_GR6_4

#define RI_ASCR2_GR6_4   (1 << 28)

Definition at line 158 of file ri.h.

◆ RI_ASMR1

#define RI_ASMR1   MMIO32(RI_BASE + 0x20)

Definition at line 49 of file ri.h.

◆ RI_ASMR1_PA

#define RI_ASMR1_PA (   x)    (x)

Analog switch mode register (RI_ASMR1)

The RI_ASMR1 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to select if analog switches of port A are to be controlled by the timer OC or through the ADC interface or RI_ASCRx registers.

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 214 of file ri.h.

◆ RI_ASMR2

#define RI_ASMR2   MMIO32(RI_BASE + 0x2c)

Definition at line 52 of file ri.h.

◆ RI_ASMR2_PB

#define RI_ASMR2_PB (   x)    (x)

Analog switch mode register (RI_ASMR2)

The RI_ASMR2 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to select if analog switches of port B are to be controlled by the timer OC or through the ADC interface or RI_ASCRx registers.

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 250 of file ri.h.

◆ RI_ASMR3

#define RI_ASMR3   MMIO32(RI_BASE + 0x38)

Definition at line 55 of file ri.h.

◆ RI_ASMR3_PC

#define RI_ASMR3_PC (   x)    (x)

Analog switch mode register (RI_ASMR3)

The RI_ASMR3 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to select if analog switches of port C are to be controlled by the timer OC or through the ADC interface or RI_ASCRx registers.

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 286 of file ri.h.

◆ RI_ASMR4

#define RI_ASMR4   MMIO32(RI_BASE + 0x44)

Definition at line 58 of file ri.h.

◆ RI_ASMR4_PF

#define RI_ASMR4_PF (   x)    (x)

Analog switch mode register (RI_ASMR4)

The RI_ASMR4 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to select if analog switches of port F are to be controlled by the timer OC or through the ADC interface or RI_ASCRx registers.

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 322 of file ri.h.

◆ RI_ASMR5

#define RI_ASMR5   MMIO32(RI_BASE + 0x50)

Definition at line 61 of file ri.h.

◆ RI_ASMR5_PG

#define RI_ASMR5_PG (   x)    (x)

Analog switch mode register (RI_ASMR5)

The RI_ASMR5 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to select if analog switches of port G are to be controlled by the timer OC or through the ADC interface or RI_ASCRx registers.

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 358 of file ri.h.

◆ RI_BASE

#define RI_BASE   ROUTING_BASE - 0x04

Definition at line 40 of file ri.h.

◆ RI_CICR1

#define RI_CICR1   MMIO32(RI_BASE + 0x28)

Definition at line 51 of file ri.h.

◆ RI_CICR1_PA

#define RI_CICR1_PA (   x)    (x)

Channel identification for capture register (RI_CICR1)

The RI_CICR1 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used when analog switches are controlled by a timer OC. RI_CICR1 allows a channel to be identified for timer input capture.

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 238 of file ri.h.

◆ RI_CICR2

#define RI_CICR2   MMIO32(RI_BASE + 0x34)

Definition at line 54 of file ri.h.

◆ RI_CICR2_PB

#define RI_CICR2_PB (   x)    (x)

Channel identification for capture register (RI_CICR2)

The RI_CICR2 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used when analog switches are controlled by a timer OC. RI_CICR2 allows a channel to be identified for timer input capture.

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 274 of file ri.h.

◆ RI_CICR3

#define RI_CICR3   MMIO32(RI_BASE + 0x40)

Definition at line 57 of file ri.h.

◆ RI_CICR3_PC

#define RI_CICR3_PC (   x)    (x)

Channel identification for capture register (RI_CICR3)

The RI_CICR3 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used when analog switches are controlled by a timer OC. RI_CICR3 allows a channel to be identified for timer input capture.

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 310 of file ri.h.

◆ RI_CICR4

#define RI_CICR4   MMIO32(RI_BASE + 0x4c)

Definition at line 60 of file ri.h.

◆ RI_CICR4_PF

#define RI_CICR4_PF (   x)    (x)

Channel identification for capture register (RI_CICR4)

The RI_CICR4 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used when analog switches are controlled by a timer OC. RI_CICR4 allows a channel to be identified for timer input capture.

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 346 of file ri.h.

◆ RI_CICR5

#define RI_CICR5   MMIO32(RI_BASE + 0x58)

Definition at line 63 of file ri.h.

◆ RI_CICR5_PG

#define RI_CICR5_PG (   x)    (x)

Channel identification for capture register (RI_CICR5)

The RI_CICR5 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used when analog switches are controlled by a timer OC. RI_CICR5 allows a channel to be identified for timer input capture.

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 382 of file ri.h.

◆ RI_CMR1

#define RI_CMR1   MMIO32(RI_BASE + 0x24)

Definition at line 50 of file ri.h.

◆ RI_CMR1_PA

#define RI_CMR1_PA (   x)    (x)

Channel mask register (RI_CMR1)

RI_CMR1 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to mask a port A channel designated as a timer input capture (after acquisition completion to avoid triggering multiple detections).

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 226 of file ri.h.

◆ RI_CMR2

#define RI_CMR2   MMIO32(RI_BASE + 0x30)

Definition at line 53 of file ri.h.

◆ RI_CMR2_PB

#define RI_CMR2_PB (   x)    (x)

Channel mask register (RI_CMR2)

RI_CMR2 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to mask a port B channel designated as a timer input capture (after acquisition completion to avoid triggering multiple detections).

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 262 of file ri.h.

◆ RI_CMR3

#define RI_CMR3   MMIO32(RI_BASE + 0x3c)

Definition at line 56 of file ri.h.

◆ RI_CMR3_PC

#define RI_CMR3_PC (   x)    (x)

Channel mask register (RI_CMR3)

RI_CMR3 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to mask a port C channel designated as a timer input capture (after acquisition completion to avoid triggering multiple detections).

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 298 of file ri.h.

◆ RI_CMR4

#define RI_CMR4   MMIO32(RI_BASE + 0x48)

Definition at line 59 of file ri.h.

◆ RI_CMR4_PF

#define RI_CMR4_PF (   x)    (x)

Channel mask register (RI_CMRF)

RI_CMR4 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to mask a port F channel designated as a timer input capture (after acquisition completion to avoid triggering multiple detections).

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 334 of file ri.h.

◆ RI_CMR5

#define RI_CMR5   MMIO32(RI_BASE + 0x54)

Definition at line 62 of file ri.h.

◆ RI_CMR5_PG

#define RI_CMR5_PG (   x)    (x)

Channel mask register (RI_CMR5)

RI_CMR1 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to mask a port G channel designated as a timer input capture (after acquisition completion to avoid triggering multiple detections).

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 370 of file ri.h.

◆ RI_HYSCR1

#define RI_HYSCR1   MMIO32(RI_BASE + 0x10)

Definition at line 45 of file ri.h.

◆ RI_HYSCR1_PA

#define RI_HYSCR1_PA (   x)    (x)

RI hysteresis control register 1.

The RI_HYSCR1 register is used to enable/disable the hysteresis of the input Schmitt trigger of ports A and B.

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 169 of file ri.h.

◆ RI_HYSCR1_PB

#define RI_HYSCR1_PB (   x)    (x << 16)

Definition at line 170 of file ri.h.

◆ RI_HYSCR2

#define RI_HYSCR2   MMIO32(RI_BASE + 0x14)

Definition at line 46 of file ri.h.

◆ RI_HYSCR2_PC

#define RI_HYSCR2_PC (   x)    (x)

RI hysteresis control register 2.

RI_HYSCR2 register allows to enable/disable hysteresis of input Schmitt trigger of ports C and D.

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 180 of file ri.h.

◆ RI_HYSCR2_PD

#define RI_HYSCR2_PD (   x)    (x << 16)

Definition at line 181 of file ri.h.

◆ RI_HYSCR2_PG

#define RI_HYSCR2_PG (   x)    (x)

RI hysteresis control register 4.

The RI_HYSCR4 register is used to enable/disable the hysteresis of the input Schmitt trigger of the entire port G.

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 202 of file ri.h.

◆ RI_HYSCR3

#define RI_HYSCR3   MMIO32(RI_BASE + 0x18)

Definition at line 47 of file ri.h.

◆ RI_HYSCR3_PE

#define RI_HYSCR3_PE (   x)    (x)

RI hysteresis control register 3.

The RI_HYSCR3 register is used to enable/disable the hysteresis of the input Schmitt trigger of the entire port E and F.

GPIO0-GPIO15 defines should be used as parameters.

Definition at line 191 of file ri.h.

◆ RI_HYSCR3_PF

#define RI_HYSCR3_PF (   x)    (x << 16)

Definition at line 192 of file ri.h.

◆ RI_HYSCR4

#define RI_HYSCR4   MMIO32(RI_BASE + 0x1c)

Definition at line 48 of file ri.h.

◆ RI_ICR

#define RI_ICR   MMIO32(RI_BASE + 0x04)

Definition at line 42 of file ri.h.

◆ RI_ICR_IC1

#define RI_ICR_IC1   (1 << 18)

Definition at line 81 of file ri.h.

◆ RI_ICR_IC1IOS_MASK

#define RI_ICR_IC1IOS_MASK   0xf

Definition at line 72 of file ri.h.

◆ RI_ICR_IC1IOS_SHIFT

#define RI_ICR_IC1IOS_SHIFT   0

RI input capture register.

The RI_ICR register is used to select the routing of 4 full ports to the input captures of TIM2, TIM3 and TIM4.

Definition at line 71 of file ri.h.

◆ RI_ICR_IC2

#define RI_ICR_IC2   (1 << 19)

Definition at line 82 of file ri.h.

◆ RI_ICR_IC2IOS_MASK

#define RI_ICR_IC2IOS_MASK   0xf

Definition at line 74 of file ri.h.

◆ RI_ICR_IC2IOS_SHIFT

#define RI_ICR_IC2IOS_SHIFT   4

Definition at line 73 of file ri.h.

◆ RI_ICR_IC3

#define RI_ICR_IC3   (1 << 20)

Definition at line 83 of file ri.h.

◆ RI_ICR_IC3IOS_MASK

#define RI_ICR_IC3IOS_MASK   0xf

Definition at line 76 of file ri.h.

◆ RI_ICR_IC3IOS_SHIFT

#define RI_ICR_IC3IOS_SHIFT   8

Definition at line 75 of file ri.h.

◆ RI_ICR_IC4

#define RI_ICR_IC4   (1 << 21)

Definition at line 84 of file ri.h.

◆ RI_ICR_IC4IOS_MASK

#define RI_ICR_IC4IOS_MASK   0xf

Definition at line 78 of file ri.h.

◆ RI_ICR_IC4IOS_SHIFT

#define RI_ICR_IC4IOS_SHIFT   12

Definition at line 77 of file ri.h.

◆ RI_ICR_TIM_MASK

#define RI_ICR_TIM_MASK   0x3

Definition at line 80 of file ri.h.

◆ RI_ICR_TIM_SHIFT

#define RI_ICR_TIM_SHIFT   16

Definition at line 79 of file ri.h.