51#define CAN_MSR_INAK_TIMEOUT 0x0000FFFF
65 if (canport ==
CAN1) {
68#if defined(BX_CAN2_BASE)
92int can_init(uint32_t canport,
bool ttcm,
bool abom,
bool awum,
bool nart,
93 bool rflm,
bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2,
94 uint32_t brp,
bool loopback,
bool silent)
96 volatile uint32_t wait_ack;
100 CAN_MCR(canport) &= ~CAN_MCR_SLEEP;
107 while ((--wait_ack) &&
122 CAN_MCR(canport) &= ~CAN_MCR_TTCM;
128 CAN_MCR(canport) &= ~CAN_MCR_ABOM;
134 CAN_MCR(canport) &= ~CAN_MCR_AWUM;
140 CAN_MCR(canport) &= ~CAN_MCR_NART;
146 CAN_MCR(canport) &= ~CAN_MCR_RFLM;
152 CAN_MCR(canport) &= ~CAN_MCR_TXFP;
158 CAN_BTR(canport) &= ~CAN_BTR_SILM;
164 CAN_BTR(canport) &= ~CAN_BTR_LBKM;
168 CAN_BTR(canport) |= sjw | ts2 | ts1 |
172 CAN_MCR(canport) &= ~CAN_MCR_INRQ;
176 while ((--wait_ack) &&
200 bool id_list_mode, uint32_t fr1, uint32_t fr2,
201 uint32_t fifo,
bool enable)
203 uint32_t filter_select_bit = 0x00000001 << nr;
260 uint16_t mask1, uint16_t id2,
261 uint16_t mask2, uint32_t fifo,
bool enable)
264 ((uint32_t)mask1 << 16) | (uint32_t)id1,
265 ((uint32_t)mask2 << 16) | (uint32_t)id2, fifo, enable);
278 uint32_t mask, uint32_t fifo,
bool enable)
295 uint16_t id1, uint16_t id2,
296 uint16_t id3, uint16_t id4,
297 uint32_t fifo,
bool enable)
300 ((uint32_t)id1 << 16) | (uint32_t)id2,
301 ((uint32_t)id3 << 16) | (uint32_t)id4, fifo, enable);
314 uint32_t id1, uint32_t id2,
315 uint32_t fifo,
bool enable)
355 uint8_t length, uint8_t *data)
358 uint32_t mailbox = 0;
398 CAN_TDTxR(canport, mailbox) &= ~CAN_TDTxR_DLC_MASK;
403 tdhxr.data8[3] = data[7];
406 tdhxr.data8[2] = data[6];
409 tdhxr.data8[1] = data[5];
412 tdhxr.data8[0] = data[4];
415 tdlxr.data8[3] = data[3];
418 tdlxr.data8[2] = data[2];
421 tdlxr.data8[1] = data[1];
424 tdlxr.data8[0] = data[0];
431 CAN_TDLxR(canport, mailbox) = tdlxr.data32;
432 CAN_TDHxR(canport, mailbox) = tdhxr.data32;
470void can_receive(uint32_t canport, uint8_t fifo,
bool release, uint32_t *
id,
471 bool *ext,
bool *rtr, uint8_t *fmi, uint8_t *length,
472 uint8_t *data, uint16_t *timestamp)
474 uint32_t fifo_id = 0;
481 fifo_id = fifoid_array[fifo];
514 *timestamp = (
CAN_RDTxR(canport, fifo_id) &
518 rdlxr.data32 =
CAN_RDLxR(canport, fifo_id);
519 rdhxr.data32 =
CAN_RDHxR(canport, fifo_id);
532 data[0] = rdlxr.data8[0];
533 data[1] = rdlxr.data8[1];
534 data[2] = rdlxr.data8[2];
535 data[3] = rdlxr.data8[3];
536 data[4] = rdhxr.data8[0];
537 data[5] = rdhxr.data8[1];
538 data[6] = rdhxr.data8[2];
539 data[7] = rdhxr.data8[3];
#define CAN_MSR_INAK_TIMEOUT
#define CAN_TDLxR(can_base, mbox)
bool can_available_mailbox(uint32_t canport)
void can_filter_init(uint32_t nr, bool scale_32bit, bool id_list_mode, uint32_t fr1, uint32_t fr2, uint32_t fifo, bool enable)
CAN Filter Init.
#define CAN_TDTxR(can_base, mbox)
#define CAN_FM1R(can_base)
#define CAN_FMR(can_base)
void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id, bool *ext, bool *rtr, uint8_t *fmi, uint8_t *length, uint8_t *data, uint16_t *timestamp)
CAN Receive Message.
#define CAN_TSR(can_base)
#define CAN_MCR(can_base)
#define CAN_RIxR_EXID_MASK
#define CAN_RDTxR_TIME_SHIFT
#define CAN_FiR1(can_base, bank)
#define CAN_TDTxR_DLC_MASK
#define CAN_RDTxR_TIME_MASK
void can_filter_id_list_32bit_init(uint32_t nr, uint32_t id1, uint32_t id2, uint32_t fifo, bool enable)
CAN Initialize a 32bit Message ID List Filter.
#define CAN_RDTxR_FMI_MASK
#define CAN_RIxR(can_base, fifo)
void can_filter_id_list_16bit_init(uint32_t nr, uint16_t id1, uint16_t id2, uint16_t id3, uint16_t id4, uint32_t fifo, bool enable)
CAN Initialize a 16bit Message ID List Filter.
int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart, bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2, uint32_t brp, bool loopback, bool silent)
CAN Init.
int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr, uint8_t length, uint8_t *data)
CAN Transmit Message.
void can_disable_irq(uint32_t canport, uint32_t irq)
CAN Disable IRQ.
#define CAN_RF0R(can_base)
#define CAN_RDLxR(can_base, fifo)
void can_reset(uint32_t canport)
CAN Reset.
#define CAN_TDHxR(can_base, mbox)
void can_enable_irq(uint32_t canport, uint32_t irq)
CAN Enable IRQ.
void can_filter_id_mask_16bit_init(uint32_t nr, uint16_t id1, uint16_t mask1, uint16_t id2, uint16_t mask2, uint32_t fifo, bool enable)
CAN Initialize a 16bit Message ID Mask Filter.
#define CAN_RIxR_EXID_SHIFT
#define CAN_BTR(can_base)
#define CAN_RIxR_STID_MASK
#define CAN_FS1R(can_base)
#define CAN_TIxR_STID_SHIFT
#define CAN_RDHxR(can_base, fifo)
#define CAN_FA1R(can_base)
void can_fifo_release(uint32_t canport, uint8_t fifo)
CAN Release FIFO.
#define CAN_FiR2(can_base, bank)
#define CAN_MSR(can_base)
#define CAN_RDTxR_FMI_SHIFT
#define CAN_TIxR_EXID_SHIFT
#define CAN_IER(can_base)
#define CAN_TIxR(can_base, mbox)
void can_filter_id_mask_32bit_init(uint32_t nr, uint32_t id, uint32_t mask, uint32_t fifo, bool enable)
CAN Initialize a 32bit Message ID Mask Filter.
#define CAN_RDTxR(can_base, fifo)
#define CAN_RDTxR_DLC_MASK
#define CAN_FFA1R(can_base)
#define CAN_RIxR_STID_SHIFT
#define CAN_RF1R(can_base)
void rcc_periph_reset_pulse(enum rcc_periph_rst rst)
Reset Peripheral, pulsed.