libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.

Defined Constants and Types for the STM32F1xx Reset and Clock Control More...

Collaboration diagram for RCC Defines:

Data Structures

struct  rcc_clock_scale
 

Modules

 RCC_CFGR Microcontroller Clock Output Source
 
 RCC_CFGR USB prescale Factors
 
 RCC_CFGR PLL Multiplication Factor
 
 RCC_CFGR HSE Divider for PLL
 
 RCC_CFGR PLL Clock Source
 
 RCC ADC clock prescaler enable values
 
 RCC_CFGR APBx prescale factors
 These can be used for both APB1 and APB2 prescaling.
 
 RCC_CFGR AHB prescale Factors
 
 RCC_CFGR System Clock Selection
 
 RCC_CFGR Deprecated dividers
 Older compatible definitions to ease migration.
 
 RCC_APB2RSTR reset values
 
 RCC_APB1RSTR reset values
 
 RCC_AHBENR enable values
 
 RCC_APB2ENR enable values
 
 RCC_APB1ENR enable values
 
 RCC_AHBRSTR reset values
 

Macros

#define RCC_CR   MMIO32(RCC_BASE + 0x00)
 
#define RCC_CFGR   MMIO32(RCC_BASE + 0x04)
 
#define RCC_CIR   MMIO32(RCC_BASE + 0x08)
 
#define RCC_APB2RSTR   MMIO32(RCC_BASE + 0x0c)
 
#define RCC_APB1RSTR   MMIO32(RCC_BASE + 0x10)
 
#define RCC_AHBENR   MMIO32(RCC_BASE + 0x14)
 
#define RCC_APB2ENR   MMIO32(RCC_BASE + 0x18)
 
#define RCC_APB1ENR   MMIO32(RCC_BASE + 0x1c)
 
#define RCC_BDCR   MMIO32(RCC_BASE + 0x20)
 
#define RCC_CSR   MMIO32(RCC_BASE + 0x24)
 
#define RCC_AHBRSTR   MMIO32(RCC_BASE + 0x28) /*(**)*/
 
#define RCC_CFGR2   MMIO32(RCC_BASE + 0x2c) /*(**)*/
 
#define RCC_CR_PLL3RDY   (1 << 29) /* (**) */
 
#define RCC_CR_PLL3ON   (1 << 28) /* (**) */
 
#define RCC_CR_PLL2RDY   (1 << 27) /* (**) */
 
#define RCC_CR_PLL2ON   (1 << 26) /* (**) */
 
#define RCC_CR_PLLRDY   (1 << 25)
 
#define RCC_CR_PLLON   (1 << 24)
 
#define RCC_CR_CSSON   (1 << 19)
 
#define RCC_CR_HSEBYP   (1 << 18)
 
#define RCC_CR_HSERDY   (1 << 17)
 
#define RCC_CR_HSEON   (1 << 16)
 
#define RCC_CR_HSIRDY   (1 << 1)
 
#define RCC_CR_HSION   (1 << 0)
 
#define RCC_CFGR_OTGFSPRE   (1 << 22) /* Connectivity line */
 
#define RCC_CFGR_USBPRE   (1 << 22) /* LD,MD, HD, XL */
 
#define RCC_CFGR_PLLMUL_SHIFT   18
 
#define RCC_CFGR_PLLMUL   (0xF << RCC_CFGR_PLLMUL_SHIFT)
 
#define RCC_CFGR_PLLXTPRE   (1 << 17)
 
#define RCC_CFGR_PLLSRC   (1 << 16)
 
#define RCC_CFGR_ADCPRE_SHIFT   14
 
#define RCC_CFGR_ADCPRE   (3 << RCC_CFGR_ADCPRE_SHIFT)
 
#define RCC_CFGR_PPRE2_SHIFT   11
 
#define RCC_CFGR_PPRE2_SHIFT   11
 
#define RCC_CFGR_PPRE2   (7 << RCC_CFGR_PPRE2_SHIFT)
 
#define RCC_CFGR_PPRE1_SHIFT   8
 
#define RCC_CFGR_PPRE1_SHIFT   8
 
#define RCC_CFGR_PPRE1   (7 << RCC_CFGR_PPRE1_SHIFT)
 
#define RCC_CFGR_HPRE_SHIFT   4
 
#define RCC_CFGR_HPRE   (0xF << RCC_CFGR_HPRE_SHIFT)
 
#define RCC_CFGR_SWS_SHIFT   2
 
#define RCC_CFGR_SWS   (3 << RCC_CFGR_SWS_SHIFT)
 
#define RCC_CFGR_SW_SHIFT   0
 
#define RCC_CFGR_SW   (3 << RCC_CFGR_SW_SHIFT)
 
#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3   0x0
 
#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2   0x1
 
#define RCC_CFGR_PPRE2_MASK   0x7
 
#define RCC_CFGR_PPRE1_MASK   0x7
 
#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK   0x0
 
#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK   0x1
 
#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK   0x2
 
#define RCC_CIR_CSSC   (1 << 23)
 
#define RCC_CIR_PLL3RDYC   (1 << 22) /* (**) */
 
#define RCC_CIR_PLL2RDYC   (1 << 21) /* (**) */
 
#define RCC_CIR_PLLRDYC   (1 << 20)
 
#define RCC_CIR_HSERDYC   (1 << 19)
 
#define RCC_CIR_HSIRDYC   (1 << 18)
 
#define RCC_CIR_LSERDYC   (1 << 17)
 
#define RCC_CIR_LSIRDYC   (1 << 16)
 
#define RCC_CIR_PLL3RDYIE   (1 << 14) /* (**) */
 
#define RCC_CIR_PLL2RDYIE   (1 << 13) /* (**) */
 
#define RCC_CIR_PLLRDYIE   (1 << 12)
 
#define RCC_CIR_HSERDYIE   (1 << 11)
 
#define RCC_CIR_HSIRDYIE   (1 << 10)
 
#define RCC_CIR_LSERDYIE   (1 << 9)
 
#define RCC_CIR_LSIRDYIE   (1 << 8)
 
#define RCC_CIR_CSSF   (1 << 7)
 
#define RCC_CIR_PLL3RDYF   (1 << 6) /* (**) */
 
#define RCC_CIR_PLL2RDYF   (1 << 5) /* (**) */
 
#define RCC_CIR_PLLRDYF   (1 << 4)
 
#define RCC_CIR_HSERDYF   (1 << 3)
 
#define RCC_CIR_HSIRDYF   (1 << 2)
 
#define RCC_CIR_LSERDYF   (1 << 1)
 
#define RCC_CIR_LSIRDYF   (1 << 0)
 
#define RCC_BDCR_BDRST   (1 << 16)
 
#define RCC_BDCR_RTCEN   (1 << 15)
 
#define RCC_BDCR_LSEBYP   (1 << 2)
 
#define RCC_BDCR_LSERDY   (1 << 1)
 
#define RCC_BDCR_LSEON   (1 << 0)
 
#define RCC_CSR_LPWRRSTF   (1 << 31)
 
#define RCC_CSR_WWDGRSTF   (1 << 30)
 
#define RCC_CSR_IWDGRSTF   (1 << 29)
 
#define RCC_CSR_SFTRSTF   (1 << 28)
 
#define RCC_CSR_PORRSTF   (1 << 27)
 
#define RCC_CSR_PINRSTF   (1 << 26)
 
#define RCC_CSR_RMVF   (1 << 24)
 
#define RCC_CSR_RESET_FLAGS
 
#define RCC_CSR_LSIRDY   (1 << 1)
 
#define RCC_CSR_LSION   (1 << 0)
 
#define RCC_CFGR2_I2S3SRC_SYSCLK   0x0
 
#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK   0x1
 
#define RCC_CFGR2_I2S2SRC_SYSCLK   0x0
 
#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK   0x1
 
#define RCC_CFGR2_I2S2SRC   (1 << 17)
 
#define RCC_CFGR2_PREDIV1SRC_HSE_CLK   0x0
 
#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK   0x1
 
#define RCC_CFGR2_PREDIV1SRC   (1 << 16)
 
#define RCC_CFGR2_PLL3MUL_SHIFT   12
 
#define RCC_CFGR2_PLL3MUL   (0xF << RCC_CFGR2_PLL3MUL_SHIFT)
 
#define RCC_CFGR2_PLL2MUL_SHIFT   8
 
#define RCC_CFGR2_PLL2MUL   (0xF << RCC_CFGR2_PLL2MUL_SHIFT)
 
#define RCC_CFGR2_PREDIV2_SHIFT   4
 
#define RCC_CFGR2_PREDIV2   (0xF << RCC_CFGR2_PREDIV2_SHIFT)
 
#define RCC_CFGR2_PREDIV1_SHIFT   0
 
#define RCC_CFGR2_PREDIV1   (0xF << RCC_CFGR2_PREDIV1_SHIFT)
 
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8   0x6
 
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9   0x7
 
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10   0x8
 
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11   0x9
 
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12   0xa
 
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13   0xb
 
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14   0xc
 
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16   0xe
 
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20   0xf
 
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8   0x6
 
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9   0x7
 
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10   0x8
 
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11   0x9
 
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12   0xa
 
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13   0xb
 
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14   0xc
 
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16   0xe
 
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20   0xf
 
#define RCC_CFGR2_PREDIV_NODIV   0x0
 
#define RCC_CFGR2_PREDIV_DIV2   0x1
 
#define RCC_CFGR2_PREDIV_DIV3   0x2
 
#define RCC_CFGR2_PREDIV_DIV4   0x3
 
#define RCC_CFGR2_PREDIV_DIV5   0x4
 
#define RCC_CFGR2_PREDIV_DIV6   0x5
 
#define RCC_CFGR2_PREDIV_DIV7   0x6
 
#define RCC_CFGR2_PREDIV_DIV8   0x7
 
#define RCC_CFGR2_PREDIV_DIV9   0x8
 
#define RCC_CFGR2_PREDIV_DIV10   0x9
 
#define RCC_CFGR2_PREDIV_DIV11   0xa
 
#define RCC_CFGR2_PREDIV_DIV12   0xb
 
#define RCC_CFGR2_PREDIV_DIV13   0xc
 
#define RCC_CFGR2_PREDIV_DIV14   0xd
 
#define RCC_CFGR2_PREDIV_DIV15   0xe
 
#define RCC_CFGR2_PREDIV_DIV16   0xf
 
#define RCC_CFGR2_PREDIV2_NODIV   0x0
 
#define RCC_CFGR2_PREDIV2_DIV2   0x1
 
#define RCC_CFGR2_PREDIV2_DIV3   0x2
 
#define RCC_CFGR2_PREDIV2_DIV4   0x3
 
#define RCC_CFGR2_PREDIV2_DIV5   0x4
 
#define RCC_CFGR2_PREDIV2_DIV6   0x5
 
#define RCC_CFGR2_PREDIV2_DIV7   0x6
 
#define RCC_CFGR2_PREDIV2_DIV8   0x7
 
#define RCC_CFGR2_PREDIV2_DIV9   0x8
 
#define RCC_CFGR2_PREDIV2_DIV10   0x9
 
#define RCC_CFGR2_PREDIV2_DIV11   0xa
 
#define RCC_CFGR2_PREDIV2_DIV12   0xb
 
#define RCC_CFGR2_PREDIV2_DIV13   0xc
 
#define RCC_CFGR2_PREDIV2_DIV14   0xd
 
#define RCC_CFGR2_PREDIV2_DIV15   0xe
 
#define RCC_CFGR2_PREDIV2_DIV16   0xf
 
#define _REG_BIT(base, bit)   (((base) << 5) + (bit))
 

Enumerations

enum  rcc_osc {
  RCC_PLL , RCC_PLL2 , RCC_PLL3 , RCC_HSE ,
  RCC_HSI , RCC_LSE , RCC_LSI
}
 
enum  rcc_periph_clken {
  RCC_DMA1 = _REG_BIT(0x14, 0) , RCC_DMA2 = _REG_BIT(0x14, 1) , RCC_SRAM = _REG_BIT(0x14, 2) , RCC_FLTF = _REG_BIT(0x14, 4) ,
  RCC_CRC = _REG_BIT(0x14, 6) , RCC_FSMC = _REG_BIT(0x14, 8) , RCC_SDIO = _REG_BIT(0x14, 10) , RCC_OTGFS = _REG_BIT(0x14, 12) ,
  RCC_ETHMAC = _REG_BIT(0x14, 14) , RCC_ETHMACTX = _REG_BIT(0x14, 15) , RCC_ETHMACRX = _REG_BIT(0x14, 16) , RCC_AFIO = _REG_BIT(0x18, 0) ,
  RCC_GPIOA = _REG_BIT(0x18, 2) , RCC_GPIOB = _REG_BIT(0x18, 3) , RCC_GPIOC = _REG_BIT(0x18, 4) , RCC_GPIOD = _REG_BIT(0x18, 5) ,
  RCC_GPIOE = _REG_BIT(0x18, 6) , RCC_GPIOF = _REG_BIT(0x18, 7) , RCC_GPIOG = _REG_BIT(0x18, 8) , RCC_ADC1 = _REG_BIT(0x18, 9) ,
  RCC_ADC2 = _REG_BIT(0x18, 10) , RCC_TIM1 = _REG_BIT(0x18, 11) , RCC_SPI1 = _REG_BIT(0x18, 12) , RCC_TIM8 = _REG_BIT(0x18, 13) ,
  RCC_USART1 = _REG_BIT(0x18, 14) , RCC_ADC3 = _REG_BIT(0x18, 15) , RCC_TIM15 = _REG_BIT(0x18, 16) , RCC_TIM16 = _REG_BIT(0x18, 17) ,
  RCC_TIM17 = _REG_BIT(0x18, 18) , RCC_TIM9 = _REG_BIT(0x18, 19) , RCC_TIM10 = _REG_BIT(0x18, 20) , RCC_TIM11 = _REG_BIT(0x18, 21) ,
  RCC_TIM2 = _REG_BIT(0x1C, 0) , RCC_TIM3 = _REG_BIT(0x1C, 1) , RCC_TIM4 = _REG_BIT(0x1C, 2) , RCC_TIM5 = _REG_BIT(0x1C, 3) ,
  RCC_TIM6 = _REG_BIT(0x1C, 4) , RCC_TIM7 = _REG_BIT(0x1C, 5) , RCC_TIM12 = _REG_BIT(0x1C, 6) , RCC_TIM13 = _REG_BIT(0x1C, 7) ,
  RCC_TIM14 = _REG_BIT(0x1C, 8) , RCC_WWDG = _REG_BIT(0x1C, 11) , RCC_SPI2 = _REG_BIT(0x1C, 14) , RCC_SPI3 = _REG_BIT(0x1C, 15) ,
  RCC_USART2 = _REG_BIT(0x1C, 17) , RCC_USART3 = _REG_BIT(0x1C, 18) , RCC_UART4 = _REG_BIT(0x1C, 19) , RCC_UART5 = _REG_BIT(0x1C, 20) ,
  RCC_I2C1 = _REG_BIT(0x1C, 21) , RCC_I2C2 = _REG_BIT(0x1C, 22) , RCC_USB = _REG_BIT(0x1C, 23) , RCC_CAN = _REG_BIT(0x1C, 25) ,
  RCC_CAN1 = _REG_BIT(0x1C, 25) , RCC_CAN2 = _REG_BIT(0x1C, 26) , RCC_BKP = _REG_BIT(0x1C, 27) , RCC_PWR = _REG_BIT(0x1C, 28) ,
  RCC_DAC = _REG_BIT(0x1C, 29) , RCC_CEC = _REG_BIT(0x1C, 30)
}
 
enum  rcc_periph_rst {
  RST_OTGFS = _REG_BIT(0x28, 12) , RST_ETHMAC = _REG_BIT(0x28, 14) , RST_AFIO = _REG_BIT(0x0c, 0) , RST_GPIOA = _REG_BIT(0x0c, 2) ,
  RST_GPIOB = _REG_BIT(0x0c, 3) , RST_GPIOC = _REG_BIT(0x0c, 4) , RST_GPIOD = _REG_BIT(0x0c, 5) , RST_GPIOE = _REG_BIT(0x0c, 6) ,
  RST_GPIOF = _REG_BIT(0x0c, 7) , RST_GPIOG = _REG_BIT(0x0c, 8) , RST_ADC1 = _REG_BIT(0x0c, 9) , RST_ADC2 = _REG_BIT(0x0c, 10) ,
  RST_TIM1 = _REG_BIT(0x0c, 11) , RST_SPI1 = _REG_BIT(0x0c, 12) , RST_TIM8 = _REG_BIT(0x0c, 13) , RST_USART1 = _REG_BIT(0x0c, 14) ,
  RST_ADC3 = _REG_BIT(0x0c, 15) , RST_TIM15 = _REG_BIT(0x0c, 16) , RST_TIM16 = _REG_BIT(0x0c, 17) , RST_TIM17 = _REG_BIT(0x0c, 18) ,
  RST_TIM9 = _REG_BIT(0x0c, 19) , RST_TIM10 = _REG_BIT(0x0c, 20) , RST_TIM11 = _REG_BIT(0x0c, 21) , RST_TIM2 = _REG_BIT(0x10, 0) ,
  RST_TIM3 = _REG_BIT(0x10, 1) , RST_TIM4 = _REG_BIT(0x10, 2) , RST_TIM5 = _REG_BIT(0x10, 3) , RST_TIM6 = _REG_BIT(0x10, 4) ,
  RST_TIM7 = _REG_BIT(0x10, 5) , RST_TIM12 = _REG_BIT(0x10, 6) , RST_TIM13 = _REG_BIT(0x10, 7) , RST_TIM14 = _REG_BIT(0x10, 8) ,
  RST_WWDG = _REG_BIT(0x10, 11) , RST_SPI2 = _REG_BIT(0x10, 14) , RST_SPI3 = _REG_BIT(0x10, 15) , RST_USART2 = _REG_BIT(0x10, 17) ,
  RST_USART3 = _REG_BIT(0x10, 18) , RST_UART4 = _REG_BIT(0x10, 19) , RST_UART5 = _REG_BIT(0x10, 20) , RST_I2C1 = _REG_BIT(0x10, 21) ,
  RST_I2C2 = _REG_BIT(0x10, 22) , RST_USB = _REG_BIT(0x10, 23) , RST_CAN = _REG_BIT(0x10, 25) , RST_CAN1 = _REG_BIT(0x10, 25) ,
  RST_CAN2 = _REG_BIT(0x10, 26) , RST_BKP = _REG_BIT(0x10, 27) , RST_PWR = _REG_BIT(0x10, 28) , RST_DAC = _REG_BIT(0x10, 29) ,
  RST_CEC = _REG_BIT(0x10, 30)
}
 
enum  rcc_clock_hsi { RCC_CLOCK_HSI_24MHZ , RCC_CLOCK_HSI_48MHZ , RCC_CLOCK_HSI_64MHZ , RCC_CLOCK_HSI_END }
 
enum  rcc_clock_hse {
  RCC_CLOCK_HSE12_72MHZ , RCC_CLOCK_HSE16_72MHZ , RCC_CLOCK_HSE25_72MHZ , RCC_CLOCK_HSE8_24MHZ ,
  RCC_CLOCK_HSE8_72MHZ , RCC_CLOCK_HSE_END
}
 

Functions

void rcc_osc_ready_int_clear (enum rcc_osc osc)
 RCC Clear the Oscillator Ready Interrupt Flag. More...
 
void rcc_osc_ready_int_enable (enum rcc_osc osc)
 RCC Enable the Oscillator Ready Interrupt. More...
 
void rcc_osc_ready_int_disable (enum rcc_osc osc)
 RCC Disable the Oscillator Ready Interrupt. More...
 
int rcc_osc_ready_int_flag (enum rcc_osc osc)
 RCC Read the Oscillator Ready Interrupt Flag. More...
 
void rcc_css_int_clear (void)
 RCC Clear the Clock Security System Interrupt Flag. More...
 
int rcc_css_int_flag (void)
 RCC Read the Clock Security System Interrupt Flag. More...
 
void rcc_osc_on (enum rcc_osc osc)
 RCC Turn on an Oscillator. More...
 
void rcc_osc_off (enum rcc_osc osc)
 RCC Turn off an Oscillator. More...
 
void rcc_css_enable (void)
 RCC Enable the Clock Security System. More...
 
void rcc_css_disable (void)
 RCC Disable the Clock Security System. More...
 
void rcc_set_sysclk_source (uint32_t clk)
 RCC Set the Source for the System Clock. More...
 
void rcc_set_pll_multiplication_factor (uint32_t mul)
 RCC Set the PLL Multiplication Factor. More...
 
void rcc_set_pll2_multiplication_factor (uint32_t mul)
 RCC Set the PLL2 Multiplication Factor. More...
 
void rcc_set_pll3_multiplication_factor (uint32_t mul)
 RCC Set the PLL3 Multiplication Factor. More...
 
void rcc_set_pll_source (uint32_t pllsrc)
 RCC Set the PLL Clock Source. More...
 
void rcc_set_pllxtpre (uint32_t pllxtpre)
 RCC Set the HSE Frequency Divider used as PLL Clock Source. More...
 
uint32_t rcc_rtc_clock_enabled_flag (void)
 RCC RTC Clock Enabled Flag. More...
 
void rcc_enable_rtc_clock (void)
 RCC Enable the RTC clock. More...
 
void rcc_set_rtc_clock_source (enum rcc_osc clock_source)
 RCC Set the Source for the RTC clock. More...
 
void rcc_set_adcpre (uint32_t adcpre)
 ADC Setup the A/D Clock. More...
 
void rcc_set_ppre2 (uint32_t ppre2)
 RCC Set the APB2 Prescale Factor. More...
 
void rcc_set_ppre1 (uint32_t ppre1)
 RCC Set the APB1 Prescale Factor. More...
 
void rcc_set_hpre (uint32_t hpre)
 RCC Set the AHB Prescale Factor. More...
 
void rcc_set_usbpre (uint32_t usbpre)
 RCC Set the USB Prescale Factor. More...
 
void rcc_set_prediv1 (uint32_t prediv)
 
void rcc_set_prediv2 (uint32_t prediv)
 
void rcc_set_prediv1_source (uint32_t rccsrc)
 
uint32_t rcc_system_clock_source (void)
 RCC Get the System Clock Source. More...
 
void rcc_clock_setup_in_hsi_out_64mhz (void) LIBOPENCM3_DEPRECATED("use rcc_clock_setup_pll( &rcc_hsi_configs[RCC_CLOCK_HSI_64MHZ])")
 
void rcc_clock_setup_in_hsi_out_48mhz (void) LIBOPENCM3_DEPRECATED("use rcc_clock_setup_pll( &rcc_hsi_configs[RCC_CLOCK_HSI_48MHZ])")
 
void rcc_clock_setup_in_hsi_out_24mhz (void) LIBOPENCM3_DEPRECATED("use rcc_clock_setup_pll( &rcc_hsi_configs[RCC_CLOCK_HSI_24MHZ])")
 
void rcc_clock_setup_in_hse_8mhz_out_24mhz (void) LIBOPENCM3_DEPRECATED("use rcc_clock_setup_pll( &rcc_hse_configs[RCC_CLOCK_HSE8_24MHZ])")
 
void rcc_clock_setup_in_hse_8mhz_out_72mhz (void) LIBOPENCM3_DEPRECATED("use rcc_clock_setup_pll( &rcc_hse_configs[RCC_CLOCK_HSE8_72MHZ])")
 
void rcc_clock_setup_in_hse_12mhz_out_72mhz (void) LIBOPENCM3_DEPRECATED("use rcc_clock_setup_pll( &rcc_hse_configs[RCC_CLOCK_HSE12_72MHZ])")
 
void rcc_clock_setup_in_hse_16mhz_out_72mhz (void) LIBOPENCM3_DEPRECATED("use rcc_clock_setup_pll( &rcc_hse_configs[RCC_CLOCK_HSE16_72MHZ])")
 
void rcc_clock_setup_in_hse_25mhz_out_72mhz (void) LIBOPENCM3_DEPRECATED("use rcc_clock_setup_pll( &rcc_hse_configs[RCC_CLOCK_HSE25_72MHZ])")
 
void rcc_clock_setup_pll (const struct rcc_clock_scale *clock)
 Switch sysclock to PLL with the given parameters. More...
 
void rcc_backupdomain_reset (void)
 RCC Reset the Backup Domain. More...
 
uint32_t rcc_get_usart_clk_freq (uint32_t usart)
 Get the peripheral clock speed for the USART at base specified. More...
 
uint32_t rcc_get_timer_clk_freq (uint32_t timer)
 Get the peripheral clock speed for the Timer at base specified. More...
 
uint32_t rcc_get_i2c_clk_freq (uint32_t i2c)
 Get the peripheral clock speed for the I2C device at base specified. More...
 
uint32_t rcc_get_spi_clk_freq (uint32_t spi)
 
void rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en)
 RCC Enable Peripheral Clocks. More...
 
void rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en)
 RCC Disable Peripheral Clocks. More...
 
void rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset)
 RCC Reset Peripherals. More...
 
void rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset)
 RCC Remove Reset on Peripherals. More...
 
void rcc_periph_clock_enable (enum rcc_periph_clken clken)
 Enable Peripheral Clock in running mode. More...
 
void rcc_periph_clock_disable (enum rcc_periph_clken clken)
 Disable Peripheral Clock in running mode. More...
 
void rcc_periph_reset_pulse (enum rcc_periph_rst rst)
 Reset Peripheral, pulsed. More...
 
void rcc_periph_reset_hold (enum rcc_periph_rst rst)
 Reset Peripheral, hold. More...
 
void rcc_periph_reset_release (enum rcc_periph_rst rst)
 Reset Peripheral, release. More...
 
void rcc_set_mco (uint32_t mcosrc)
 Select the source of Microcontroller Clock Output. More...
 
void rcc_osc_bypass_enable (enum rcc_osc osc)
 RCC Enable Bypass. More...
 
void rcc_osc_bypass_disable (enum rcc_osc osc)
 RCC Disable Bypass. More...
 
bool rcc_is_osc_ready (enum rcc_osc osc)
 Is the given oscillator ready? More...
 
void rcc_wait_for_osc_ready (enum rcc_osc osc)
 Wait for Oscillator Ready. More...
 
uint16_t rcc_get_div_from_hpre (uint8_t div_val)
 This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More...
 

Variables

uint32_t rcc_ahb_frequency
 
uint32_t rcc_apb1_frequency
 Set the default clock frequencies. More...
 
uint32_t rcc_apb2_frequency
 
const struct rcc_clock_scale rcc_hsi_configs [RCC_CLOCK_HSI_END]
 
const struct rcc_clock_scale rcc_hse_configs [RCC_CLOCK_HSE_END]
 

Detailed Description

Defined Constants and Types for the STM32F1xx Reset and Clock Control

Version
1.0.0
Author
© 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
© 2009 Uwe Hermann uwe@h.nosp@m.erma.nosp@m.nn-uw.nosp@m.e.de
Date
18 August 2012

LGPL License Terms libopencm3 License

Author
© 2013 Frantisek Burian BuFra.nosp@m.n@se.nosp@m.znam..nosp@m.cz

Macro Definition Documentation

◆ _REG_BIT

#define _REG_BIT (   base,
  bit 
)    (((base) << 5) + (bit))

Definition at line 571 of file f1/rcc.h.

◆ RCC_AHBENR

#define RCC_AHBENR   MMIO32(RCC_BASE + 0x14)

Definition at line 53 of file f1/rcc.h.

◆ RCC_AHBRSTR

#define RCC_AHBRSTR   MMIO32(RCC_BASE + 0x28) /*(**)*/

Definition at line 58 of file f1/rcc.h.

◆ RCC_APB1ENR

#define RCC_APB1ENR   MMIO32(RCC_BASE + 0x1c)

Definition at line 55 of file f1/rcc.h.

◆ RCC_APB1RSTR

#define RCC_APB1RSTR   MMIO32(RCC_BASE + 0x10)

Definition at line 52 of file f1/rcc.h.

◆ RCC_APB2ENR

#define RCC_APB2ENR   MMIO32(RCC_BASE + 0x18)

Definition at line 54 of file f1/rcc.h.

◆ RCC_APB2RSTR

#define RCC_APB2RSTR   MMIO32(RCC_BASE + 0x0c)

Definition at line 51 of file f1/rcc.h.

◆ RCC_BDCR

#define RCC_BDCR   MMIO32(RCC_BASE + 0x20)

Definition at line 56 of file f1/rcc.h.

◆ RCC_BDCR_BDRST

#define RCC_BDCR_BDRST   (1 << 16)

Definition at line 442 of file f1/rcc.h.

◆ RCC_BDCR_LSEBYP

#define RCC_BDCR_LSEBYP   (1 << 2)

Definition at line 445 of file f1/rcc.h.

◆ RCC_BDCR_LSEON

#define RCC_BDCR_LSEON   (1 << 0)

Definition at line 447 of file f1/rcc.h.

◆ RCC_BDCR_LSERDY

#define RCC_BDCR_LSERDY   (1 << 1)

Definition at line 446 of file f1/rcc.h.

◆ RCC_BDCR_RTCEN

#define RCC_BDCR_RTCEN   (1 << 15)

Definition at line 443 of file f1/rcc.h.

◆ RCC_CFGR

#define RCC_CFGR   MMIO32(RCC_BASE + 0x04)

Definition at line 49 of file f1/rcc.h.

◆ RCC_CFGR2

#define RCC_CFGR2   MMIO32(RCC_BASE + 0x2c) /*(**)*/

Definition at line 59 of file f1/rcc.h.

◆ RCC_CFGR2_I2S2SRC

#define RCC_CFGR2_I2S2SRC   (1 << 17)

Definition at line 483 of file f1/rcc.h.

◆ RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK

#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK   0x1

Definition at line 482 of file f1/rcc.h.

◆ RCC_CFGR2_I2S2SRC_SYSCLK

#define RCC_CFGR2_I2S2SRC_SYSCLK   0x0

Definition at line 481 of file f1/rcc.h.

◆ RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK

#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK   0x1

Definition at line 478 of file f1/rcc.h.

◆ RCC_CFGR2_I2S3SRC_SYSCLK

#define RCC_CFGR2_I2S3SRC_SYSCLK   0x0

Definition at line 477 of file f1/rcc.h.

◆ RCC_CFGR2_PLL2MUL

#define RCC_CFGR2_PLL2MUL   (0xF << RCC_CFGR2_PLL2MUL_SHIFT)

Definition at line 494 of file f1/rcc.h.

◆ RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10

#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10   0x8

Definition at line 516 of file f1/rcc.h.

◆ RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11

#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11   0x9

Definition at line 517 of file f1/rcc.h.

◆ RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12

#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12   0xa

Definition at line 518 of file f1/rcc.h.

◆ RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13

#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13   0xb

Definition at line 519 of file f1/rcc.h.

◆ RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14

#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14   0xc

Definition at line 520 of file f1/rcc.h.

◆ RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16

#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16   0xe

Definition at line 521 of file f1/rcc.h.

◆ RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20

#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20   0xf

Definition at line 522 of file f1/rcc.h.

◆ RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8

#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8   0x6

Definition at line 514 of file f1/rcc.h.

◆ RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9

#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9   0x7

Definition at line 515 of file f1/rcc.h.

◆ RCC_CFGR2_PLL2MUL_SHIFT

#define RCC_CFGR2_PLL2MUL_SHIFT   8

Definition at line 493 of file f1/rcc.h.

◆ RCC_CFGR2_PLL3MUL

#define RCC_CFGR2_PLL3MUL   (0xF << RCC_CFGR2_PLL3MUL_SHIFT)

Definition at line 491 of file f1/rcc.h.

◆ RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10

#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10   0x8

Definition at line 505 of file f1/rcc.h.

◆ RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11

#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11   0x9

Definition at line 506 of file f1/rcc.h.

◆ RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12

#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12   0xa

Definition at line 507 of file f1/rcc.h.

◆ RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13

#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13   0xb

Definition at line 508 of file f1/rcc.h.

◆ RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14

#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14   0xc

Definition at line 509 of file f1/rcc.h.

◆ RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16

#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16   0xe

Definition at line 510 of file f1/rcc.h.

◆ RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20

#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20   0xf

Definition at line 511 of file f1/rcc.h.

◆ RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8

#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8   0x6

Definition at line 503 of file f1/rcc.h.

◆ RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9

#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9   0x7

Definition at line 504 of file f1/rcc.h.

◆ RCC_CFGR2_PLL3MUL_SHIFT

#define RCC_CFGR2_PLL3MUL_SHIFT   12

Definition at line 490 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV1

#define RCC_CFGR2_PREDIV1   (0xF << RCC_CFGR2_PREDIV1_SHIFT)

Definition at line 500 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV1_SHIFT

#define RCC_CFGR2_PREDIV1_SHIFT   0

Definition at line 499 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV1SRC

#define RCC_CFGR2_PREDIV1SRC   (1 << 16)

Definition at line 488 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV1SRC_HSE_CLK

#define RCC_CFGR2_PREDIV1SRC_HSE_CLK   0x0

Definition at line 486 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV1SRC_PLL2_CLK

#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK   0x1

Definition at line 487 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2

#define RCC_CFGR2_PREDIV2   (0xF << RCC_CFGR2_PREDIV2_SHIFT)

Definition at line 497 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2_DIV10

#define RCC_CFGR2_PREDIV2_DIV10   0x9

Definition at line 552 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2_DIV11

#define RCC_CFGR2_PREDIV2_DIV11   0xa

Definition at line 553 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2_DIV12

#define RCC_CFGR2_PREDIV2_DIV12   0xb

Definition at line 554 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2_DIV13

#define RCC_CFGR2_PREDIV2_DIV13   0xc

Definition at line 555 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2_DIV14

#define RCC_CFGR2_PREDIV2_DIV14   0xd

Definition at line 556 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2_DIV15

#define RCC_CFGR2_PREDIV2_DIV15   0xe

Definition at line 557 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2_DIV16

#define RCC_CFGR2_PREDIV2_DIV16   0xf

Definition at line 558 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2_DIV2

#define RCC_CFGR2_PREDIV2_DIV2   0x1

Definition at line 544 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2_DIV3

#define RCC_CFGR2_PREDIV2_DIV3   0x2

Definition at line 545 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2_DIV4

#define RCC_CFGR2_PREDIV2_DIV4   0x3

Definition at line 546 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2_DIV5

#define RCC_CFGR2_PREDIV2_DIV5   0x4

Definition at line 547 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2_DIV6

#define RCC_CFGR2_PREDIV2_DIV6   0x5

Definition at line 548 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2_DIV7

#define RCC_CFGR2_PREDIV2_DIV7   0x6

Definition at line 549 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2_DIV8

#define RCC_CFGR2_PREDIV2_DIV8   0x7

Definition at line 550 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2_DIV9

#define RCC_CFGR2_PREDIV2_DIV9   0x8

Definition at line 551 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2_NODIV

#define RCC_CFGR2_PREDIV2_NODIV   0x0

Definition at line 543 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV2_SHIFT

#define RCC_CFGR2_PREDIV2_SHIFT   4

Definition at line 496 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV10

#define RCC_CFGR2_PREDIV_DIV10   0x9

Definition at line 534 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV11

#define RCC_CFGR2_PREDIV_DIV11   0xa

Definition at line 535 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV12

#define RCC_CFGR2_PREDIV_DIV12   0xb

Definition at line 536 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV13

#define RCC_CFGR2_PREDIV_DIV13   0xc

Definition at line 537 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV14

#define RCC_CFGR2_PREDIV_DIV14   0xd

Definition at line 538 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV15

#define RCC_CFGR2_PREDIV_DIV15   0xe

Definition at line 539 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV16

#define RCC_CFGR2_PREDIV_DIV16   0xf

Definition at line 540 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV2

#define RCC_CFGR2_PREDIV_DIV2   0x1

Definition at line 526 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV3

#define RCC_CFGR2_PREDIV_DIV3   0x2

Definition at line 527 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV4

#define RCC_CFGR2_PREDIV_DIV4   0x3

Definition at line 528 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV5

#define RCC_CFGR2_PREDIV_DIV5   0x4

Definition at line 529 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV6

#define RCC_CFGR2_PREDIV_DIV6   0x5

Definition at line 530 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV7

#define RCC_CFGR2_PREDIV_DIV7   0x6

Definition at line 531 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV8

#define RCC_CFGR2_PREDIV_DIV8   0x7

Definition at line 532 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV_DIV9

#define RCC_CFGR2_PREDIV_DIV9   0x8

Definition at line 533 of file f1/rcc.h.

◆ RCC_CFGR2_PREDIV_NODIV

#define RCC_CFGR2_PREDIV_NODIV   0x0

Definition at line 525 of file f1/rcc.h.

◆ RCC_CFGR_ADCPRE

#define RCC_CFGR_ADCPRE   (3 << RCC_CFGR_ADCPRE_SHIFT)

Definition at line 90 of file f1/rcc.h.

◆ RCC_CFGR_ADCPRE_SHIFT

#define RCC_CFGR_ADCPRE_SHIFT   14

Definition at line 89 of file f1/rcc.h.

◆ RCC_CFGR_HPRE

#define RCC_CFGR_HPRE   (0xF << RCC_CFGR_HPRE_SHIFT)

Definition at line 99 of file f1/rcc.h.

◆ RCC_CFGR_HPRE_SHIFT

#define RCC_CFGR_HPRE_SHIFT   4

Definition at line 98 of file f1/rcc.h.

◆ RCC_CFGR_OTGFSPRE

#define RCC_CFGR_OTGFSPRE   (1 << 22) /* Connectivity line */

Definition at line 80 of file f1/rcc.h.

◆ RCC_CFGR_PLLMUL

#define RCC_CFGR_PLLMUL   (0xF << RCC_CFGR_PLLMUL_SHIFT)

Definition at line 84 of file f1/rcc.h.

◆ RCC_CFGR_PLLMUL_SHIFT

#define RCC_CFGR_PLLMUL_SHIFT   18

Definition at line 83 of file f1/rcc.h.

◆ RCC_CFGR_PLLSRC

#define RCC_CFGR_PLLSRC   (1 << 16)

Definition at line 87 of file f1/rcc.h.

◆ RCC_CFGR_PLLXTPRE

#define RCC_CFGR_PLLXTPRE   (1 << 17)

Definition at line 86 of file f1/rcc.h.

◆ RCC_CFGR_PPRE1

#define RCC_CFGR_PPRE1   (7 << RCC_CFGR_PPRE1_SHIFT)

Definition at line 96 of file f1/rcc.h.

◆ RCC_CFGR_PPRE1_MASK

#define RCC_CFGR_PPRE1_MASK   0x7

Definition at line 197 of file f1/rcc.h.

◆ RCC_CFGR_PPRE1_SHIFT [1/2]

#define RCC_CFGR_PPRE1_SHIFT   8

Definition at line 196 of file f1/rcc.h.

◆ RCC_CFGR_PPRE1_SHIFT [2/2]

#define RCC_CFGR_PPRE1_SHIFT   8

Definition at line 196 of file f1/rcc.h.

◆ RCC_CFGR_PPRE2

#define RCC_CFGR_PPRE2   (7 << RCC_CFGR_PPRE2_SHIFT)

Definition at line 93 of file f1/rcc.h.

◆ RCC_CFGR_PPRE2_MASK

#define RCC_CFGR_PPRE2_MASK   0x7

Definition at line 195 of file f1/rcc.h.

◆ RCC_CFGR_PPRE2_SHIFT [1/2]

#define RCC_CFGR_PPRE2_SHIFT   11

Definition at line 194 of file f1/rcc.h.

◆ RCC_CFGR_PPRE2_SHIFT [2/2]

#define RCC_CFGR_PPRE2_SHIFT   11

Definition at line 194 of file f1/rcc.h.

◆ RCC_CFGR_SW

#define RCC_CFGR_SW   (3 << RCC_CFGR_SW_SHIFT)

Definition at line 105 of file f1/rcc.h.

◆ RCC_CFGR_SW_SHIFT

#define RCC_CFGR_SW_SHIFT   0

Definition at line 104 of file f1/rcc.h.

◆ RCC_CFGR_SWS

#define RCC_CFGR_SWS   (3 << RCC_CFGR_SWS_SHIFT)

Definition at line 102 of file f1/rcc.h.

◆ RCC_CFGR_SWS_SHIFT

#define RCC_CFGR_SWS_SHIFT   2

Definition at line 101 of file f1/rcc.h.

◆ RCC_CFGR_SWS_SYSCLKSEL_HSECLK

#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK   0x1

Definition at line 227 of file f1/rcc.h.

◆ RCC_CFGR_SWS_SYSCLKSEL_HSICLK

#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK   0x0

Definition at line 226 of file f1/rcc.h.

◆ RCC_CFGR_SWS_SYSCLKSEL_PLLCLK

#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK   0x2

Definition at line 228 of file f1/rcc.h.

◆ RCC_CFGR_USBPRE

#define RCC_CFGR_USBPRE   (1 << 22) /* LD,MD, HD, XL */

Definition at line 81 of file f1/rcc.h.

◆ RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2

#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2   0x1

Definition at line 136 of file f1/rcc.h.

◆ RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3

#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3   0x0

Definition at line 135 of file f1/rcc.h.

◆ RCC_CIR

#define RCC_CIR   MMIO32(RCC_BASE + 0x08)

Definition at line 50 of file f1/rcc.h.

◆ RCC_CIR_CSSC

#define RCC_CIR_CSSC   (1 << 23)

Definition at line 277 of file f1/rcc.h.

◆ RCC_CIR_CSSF

#define RCC_CIR_CSSF   (1 << 7)

Definition at line 298 of file f1/rcc.h.

◆ RCC_CIR_HSERDYC

#define RCC_CIR_HSERDYC   (1 << 19)

Definition at line 283 of file f1/rcc.h.

◆ RCC_CIR_HSERDYF

#define RCC_CIR_HSERDYF   (1 << 3)

Definition at line 304 of file f1/rcc.h.

◆ RCC_CIR_HSERDYIE

#define RCC_CIR_HSERDYIE   (1 << 11)

Definition at line 292 of file f1/rcc.h.

◆ RCC_CIR_HSIRDYC

#define RCC_CIR_HSIRDYC   (1 << 18)

Definition at line 284 of file f1/rcc.h.

◆ RCC_CIR_HSIRDYF

#define RCC_CIR_HSIRDYF   (1 << 2)

Definition at line 305 of file f1/rcc.h.

◆ RCC_CIR_HSIRDYIE

#define RCC_CIR_HSIRDYIE   (1 << 10)

Definition at line 293 of file f1/rcc.h.

◆ RCC_CIR_LSERDYC

#define RCC_CIR_LSERDYC   (1 << 17)

Definition at line 285 of file f1/rcc.h.

◆ RCC_CIR_LSERDYF

#define RCC_CIR_LSERDYF   (1 << 1)

Definition at line 306 of file f1/rcc.h.

◆ RCC_CIR_LSERDYIE

#define RCC_CIR_LSERDYIE   (1 << 9)

Definition at line 294 of file f1/rcc.h.

◆ RCC_CIR_LSIRDYC

#define RCC_CIR_LSIRDYC   (1 << 16)

Definition at line 286 of file f1/rcc.h.

◆ RCC_CIR_LSIRDYF

#define RCC_CIR_LSIRDYF   (1 << 0)

Definition at line 307 of file f1/rcc.h.

◆ RCC_CIR_LSIRDYIE

#define RCC_CIR_LSIRDYIE   (1 << 8)

Definition at line 295 of file f1/rcc.h.

◆ RCC_CIR_PLL2RDYC

#define RCC_CIR_PLL2RDYC   (1 << 21) /* (**) */

Definition at line 281 of file f1/rcc.h.

◆ RCC_CIR_PLL2RDYF

#define RCC_CIR_PLL2RDYF   (1 << 5) /* (**) */

Definition at line 302 of file f1/rcc.h.

◆ RCC_CIR_PLL2RDYIE

#define RCC_CIR_PLL2RDYIE   (1 << 13) /* (**) */

Definition at line 290 of file f1/rcc.h.

◆ RCC_CIR_PLL3RDYC

#define RCC_CIR_PLL3RDYC   (1 << 22) /* (**) */

Definition at line 280 of file f1/rcc.h.

◆ RCC_CIR_PLL3RDYF

#define RCC_CIR_PLL3RDYF   (1 << 6) /* (**) */

Definition at line 301 of file f1/rcc.h.

◆ RCC_CIR_PLL3RDYIE

#define RCC_CIR_PLL3RDYIE   (1 << 14) /* (**) */

Definition at line 289 of file f1/rcc.h.

◆ RCC_CIR_PLLRDYC

#define RCC_CIR_PLLRDYC   (1 << 20)

Definition at line 282 of file f1/rcc.h.

◆ RCC_CIR_PLLRDYF

#define RCC_CIR_PLLRDYF   (1 << 4)

Definition at line 303 of file f1/rcc.h.

◆ RCC_CIR_PLLRDYIE

#define RCC_CIR_PLLRDYIE   (1 << 12)

Definition at line 291 of file f1/rcc.h.

◆ RCC_CR

#define RCC_CR   MMIO32(RCC_BASE + 0x00)

Definition at line 48 of file f1/rcc.h.

◆ RCC_CR_CSSON

#define RCC_CR_CSSON   (1 << 19)

Definition at line 69 of file f1/rcc.h.

◆ RCC_CR_HSEBYP

#define RCC_CR_HSEBYP   (1 << 18)

Definition at line 70 of file f1/rcc.h.

◆ RCC_CR_HSEON

#define RCC_CR_HSEON   (1 << 16)

Definition at line 72 of file f1/rcc.h.

◆ RCC_CR_HSERDY

#define RCC_CR_HSERDY   (1 << 17)

Definition at line 71 of file f1/rcc.h.

◆ RCC_CR_HSION

#define RCC_CR_HSION   (1 << 0)

Definition at line 76 of file f1/rcc.h.

◆ RCC_CR_HSIRDY

#define RCC_CR_HSIRDY   (1 << 1)

Definition at line 75 of file f1/rcc.h.

◆ RCC_CR_PLL2ON

#define RCC_CR_PLL2ON   (1 << 26) /* (**) */

Definition at line 66 of file f1/rcc.h.

◆ RCC_CR_PLL2RDY

#define RCC_CR_PLL2RDY   (1 << 27) /* (**) */

Definition at line 65 of file f1/rcc.h.

◆ RCC_CR_PLL3ON

#define RCC_CR_PLL3ON   (1 << 28) /* (**) */

Definition at line 64 of file f1/rcc.h.

◆ RCC_CR_PLL3RDY

#define RCC_CR_PLL3RDY   (1 << 29) /* (**) */

Definition at line 63 of file f1/rcc.h.

◆ RCC_CR_PLLON

#define RCC_CR_PLLON   (1 << 24)

Definition at line 68 of file f1/rcc.h.

◆ RCC_CR_PLLRDY

#define RCC_CR_PLLRDY   (1 << 25)

Definition at line 67 of file f1/rcc.h.

◆ RCC_CSR

#define RCC_CSR   MMIO32(RCC_BASE + 0x24)

Definition at line 57 of file f1/rcc.h.

◆ RCC_CSR_IWDGRSTF

#define RCC_CSR_IWDGRSTF   (1 << 29)

Definition at line 453 of file f1/rcc.h.

◆ RCC_CSR_LPWRRSTF

#define RCC_CSR_LPWRRSTF   (1 << 31)

Definition at line 451 of file f1/rcc.h.

◆ RCC_CSR_LSION

#define RCC_CSR_LSION   (1 << 0)

Definition at line 462 of file f1/rcc.h.

◆ RCC_CSR_LSIRDY

#define RCC_CSR_LSIRDY   (1 << 1)

Definition at line 461 of file f1/rcc.h.

◆ RCC_CSR_PINRSTF

#define RCC_CSR_PINRSTF   (1 << 26)

Definition at line 456 of file f1/rcc.h.

◆ RCC_CSR_PORRSTF

#define RCC_CSR_PORRSTF   (1 << 27)

Definition at line 455 of file f1/rcc.h.

◆ RCC_CSR_RESET_FLAGS

#define RCC_CSR_RESET_FLAGS
Value:
RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF |\
RCC_CSR_PINRSTF)
#define RCC_CSR_SFTRSTF
Definition: f1/rcc.h:454
#define RCC_CSR_LPWRRSTF
Definition: f1/rcc.h:451
#define RCC_CSR_PORRSTF
Definition: f1/rcc.h:455
#define RCC_CSR_WWDGRSTF
Definition: f1/rcc.h:452

Definition at line 458 of file f1/rcc.h.

◆ RCC_CSR_RMVF

#define RCC_CSR_RMVF   (1 << 24)

Definition at line 457 of file f1/rcc.h.

◆ RCC_CSR_SFTRSTF

#define RCC_CSR_SFTRSTF   (1 << 28)

Definition at line 454 of file f1/rcc.h.

◆ RCC_CSR_WWDGRSTF

#define RCC_CSR_WWDGRSTF   (1 << 30)

Definition at line 452 of file f1/rcc.h.

Enumeration Type Documentation

◆ rcc_clock_hse

Enumerator
RCC_CLOCK_HSE12_72MHZ 
RCC_CLOCK_HSE16_72MHZ 
RCC_CLOCK_HSE25_72MHZ 
RCC_CLOCK_HSE8_24MHZ 
RCC_CLOCK_HSE8_72MHZ 
RCC_CLOCK_HSE_END 

Definition at line 711 of file f1/rcc.h.

◆ rcc_clock_hsi

Enumerator
RCC_CLOCK_HSI_24MHZ 
RCC_CLOCK_HSI_48MHZ 
RCC_CLOCK_HSI_64MHZ 
RCC_CLOCK_HSI_END 

Definition at line 704 of file f1/rcc.h.

◆ rcc_osc

enum rcc_osc
Enumerator
RCC_PLL 
RCC_PLL2 
RCC_PLL3 
RCC_HSE 
RCC_HSI 
RCC_LSE 
RCC_LSI 

Definition at line 567 of file f1/rcc.h.

◆ rcc_periph_clken

Enumerator
RCC_DMA1 
RCC_DMA2 
RCC_SRAM 
RCC_FLTF 
RCC_CRC 
RCC_FSMC 
RCC_SDIO 
RCC_OTGFS 
RCC_ETHMAC 
RCC_ETHMACTX 
RCC_ETHMACRX 
RCC_AFIO 
RCC_GPIOA 
RCC_GPIOB 
RCC_GPIOC 
RCC_GPIOD 
RCC_GPIOE 
RCC_GPIOF 
RCC_GPIOG 
RCC_ADC1 
RCC_ADC2 
RCC_TIM1 
RCC_SPI1 
RCC_TIM8 
RCC_USART1 
RCC_ADC3 
RCC_TIM15 
RCC_TIM16 
RCC_TIM17 
RCC_TIM9 
RCC_TIM10 
RCC_TIM11 
RCC_TIM2 
RCC_TIM3 
RCC_TIM4 
RCC_TIM5 
RCC_TIM6 
RCC_TIM7 
RCC_TIM12 
RCC_TIM13 
RCC_TIM14 
RCC_WWDG 
RCC_SPI2 
RCC_SPI3 
RCC_USART2 
RCC_USART3 
RCC_UART4 
RCC_UART5 
RCC_I2C1 
RCC_I2C2 
RCC_USB 
RCC_CAN 
RCC_CAN1 
RCC_CAN2 
RCC_BKP 
RCC_PWR 
RCC_DAC 
RCC_CEC 

Definition at line 577 of file f1/rcc.h.

◆ rcc_periph_rst

Enumerator
RST_OTGFS 
RST_ETHMAC 
RST_AFIO 
RST_GPIOA 
RST_GPIOB 
RST_GPIOC 
RST_GPIOD 
RST_GPIOE 
RST_GPIOF 
RST_GPIOG 
RST_ADC1 
RST_ADC2 
RST_TIM1 
RST_SPI1 
RST_TIM8 
RST_USART1 
RST_ADC3 
RST_TIM15 
RST_TIM16 
RST_TIM17 
RST_TIM9 
RST_TIM10 
RST_TIM11 
RST_TIM2 
RST_TIM3 
RST_TIM4 
RST_TIM5 
RST_TIM6 
RST_TIM7 
RST_TIM12 
RST_TIM13 
RST_TIM14 
RST_WWDG 
RST_SPI2 
RST_SPI3 
RST_USART2 
RST_USART3 
RST_UART4 
RST_UART5 
RST_I2C1 
RST_I2C2 
RST_USB 
RST_CAN 
RST_CAN1 
RST_CAN2 
RST_BKP 
RST_PWR 
RST_DAC 
RST_CEC 

Definition at line 644 of file f1/rcc.h.

Function Documentation

◆ rcc_backupdomain_reset()

void rcc_backupdomain_reset ( void  )

RCC Reset the Backup Domain.

The backup domain registers are reset to disable RTC controls and clear user data.

Definition at line 1283 of file rcc.c.

References RCC_BDCR, and RCC_BDCR_BDRST.

◆ rcc_clock_setup_in_hse_12mhz_out_72mhz()

void rcc_clock_setup_in_hse_12mhz_out_72mhz ( void  ) &

◆ rcc_clock_setup_in_hse_16mhz_out_72mhz()

void rcc_clock_setup_in_hse_16mhz_out_72mhz ( void  ) &

◆ rcc_clock_setup_in_hse_25mhz_out_72mhz()

void rcc_clock_setup_in_hse_25mhz_out_72mhz ( void  ) &

◆ rcc_clock_setup_in_hse_8mhz_out_24mhz()

void rcc_clock_setup_in_hse_8mhz_out_24mhz ( void  ) &

◆ rcc_clock_setup_in_hse_8mhz_out_72mhz()

void rcc_clock_setup_in_hse_8mhz_out_72mhz ( void  ) &

◆ rcc_clock_setup_in_hsi_out_24mhz()

void rcc_clock_setup_in_hsi_out_24mhz ( void  ) &

◆ rcc_clock_setup_in_hsi_out_48mhz()

void rcc_clock_setup_in_hsi_out_48mhz ( void  ) &

◆ rcc_clock_setup_in_hsi_out_64mhz()

void rcc_clock_setup_in_hsi_out_64mhz ( void  ) &

◆ rcc_clock_setup_pll()

◆ rcc_css_disable()

void rcc_css_disable ( void  )

RCC Disable the Clock Security System.

Definition at line 467 of file rcc.c.

References RCC_CR, and RCC_CR_CSSON.

◆ rcc_css_enable()

void rcc_css_enable ( void  )

RCC Enable the Clock Security System.

Definition at line 457 of file rcc.c.

References RCC_CR, and RCC_CR_CSSON.

◆ rcc_css_int_clear()

void rcc_css_int_clear ( void  )

RCC Clear the Clock Security System Interrupt Flag.

Definition at line 327 of file rcc.c.

References RCC_CIR, and RCC_CIR_CSSC.

◆ rcc_css_int_flag()

int rcc_css_int_flag ( void  )

RCC Read the Clock Security System Interrupt Flag.

Returns
int. Boolean value for flag set.

Definition at line 338 of file rcc.c.

References RCC_CIR, and RCC_CIR_CSSF.

◆ rcc_enable_rtc_clock()

void rcc_enable_rtc_clock ( void  )

RCC Enable the RTC clock.

Definition at line 570 of file rcc.c.

References RCC_BDCR, and RCC_BDCR_RTCEN.

Referenced by rtc_awake_from_off().

Here is the caller graph for this function:

◆ rcc_get_div_from_hpre()

uint16_t rcc_get_div_from_hpre ( uint8_t  div_val)

This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.

Parameters
div_valMasked and shifted divider value from register (e.g. RCC_CFGR)

Definition at line 276 of file rcc_common_all.c.

◆ rcc_get_i2c_clk_freq()

uint32_t rcc_get_i2c_clk_freq ( uint32_t  i2c)

Get the peripheral clock speed for the I2C device at base specified.

Parameters
i2cBase address of I2C to get clock frequency for.

Definition at line 1328 of file rcc.c.

References rcc_apb1_frequency.

◆ rcc_get_spi_clk_freq()

uint32_t rcc_get_spi_clk_freq ( uint32_t  spi)

◆ rcc_get_timer_clk_freq()

uint32_t rcc_get_timer_clk_freq ( uint32_t  timer)

Get the peripheral clock speed for the Timer at base specified.

Parameters
timerBase address of TIM to get clock frequency for.

Definition at line 1309 of file rcc.c.

References cm3_assert_not_reached, rcc_clock_scale::ppre1, rcc_clock_scale::ppre2, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CFGR, RCC_CFGR_PPRE1_HCLK_NODIV, RCC_CFGR_PPRE1_MASK, RCC_CFGR_PPRE1_SHIFT, RCC_CFGR_PPRE2_HCLK_NODIV, RCC_CFGR_PPRE2_MASK, RCC_CFGR_PPRE2_SHIFT, TIM14_BASE, and TIM2_BASE.

◆ rcc_get_usart_clk_freq()

uint32_t rcc_get_usart_clk_freq ( uint32_t  usart)

Get the peripheral clock speed for the USART at base specified.

Parameters
usartBase address of USART to get clock frequency for.

Definition at line 1296 of file rcc.c.

References rcc_apb1_frequency, rcc_apb2_frequency, and USART1_BASE.

◆ rcc_is_osc_ready()

bool rcc_is_osc_ready ( enum rcc_osc  osc)

Is the given oscillator ready?

Parameters
oscOscillator ID
Returns
true if the hardware indicates the oscillator is ready.

Definition at line 343 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSERDY, RCC_CR, RCC_CR_HSERDY, RCC_CR_HSIRDY, RCC_CR_PLL2RDY, RCC_CR_PLL3RDY, RCC_CR_PLLRDY, RCC_CSR, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_PLL, RCC_PLL2, and RCC_PLL3.

Referenced by rcc_wait_for_osc_ready().

Here is the caller graph for this function:

◆ rcc_osc_bypass_disable()

void rcc_osc_bypass_disable ( enum rcc_osc  osc)

RCC Disable Bypass.

Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note
The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see rcc_backupdomain_reset).
Parameters
[in]oscOscillator ID. Only HSE and LSE have effect.

Definition at line 254 of file rcc_common_all.c.

References RCC_BDCR, RCC_BDCR_LSEBYP, RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_bypass_enable()

void rcc_osc_bypass_enable ( enum rcc_osc  osc)

RCC Enable Bypass.

Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note
The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).
Parameters
[in]oscOscillator ID. Only HSE and LSE have effect.

Definition at line 224 of file rcc_common_all.c.

References RCC_BDCR, RCC_BDCR_LSEBYP, RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_off()

void rcc_osc_off ( enum rcc_osc  osc)

RCC Turn off an Oscillator.

Disable an oscillator and power off.

Note
An oscillator cannot be turned off if it is selected as the system clock.
The LSE clock is in the backup domain and cannot be disabled until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been (see reset rcc_backupdomain_reset).
Parameters
[in]oscOscillator ID

Definition at line 425 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSEON, RCC_CR, RCC_CR_HSEON, RCC_CR_HSION, RCC_CR_PLL2ON, RCC_CR_PLL3ON, RCC_CR_PLLON, RCC_CSR, RCC_CSR_LSION, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_PLL, RCC_PLL2, and RCC_PLL3.

◆ rcc_osc_on()

void rcc_osc_on ( enum rcc_osc  osc)

RCC Turn on an Oscillator.

Enable an oscillator and power on. Each oscillator requires an amount of time to settle to a usable state. Refer to datasheets for time delay information. A status flag is available to indicate when the oscillator becomes ready (see rcc_osc_ready_int_flag and rcc_wait_for_osc_ready).

Note
The LSE clock is in the backup domain and cannot be enabled until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).
Parameters
[in]oscOscillator ID

Definition at line 384 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSEON, RCC_CR, RCC_CR_HSEON, RCC_CR_HSION, RCC_CR_PLL2ON, RCC_CR_PLL3ON, RCC_CR_PLLON, RCC_CSR, RCC_CSR_LSION, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_PLL, RCC_PLL2, and RCC_PLL3.

Referenced by rcc_clock_setup_in_hse_12mhz_out_72mhz(), rcc_clock_setup_in_hse_16mhz_out_72mhz(), rcc_clock_setup_in_hse_25mhz_out_72mhz(), rcc_clock_setup_in_hse_8mhz_out_24mhz(), rcc_clock_setup_in_hse_8mhz_out_72mhz(), rcc_clock_setup_in_hsi_out_24mhz(), rcc_clock_setup_in_hsi_out_48mhz(), rcc_clock_setup_in_hsi_out_64mhz(), and rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_osc_ready_int_clear()

void rcc_osc_ready_int_clear ( enum rcc_osc  osc)

RCC Clear the Oscillator Ready Interrupt Flag.

Clear the interrupt flag that was set when a clock oscillator became ready to use.

Parameters
[in]oscOscillator ID

Definition at line 193 of file rcc.c.

References RCC_CIR, RCC_CIR_HSERDYC, RCC_CIR_HSIRDYC, RCC_CIR_LSERDYC, RCC_CIR_LSIRDYC, RCC_CIR_PLL2RDYC, RCC_CIR_PLL3RDYC, RCC_CIR_PLLRDYC, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_PLL, RCC_PLL2, and RCC_PLL3.

◆ rcc_osc_ready_int_disable()

void rcc_osc_ready_int_disable ( enum rcc_osc  osc)

RCC Disable the Oscillator Ready Interrupt.

Parameters
[in]oscOscillator ID

Definition at line 259 of file rcc.c.

References RCC_CIR, RCC_CIR_HSERDYIE, RCC_CIR_HSIRDYIE, RCC_CIR_LSERDYIE, RCC_CIR_LSIRDYIE, RCC_CIR_PLL2RDYIE, RCC_CIR_PLL3RDYIE, RCC_CIR_PLLRDYIE, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_PLL, RCC_PLL2, and RCC_PLL3.

◆ rcc_osc_ready_int_enable()

void rcc_osc_ready_int_enable ( enum rcc_osc  osc)

RCC Enable the Oscillator Ready Interrupt.

Parameters
oscOscillator ID

Definition at line 226 of file rcc.c.

References RCC_CIR, RCC_CIR_HSERDYIE, RCC_CIR_HSIRDYIE, RCC_CIR_LSERDYIE, RCC_CIR_LSIRDYIE, RCC_CIR_PLL2RDYIE, RCC_CIR_PLL3RDYIE, RCC_CIR_PLLRDYIE, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_PLL, RCC_PLL2, and RCC_PLL3.

◆ rcc_osc_ready_int_flag()

int rcc_osc_ready_int_flag ( enum rcc_osc  osc)

RCC Read the Oscillator Ready Interrupt Flag.

Parameters
[in]oscOscillator ID
Returns
int. Boolean value for flag set.

Definition at line 293 of file rcc.c.

References cm3_assert_not_reached, RCC_CIR, RCC_CIR_HSERDYF, RCC_CIR_HSIRDYF, RCC_CIR_LSERDYF, RCC_CIR_LSIRDYF, RCC_CIR_PLL2RDYF, RCC_CIR_PLL3RDYF, RCC_CIR_PLLRDYF, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_PLL, RCC_PLL2, and RCC_PLL3.

◆ rcc_periph_clock_disable()

void rcc_periph_clock_disable ( enum rcc_periph_clken  clken)

Disable Peripheral Clock in running mode.

Disable the clock on particular peripheral.

Parameters
[in]clkenrcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 148 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_clock_enable()

void rcc_periph_clock_enable ( enum rcc_periph_clken  clken)

Enable Peripheral Clock in running mode.

Enable the clock on particular peripheral.

Parameters
[in]clkenrcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 134 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by rtc_auto_awake(), rtc_awake_from_off(), rtc_awake_from_standby(), st_usbfs_v1_usbd_init(), and stm32f107_usbd_init().

Here is the caller graph for this function:

◆ rcc_periph_reset_hold()

void rcc_periph_reset_hold ( enum rcc_periph_rst  rst)

Reset Peripheral, hold.

Reset particular peripheral, and hold in reset state.

Parameters
[in]rstrcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 179 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_pulse()

void rcc_periph_reset_pulse ( enum rcc_periph_rst  rst)

Reset Peripheral, pulsed.

Reset particular peripheral, and restore to working state.

Parameters
[in]rstrcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 163 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by can_reset(), i2c_reset(), and spi_reset().

Here is the caller graph for this function:

◆ rcc_periph_reset_release()

void rcc_periph_reset_release ( enum rcc_periph_rst  rst)

Reset Peripheral, release.

Restore peripheral from reset state to working state.

Parameters
[in]rstrcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 194 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_peripheral_clear_reset()

void rcc_peripheral_clear_reset ( volatile uint32_t *  reg,
uint32_t  clear_reset 
)

RCC Remove Reset on Peripherals.

Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.

See also
rcc_periph_reset_release for a less error prone version, if you only need to unreset a single peripheral.
rcc_periph_reset_pulse if you are only going to toggle reset anyway.
Parameters
[in]*regUnsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]clear_resetUnsigned int32. Logical OR of all resets to be removed:

Definition at line 116 of file rcc_common_all.c.

◆ rcc_peripheral_disable_clock()

void rcc_peripheral_disable_clock ( volatile uint32_t *  reg,
uint32_t  en 
)

RCC Disable Peripheral Clocks.

Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.

See also
rcc_periph_clock_disable for a less error prone version, if you only need to disable a single peripheral.
Parameters
[in]*regUnsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]enUnsigned int32. Logical OR of all enables to be used for disabling.

Definition at line 69 of file rcc_common_all.c.

◆ rcc_peripheral_enable_clock()

void rcc_peripheral_enable_clock ( volatile uint32_t *  reg,
uint32_t  en 
)

RCC Enable Peripheral Clocks.

Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.

See also
rcc_periph_clock_enable for a less error prone version, if you only need to enable a single peripheral.
Parameters
[in]*regUnsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]enUnsigned int32. Logical OR of all enables to be set

Definition at line 46 of file rcc_common_all.c.

◆ rcc_peripheral_reset()

void rcc_peripheral_reset ( volatile uint32_t *  reg,
uint32_t  reset 
)

RCC Reset Peripherals.

Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.

See also
rcc_periph_reset_hold for a less error prone version, if you only need to reset a single peripheral.
rcc_periph_reset_pulse if you are only going to toggle reset anyway.
Parameters
[in]*regUnsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]resetUnsigned int32. Logical OR of all resets.

Definition at line 92 of file rcc_common_all.c.

◆ rcc_rtc_clock_enabled_flag()

uint32_t rcc_rtc_clock_enabled_flag ( void  )

RCC RTC Clock Enabled Flag.

Returns
uint32_t. Nonzero if the RTC Clock is enabled.

Definition at line 560 of file rcc.c.

References RCC_BDCR, and RCC_BDCR_RTCEN.

Referenced by rtc_auto_awake().

Here is the caller graph for this function:

◆ rcc_set_adcpre()

void rcc_set_adcpre ( uint32_t  adcpre)

◆ rcc_set_hpre()

◆ rcc_set_mco()

void rcc_set_mco ( uint32_t  mcosrc)

Select the source of Microcontroller Clock Output.

Exact sources available depend on your target. On devices with multiple MCO pins, this function controls MCO1

Parameters
[in]mcosrcthe unshifted source bits

Definition at line 207 of file rcc_common_all.c.

References RCC_CFGR, RCC_CFGR_MCO_MASK, and RCC_CFGR_MCO_SHIFT.

◆ rcc_set_pll2_multiplication_factor()

void rcc_set_pll2_multiplication_factor ( uint32_t  mul)

RCC Set the PLL2 Multiplication Factor.

Note
This only has effect when the PLL is disabled.
Parameters
[in]mulUnsigned int32. PLL multiplication factor RCC_CFGR PLL Multiplication Factor

Definition at line 506 of file rcc.c.

References RCC_CFGR2, RCC_CFGR2_PLL2MUL, and RCC_CFGR2_PLL2MUL_SHIFT.

Referenced by rcc_clock_setup_in_hse_25mhz_out_72mhz(), and rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_set_pll3_multiplication_factor()

void rcc_set_pll3_multiplication_factor ( uint32_t  mul)

RCC Set the PLL3 Multiplication Factor.

Note
This only has effect when the PLL is disabled.
Parameters
[in]mulUnsigned int32. PLL multiplication factor RCC_CFGR PLL Multiplication Factor

Definition at line 520 of file rcc.c.

References RCC_CFGR2, RCC_CFGR2_PLL3MUL, and RCC_CFGR2_PLL3MUL_SHIFT.

Referenced by rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_set_pll_multiplication_factor()

void rcc_set_pll_multiplication_factor ( uint32_t  mul)

RCC Set the PLL Multiplication Factor.

Note
This only has effect when the PLL is disabled.
Parameters
[in]mulUnsigned int32. PLL multiplication factor RCC_CFGR PLL Multiplication Factor

Definition at line 492 of file rcc.c.

References RCC_CFGR, RCC_CFGR_PLLMUL, and RCC_CFGR_PLLMUL_SHIFT.

Referenced by rcc_clock_setup_in_hse_12mhz_out_72mhz(), rcc_clock_setup_in_hse_16mhz_out_72mhz(), rcc_clock_setup_in_hse_25mhz_out_72mhz(), rcc_clock_setup_in_hse_8mhz_out_24mhz(), rcc_clock_setup_in_hse_8mhz_out_72mhz(), rcc_clock_setup_in_hsi_out_24mhz(), rcc_clock_setup_in_hsi_out_48mhz(), rcc_clock_setup_in_hsi_out_64mhz(), and rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_set_pll_source()

void rcc_set_pll_source ( uint32_t  pllsrc)

RCC Set the PLL Clock Source.

Note
This only has effect when the PLL is disabled.
Parameters
[in]pllsrcUnsigned int32. PLL clock source RCC_CFGR PLL Clock Source

Definition at line 534 of file rcc.c.

References RCC_CFGR, and RCC_CFGR_PLLSRC.

Referenced by rcc_clock_setup_in_hse_12mhz_out_72mhz(), rcc_clock_setup_in_hse_16mhz_out_72mhz(), rcc_clock_setup_in_hse_25mhz_out_72mhz(), rcc_clock_setup_in_hse_8mhz_out_24mhz(), rcc_clock_setup_in_hse_8mhz_out_72mhz(), rcc_clock_setup_in_hsi_out_24mhz(), rcc_clock_setup_in_hsi_out_48mhz(), rcc_clock_setup_in_hsi_out_64mhz(), and rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_set_pllxtpre()

void rcc_set_pllxtpre ( uint32_t  pllxtpre)

RCC Set the HSE Frequency Divider used as PLL Clock Source.

Note
This only has effect when the PLL is disabled.
Parameters
[in]pllxtpreUnsigned int32. HSE division factor RCC_CFGR HSE Divider for PLL

Definition at line 548 of file rcc.c.

References RCC_CFGR, and RCC_CFGR_PLLXTPRE.

Referenced by rcc_clock_setup_in_hse_12mhz_out_72mhz(), rcc_clock_setup_in_hse_16mhz_out_72mhz(), rcc_clock_setup_in_hse_25mhz_out_72mhz(), rcc_clock_setup_in_hse_8mhz_out_24mhz(), rcc_clock_setup_in_hse_8mhz_out_72mhz(), and rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_set_ppre1()

void rcc_set_ppre1 ( uint32_t  ppre1)

RCC Set the APB1 Prescale Factor.

Note
The APB1 clock frequency must not exceed 36MHz.
Parameters
[in]ppre1Unsigned int32. APB1 prescale factor rcc_cfgr_apb1pre

Definition at line 658 of file rcc.c.

References rcc_clock_scale::ppre1, RCC_CFGR, RCC_CFGR_PPRE1, and RCC_CFGR_PPRE1_SHIFT.

Referenced by rcc_clock_setup_in_hse_12mhz_out_72mhz(), rcc_clock_setup_in_hse_16mhz_out_72mhz(), rcc_clock_setup_in_hse_25mhz_out_72mhz(), rcc_clock_setup_in_hse_8mhz_out_24mhz(), rcc_clock_setup_in_hse_8mhz_out_72mhz(), rcc_clock_setup_in_hsi_out_24mhz(), rcc_clock_setup_in_hsi_out_48mhz(), rcc_clock_setup_in_hsi_out_64mhz(), and rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_set_ppre2()

void rcc_set_ppre2 ( uint32_t  ppre2)

◆ rcc_set_prediv1()

void rcc_set_prediv1 ( uint32_t  prediv)

Definition at line 698 of file rcc.c.

References RCC_CFGR2, RCC_CFGR2_PREDIV1, and RCC_CFGR2_PREDIV1_SHIFT.

Referenced by rcc_clock_setup_in_hse_25mhz_out_72mhz(), and rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_set_prediv1_source()

void rcc_set_prediv1_source ( uint32_t  rccsrc)

Definition at line 710 of file rcc.c.

References RCC_CFGR2, and RCC_CFGR2_PREDIV1SRC.

Referenced by rcc_clock_setup_in_hse_25mhz_out_72mhz(), and rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_set_prediv2()

void rcc_set_prediv2 ( uint32_t  prediv)

Definition at line 704 of file rcc.c.

References RCC_CFGR2, RCC_CFGR2_PREDIV2, and RCC_CFGR2_PREDIV2_SHIFT.

Referenced by rcc_clock_setup_in_hse_25mhz_out_72mhz(), and rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_set_rtc_clock_source()

void rcc_set_rtc_clock_source ( enum rcc_osc  clock_source)

RCC Set the Source for the RTC clock.

Parameters
[in]clock_sourceRTC clock source. Only HSE/128, LSE and LSI.

Definition at line 581 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSEON, RCC_BDCR_LSERDY, RCC_CR, RCC_CR_HSEON, RCC_CR_HSERDY, RCC_CSR, RCC_CSR_LSION, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_PLL, RCC_PLL2, and RCC_PLL3.

Referenced by rtc_awake_from_off().

Here is the caller graph for this function:

◆ rcc_set_sysclk_source()

void rcc_set_sysclk_source ( uint32_t  clk)

◆ rcc_set_usbpre()

void rcc_set_usbpre ( uint32_t  usbpre)

RCC Set the USB Prescale Factor.

The prescale factor can be set to 1 (no prescale) for use when the PLL clock is 48MHz, or 1.5 to generate the 48MHz USB clock from a 72MHz PLL clock.

Note
This bit cannot be reset while the USB clock is enabled.
Parameters
[in]usbpreUnsigned int32. USB prescale factor RCC_CFGR USB prescale Factors

Definition at line 689 of file rcc.c.

References RCC_CFGR, RCC_CFGR_USBPRE, and rcc_clock_scale::usbpre.

Referenced by rcc_clock_setup_in_hse_25mhz_out_72mhz(), rcc_clock_setup_in_hsi_out_48mhz(), and rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_system_clock_source()

uint32_t rcc_system_clock_source ( void  )

RCC Get the System Clock Source.

Returns
Unsigned int32. System clock source:
  • 00 indicates HSE
  • 01 indicates LSE
  • 02 indicates PLL

Definition at line 728 of file rcc.c.

References RCC_CFGR, RCC_CFGR_SWS, and RCC_CFGR_SWS_SHIFT.

◆ rcc_wait_for_osc_ready()

void rcc_wait_for_osc_ready ( enum rcc_osc  osc)

Wait for Oscillator Ready.

Block until the hardware indicates that the Oscillator is ready.

Parameters
oscOscillator ID

Definition at line 364 of file rcc.c.

References rcc_is_osc_ready().

Referenced by rcc_clock_setup_in_hse_12mhz_out_72mhz(), rcc_clock_setup_in_hse_16mhz_out_72mhz(), rcc_clock_setup_in_hse_25mhz_out_72mhz(), rcc_clock_setup_in_hse_8mhz_out_24mhz(), rcc_clock_setup_in_hse_8mhz_out_72mhz(), rcc_clock_setup_in_hsi_out_24mhz(), rcc_clock_setup_in_hsi_out_48mhz(), rcc_clock_setup_in_hsi_out_64mhz(), and rcc_clock_setup_pll().

Here is the call graph for this function:
Here is the caller graph for this function:

Variable Documentation

◆ rcc_ahb_frequency

◆ rcc_apb1_frequency

◆ rcc_apb2_frequency

◆ rcc_hse_configs

const struct rcc_clock_scale rcc_hse_configs[RCC_CLOCK_HSE_END]
extern

Definition at line 59 of file rcc.c.

◆ rcc_hsi_configs

const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_HSI_END]
extern

Definition at line 59 of file rcc.c.