libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
usb_f107.c
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 *
6 * This library is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public License
17 * along with this library. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <string.h>
24#include <libopencm3/usb/usbd.h>
26#include "usb_private.h"
27#include "usb_dwc_common.h"
28
29/* Receive FIFO size in 32-bit words. */
30#define RX_FIFO_SIZE 128
31
33
34static struct _usbd_device usbd_dev;
35
36const struct _usbd_driver stm32f107_usb_driver = {
37 .init = stm32f107_usbd_init,
38 .set_address = dwc_set_address,
39 .ep_setup = dwc_ep_setup,
40 .ep_reset = dwc_endpoints_reset,
41 .ep_stall_set = dwc_ep_stall_set,
42 .ep_stall_get = dwc_ep_stall_get,
43 .ep_nak_set = dwc_ep_nak_set,
44 .ep_write_packet = dwc_ep_write_packet,
45 .ep_read_packet = dwc_ep_read_packet,
46 .poll = dwc_poll,
47 .disconnect = dwc_disconnect,
48 .base_address = USB_OTG_FS_BASE,
49 .set_address_before_status = 1,
50 .rx_fifo_size = RX_FIFO_SIZE,
51};
52
53/** Initialize the USB device controller hardware of the STM32. */
55{
58
59 /* Wait for AHB idle. */
61 /* Do core soft reset. */
64
66 /* Enable VBUS detection in device mode and power up the PHY. */
68 } else {
69 /* Enable VBUS sensing in device mode and power up the PHY. */
71 }
72 /* Explicitly enable DP pullup (not all cores do this by default) */
73 OTG_FS_DCTL &= ~OTG_DCTL_SDIS;
74
75 /* Force peripheral only mode. */
77
79
80 /* Full speed device. */
82
83 /* Restart the PHY clock. */
85
87 usbd_dev.fifo_mem_top = stm32f107_usb_driver.rx_fifo_size;
88
89 /* Unmask interrupts for TX and RX. */
96 OTG_FS_DAINTMSK = 0xF;
98
99 return &usbd_dev;
100}
void rcc_periph_clock_enable(enum rcc_periph_clken clken)
Enable Peripheral Clock in running mode.
@ RCC_OTGFS
Definition: f1/rcc.h:587
struct _usbd_device usbd_device
Definition: usbd.h:53
const struct _usbd_driver stm32f107_usb_driver
Definition: usb_f107.c:36
#define OTG_GUSBCFG_FDMOD
Definition: otg_common.h:125
#define OTG_DIEPMSK_XFRCM
Definition: otg_common.h:270
#define OTG_GINTMSK_IEPINT
Definition: otg_common.h:188
#define OTG_GRSTCTL_AHBIDL
Definition: otg_common.h:130
#define OTG_GINTMSK_RXFLVLM
Definition: otg_common.h:177
#define OTG_GRSTCTL_CSRST
Definition: otg_common.h:139
#define OTG_GAHBCFG_GINT
Definition: otg_common.h:114
#define OTG_CID_HAS_VBDEN
Definition: otg_common.h:235
#define OTG_GINTMSK_WUIM
Definition: otg_common.h:199
#define OTG_GUSBCFG_PHYSEL
Definition: otg_common.h:127
#define OTG_GCCFG_VBDEN
Only on cores >= 0x2000.
Definition: otg_common.h:226
#define OTG_GCCFG_VBUSBSEN
Definition: otg_common.h:228
#define OTG_DCFG_DSPD
Definition: otg_common.h:251
#define OTG_GINTSTS_MMIS
Definition: otg_common.h:170
#define OTG_GINTMSK_ENUMDNEM
Definition: otg_common.h:184
#define OTG_GUSBCFG_TRDT_MASK
Definition: otg_common.h:122
#define OTG_GCCFG_PWRDWN
Definition: otg_common.h:231
#define OTG_GINTMSK_USBSUSPM
Definition: otg_common.h:182
#define OTG_FS_GINTSTS
Definition: otg_fs.h:47
#define OTG_FS_GRXFSIZ
Definition: otg_fs.h:51
#define OTG_FS_PCGCCTL
Definition: otg_fs.h:97
#define OTG_FS_GINTMSK
Definition: otg_fs.h:48
#define OTG_FS_GCCFG
Definition: otg_fs.h:54
#define OTG_FS_GAHBCFG
Definition: otg_fs.h:44
#define OTG_FS_GUSBCFG
Definition: otg_fs.h:45
#define OTG_FS_DCFG
Definition: otg_fs.h:74
#define OTG_FS_CID
Definition: otg_fs.h:55
#define OTG_FS_DCTL
Definition: otg_fs.h:75
#define OTG_FS_DAINTMSK
Definition: otg_fs.h:80
#define OTG_FS_DIEPMSK
Definition: otg_fs.h:77
#define OTG_FS_GRSTCTL
Definition: otg_fs.h:46
#define USB_OTG_FS_BASE
uint8_t dwc_ep_stall_get(usbd_device *usbd_dev, uint8_t addr)
void dwc_disconnect(usbd_device *usbd_dev, bool disconnected)
void dwc_endpoints_reset(usbd_device *usbd_dev)
uint16_t dwc_ep_write_packet(usbd_device *usbd_dev, uint8_t addr, const void *buf, uint16_t len)
uint16_t dwc_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, void *buf, uint16_t len)
void dwc_set_address(usbd_device *usbd_dev, uint8_t addr)
void dwc_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak)
void dwc_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall)
void dwc_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type, uint16_t max_size, void(*callback)(usbd_device *usbd_dev, uint8_t ep))
void dwc_poll(usbd_device *usbd_dev)
static usbd_device * stm32f107_usbd_init(void)
Initialize the USB device controller hardware of the STM32.
Definition: usb_f107.c:54
#define RX_FIFO_SIZE
Definition: usb_f107.c:30
static struct _usbd_device usbd_dev
Definition: usb_f107.c:34