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#define | TPIU_SSPSR MMIO32(TPIU_BASE + 0x000) |
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#define | TPIU_CSPSR MMIO32(TPIU_BASE + 0x004) |
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#define | TPIU_ACPR MMIO32(TPIU_BASE + 0x010) |
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#define | TPIU_SPPR MMIO32(TPIU_BASE + 0x0F0) |
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#define | TPIU_FFSR MMIO32(TPIU_BASE + 0x300) |
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#define | TPIU_FFCR MMIO32(TPIU_BASE + 0x304) |
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#define | TPIU_DEVID MMIO32(TPIU_BASE + 0xFC8) |
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#define | TPIU_LSR MMIO32(TPIU_BASE + CORESIGHT_LSR_OFFSET) |
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#define | TPIU_LAR MMIO32(TPIU_BASE + CORESIGHT_LAR_OFFSET) |
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#define | TPIU_SPPR_SYNC (0x0) |
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#define | TPIU_SPPR_ASYNC_MANCHESTER (0x1) |
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#define | TPIU_SPPR_ASYNC_NRZ (0x2) |
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#define | TPIU_FFSR_FTNONSTOP (1 << 3) |
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#define | TPIU_FFSR_TCPRESENT (1 << 2) |
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#define | TPIU_FFSR_FTSTOPPED (1 << 1) |
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#define | TPIU_FFSR_FLINPROG (1 << 0) |
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#define | TPIU_FFCR_TRIGIN (1 << 8) |
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#define | TPIU_FFCR_ENFCONT (1 << 1) |
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#define | TPUI_DEVID_NRZ_SUPPORTED (1 << 11) |
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#define | TPUI_DEVID_MANCHESTER_SUPPORTED (1 << 10) |
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#define | TPUI_DEVID_FIFO_SIZE_MASK (7 << 6) |
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